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tegra_ahcisatareg.h revision 1.1 
      1 /* $NetBSD: tegra_ahcisatareg.h,v 1.1 2015/05/15 17:43:35 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_TEGRA_AHCISATAREG_H
     30 #define _ARM_TEGRA_AHCISATAREG_H
     31 
     32 #define TEGRA_SATA_FPCI_BAR5_REG		0x94
     33 
     34 #define TEGRA_SATA_FPCI_BAR_START			__BITS(31,4)
     35 #define TEGRA_SATA_FPCI_BAR_ACCESS_TYPE			__BIT(0)
     36 
     37 #define TEGRA_SATA_CONFIGURATION_REG		0x180
     38 #define TEGRA_SATA_CONFIGURATION_EN_FPCI		__BIT(0)
     39 
     40 #define TEGRA_SATA_INTR_MASK_REG		0x188
     41 #define TEGRA_SATA_INTR_MASK_IP_INT			__BIT(16)
     42 #define TEGRA_SATA_INTR_MASK_MSI			__BIT(8)
     43 #define TEGRA_SATA_INTR_MASK_INT			__BIT(0)
     44 
     45 #define TEGRA_T_SATA0_CFG1_REG			0x1004
     46 #define TEGRA_T_SATA0_CFG1_INTR_DISABLE			__BIT(10)
     47 #define TEGRA_T_SATA0_CFG1_SERR				__BIT(8)
     48 #define TEGRA_T_SATA0_CFG1_BUS_MASTER			__BIT(2)
     49 #define TEGRA_T_SATA0_CFG1_MEM_SPACE			__BIT(1)
     50 #define TEGRA_T_SATA0_CFG1_IO_SPACE			__BIT(0)
     51 
     52 #define TEGRA_T_SATA0_CFG9_REG			0x1024
     53 #define TEGRA_T_SATA0_CFG9_BASE_ADDRESS			__BITS(31,13)
     54 #define TEGRA_T_SATA0_CFG9_SPACE_TYPE			__BIT(0)
     55 
     56 #define TEGRA_T_SATA0_BKDOOR_CC_REG		0x14a4
     57 #define TEGRA_T_SATA0_BKDOOR_CC_CLASS_CODE		__BITS(31,16)
     58 #define TEGRA_T_SATA0_BKDOOR_CC_PROG_IF			__BITS(15,8)
     59 
     60 #define TEGRA_T_SATA0_CFG_POWER_GATE_REG	0x14ac
     61 #define TEGRA_T_SATA0_CFG_POWER_GATE_SSTS_RESTORED	__BIT(23)
     62 
     63 #define TEGRA_T_SATA0_CFG_SATA_REG		0x154c
     64 #define TEGRA_T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN	__BIT(12)
     65 
     66 #define TEGRA_T_SATA0_INDEX_REG			0x1680
     67 #define TEGRA_T_SATA0_INDEX_CH4				__BIT(3)
     68 #define TEGRA_T_SATA0_INDEX_CH3				__BIT(2)
     69 #define TEGRA_T_SATA0_INDEX_CH2				__BIT(1)
     70 #define TEGRA_T_SATA0_INDEX_CH1				__BIT(0)
     71 
     72 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_REG	0x1690
     73 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_DRV_CNTL	__BITS(27,24)
     74 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_PRE	__BITS(23,20)
     75 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_CMADJ	__BITS(19,16)
     76 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK	__BITS(15,8)
     77 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP		__BITS(7,0)
     78 
     79 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_REG	0x1694
     80 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_DRV_CNTL	__BITS(27,24)
     81 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_PRE	__BITS(23,20)
     82 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK	__BITS(19,12)
     83 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_CMADJ	__BITS(11,8)
     84 #define TEGRA_T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP		__BITS(7,0)
     85 
     86 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_REG		0x169c
     87 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN3	__BITS(23,16)
     88 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN2	__BITS(15,8)
     89 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1	__BITS(7,0)
     90 
     91 #define TEGRA_T_SATA0_CHX_PHY_CTRL11_REG	0x16d0
     92 #define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ		__BITS(31,16)
     93 #define TEGRA_T_SATA0_CHX_PHY_CTRL11_GEN1_RX_EQ		__BITS(15,0)
     94 
     95 #endif /* _ARM_TEGRA_AHCISATAREG_H */
     96