1 /* $NetBSD: tegra_cec.c,v 1.11 2021/08/07 16:18:44 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_cec.c,v 1.11 2021/08/07 16:18:44 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 #include <sys/poll.h> 41 #include <sys/select.h> 42 43 #include <dev/hdmicec/hdmicecio.h> 44 #include <dev/hdmicec/hdmicec_if.h> 45 46 #include <arm/nvidia/tegra_var.h> 47 #include <arm/nvidia/tegra_pmcreg.h> 48 #include <arm/nvidia/tegra_cecreg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #define CEC_VENDORID_NVIDIA 0x00044b 53 54 static int tegra_cec_match(device_t, cfdata_t, void *); 55 static void tegra_cec_attach(device_t, device_t, void *); 56 57 static int tegra_cec_intr(void *); 58 59 struct tegra_cec_softc { 60 device_t sc_dev; 61 bus_space_tag_t sc_bst; 62 bus_space_handle_t sc_bsh; 63 void *sc_ih; 64 struct clk *sc_clk; 65 struct fdtbus_reset *sc_rst; 66 67 kmutex_t sc_lock; 68 kcondvar_t sc_cv; 69 70 const char *sc_hdmidevname; 71 device_t sc_cecdev; 72 73 struct selinfo sc_selinfo; 74 75 uint8_t sc_rxbuf[16]; 76 int sc_rxlen; 77 bool sc_rxdone; 78 79 uint8_t sc_txbuf[16]; 80 int sc_txlen; 81 int sc_txcur; 82 int sc_txerr; 83 bool sc_txdone; 84 }; 85 86 static void tegra_cec_reset(struct tegra_cec_softc *); 87 88 static int tegra_cec_open(void *, int); 89 static void tegra_cec_close(void *); 90 static int tegra_cec_ioctl(void *, u_long, void *, int, lwp_t *); 91 static int tegra_cec_send(void *, const uint8_t *, size_t); 92 static ssize_t tegra_cec_recv(void *, uint8_t *, size_t); 93 static int tegra_cec_poll(void *, int, lwp_t *); 94 95 static const struct hdmicec_hw_if tegra_cec_hw_if = { 96 .open = tegra_cec_open, 97 .close = tegra_cec_close, 98 .ioctl = tegra_cec_ioctl, 99 .send = tegra_cec_send, 100 .recv = tegra_cec_recv, 101 .poll = tegra_cec_poll, 102 }; 103 104 CFATTACH_DECL_NEW(tegra_cec, sizeof(struct tegra_cec_softc), 105 tegra_cec_match, tegra_cec_attach, NULL, NULL); 106 107 #define CEC_READ(sc, reg) \ 108 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 109 #define CEC_WRITE(sc, reg, val) \ 110 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 111 #define CEC_SET_CLEAR(sc, reg, set, clr) \ 112 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 113 114 static const struct device_compatible_entry compat_data[] = { 115 { .compat = "nvidia,tegra124-cec" }, 116 DEVICE_COMPAT_EOL 117 }; 118 119 static int 120 tegra_cec_match(device_t parent, cfdata_t cf, void *aux) 121 { 122 struct fdt_attach_args * const faa = aux; 123 124 return of_compatible_match(faa->faa_phandle, compat_data); 125 } 126 127 static void 128 tegra_cec_attach(device_t parent, device_t self, void *aux) 129 { 130 struct tegra_cec_softc * const sc = device_private(self); 131 struct fdt_attach_args * const faa = aux; 132 prop_dictionary_t prop = device_properties(self); 133 struct hdmicec_attach_args caa; 134 char intrstr[128]; 135 bus_addr_t addr; 136 bus_size_t size; 137 int error; 138 139 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 140 aprint_error(": couldn't get registers\n"); 141 return; 142 } 143 sc->sc_clk = fdtbus_clock_get(faa->faa_phandle, "cec"); 144 if (sc->sc_clk == NULL) { 145 aprint_error(": couldn't get clock cec\n"); 146 return; 147 } 148 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "cec"); 149 if (sc->sc_rst == NULL) { 150 aprint_error(": couldn't get reset cec\n"); 151 return; 152 } 153 154 sc->sc_dev = self; 155 sc->sc_bst = faa->faa_bst; 156 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 157 if (error) { 158 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 159 return; 160 } 161 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 162 cv_init(&sc->sc_cv, "tegracec"); 163 selinit(&sc->sc_selinfo); 164 165 aprint_naive("\n"); 166 aprint_normal(": HDMI CEC\n"); 167 168 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 169 aprint_error_dev(self, "failed to decode interrupt\n"); 170 return; 171 } 172 173 sc->sc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, IPL_VM, 174 FDT_INTR_MPSAFE, tegra_cec_intr, sc, device_xname(self)); 175 if (sc->sc_ih == NULL) { 176 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 177 intrstr); 178 return; 179 } 180 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 181 182 prop_dictionary_get_string(prop, "hdmi-device", 183 &sc->sc_hdmidevname); 184 185 fdtbus_reset_assert(sc->sc_rst); 186 error = clk_enable(sc->sc_clk); 187 if (error) { 188 aprint_error_dev(self, "couldn't enable cec: %d\n", error); 189 return; 190 } 191 fdtbus_reset_deassert(sc->sc_rst); 192 193 CEC_WRITE(sc, CEC_SW_CONTROL_REG, 0); 194 CEC_WRITE(sc, CEC_INPUT_FILTER_REG, 0); 195 CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0); 196 CEC_WRITE(sc, CEC_INT_MASK_REG, 0); 197 CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff); 198 199 memset(&caa, 0, sizeof(caa)); 200 caa.priv = sc; 201 caa.hwif = &tegra_cec_hw_if; 202 sc->sc_cecdev = config_found(self, &caa, NULL, CFARGS_NONE); 203 } 204 205 static int 206 tegra_cec_intr(void *priv) 207 { 208 struct tegra_cec_softc * const sc = priv; 209 uint32_t val; 210 int handled = 0; 211 212 mutex_enter(&sc->sc_lock); 213 const uint32_t int_stat = CEC_READ(sc, CEC_INT_STAT_REG); 214 215 if (int_stat & CEC_INT_RX_REGISTER_FULL) { 216 val = CEC_READ(sc, CEC_RX_REGISTER_REG); 217 sc->sc_rxbuf[sc->sc_rxlen++] = 218 __SHIFTOUT(val, CEC_RX_REGISTER_DATA); 219 if ((val & CEC_RX_REGISTER_EOM) != 0 || 220 sc->sc_rxlen == 16) { 221 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0, 222 CEC_INT_RX_REGISTER_FULL); 223 sc->sc_rxdone = true; 224 cv_broadcast(&sc->sc_cv); 225 selnotify(&sc->sc_selinfo, POLLIN|POLLRDNORM, 226 NOTE_SUBMIT); 227 } 228 CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_RX_REGISTER_FULL); 229 ++handled; 230 } 231 232 if (int_stat & CEC_INT_TX_REGISTER_EMPTY) { 233 if (sc->sc_txcur < sc->sc_txlen) { 234 const uint8_t destination = sc->sc_txbuf[0] & 0xf; 235 val = __SHIFTIN(sc->sc_txbuf[sc->sc_txcur], 236 CEC_TX_REGISTER_DATA); 237 if (sc->sc_txcur == 0) 238 val |= CEC_TX_REGISTER_GENERATE_START_BIT; 239 if (sc->sc_txcur == sc->sc_txlen - 1) 240 val |= CEC_TX_REGISTER_EOM; 241 if (destination == 0xf) 242 val |= CEC_TX_REGISTER_ADDRESS_MODE; 243 244 CEC_WRITE(sc, CEC_TX_REGISTER_REG, val); 245 CEC_WRITE(sc, CEC_INT_STAT_REG, 246 CEC_INT_TX_REGISTER_EMPTY); 247 ++sc->sc_txcur; 248 } else { 249 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0, 250 CEC_INT_TX_REGISTER_EMPTY); 251 } 252 ++handled; 253 } 254 255 if (int_stat & CEC_INT_TX_FRAME_TRANSMITTED) { 256 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0, 257 CEC_INT_TX_FRAME_TRANSMITTED | 258 CEC_INT_TX_FRAME_OR_BLOCK_NAKD); 259 CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_TX_FRAME_TRANSMITTED); 260 if (int_stat & CEC_INT_TX_FRAME_OR_BLOCK_NAKD) { 261 CEC_WRITE(sc, CEC_INT_STAT_REG, 262 CEC_INT_TX_FRAME_OR_BLOCK_NAKD); 263 sc->sc_txerr = ECONNREFUSED; 264 tegra_cec_reset(sc); 265 } 266 sc->sc_txdone = true; 267 cv_broadcast(&sc->sc_cv); 268 ++handled; 269 } 270 271 if (int_stat & CEC_INT_TX_REGISTER_UNDERRUN) { 272 tegra_cec_reset(sc); 273 cv_broadcast(&sc->sc_cv); 274 ++handled; 275 } 276 277 mutex_exit(&sc->sc_lock); 278 279 return handled; 280 } 281 282 static void 283 tegra_cec_reset(struct tegra_cec_softc *sc) 284 { 285 uint32_t val; 286 287 KASSERT(mutex_owned(&sc->sc_lock)); 288 289 val = CEC_READ(sc, CEC_HW_CONTROL_REG); 290 CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0); 291 CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff); 292 CEC_WRITE(sc, CEC_HW_CONTROL_REG, val); 293 } 294 295 static int 296 tegra_cec_open(void *priv, int flag) 297 { 298 struct tegra_cec_softc * const sc = priv; 299 300 mutex_enter(&sc->sc_lock); 301 sc->sc_rxlen = 0; 302 sc->sc_rxdone = false; 303 CEC_WRITE(sc, CEC_INT_MASK_REG, CEC_INT_RX_REGISTER_FULL); 304 CEC_WRITE(sc, CEC_HW_CONTROL_REG, CEC_HW_CONTROL_TX_RX_MODE); 305 mutex_exit(&sc->sc_lock); 306 307 return 0; 308 } 309 310 static void 311 tegra_cec_close(void *priv) 312 { 313 struct tegra_cec_softc * const sc = priv; 314 315 mutex_enter(&sc->sc_lock); 316 CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0); 317 CEC_WRITE(sc, CEC_INT_MASK_REG, 0); 318 CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff); 319 mutex_exit(&sc->sc_lock); 320 } 321 322 static int 323 tegra_cec_get_phys_addr(struct tegra_cec_softc *sc, uint16_t *phys_addr) 324 { 325 device_t hdmidev; 326 327 if (sc->sc_hdmidevname == NULL) 328 return EIO; 329 hdmidev = device_find_by_xname(sc->sc_hdmidevname); 330 if (hdmidev == NULL) 331 return ENXIO; 332 333 const prop_dictionary_t prop = device_properties(hdmidev); 334 if (!prop_dictionary_get_uint16(prop, "physical-address", phys_addr)) 335 return ENOTCONN; 336 337 return 0; 338 } 339 340 static int 341 tegra_cec_ioctl(void *priv, u_long cmd, void *data, int flag, lwp_t *l) 342 { 343 struct tegra_cec_softc * const sc = priv; 344 uint32_t val; 345 346 switch (cmd) { 347 case CEC_GET_PHYS_ADDR: 348 return tegra_cec_get_phys_addr(sc, data); 349 case CEC_GET_LOG_ADDRS: 350 val = CEC_READ(sc, CEC_HW_CONTROL_REG); 351 *(uint16_t *)data = 352 __SHIFTOUT(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS); 353 return 0; 354 case CEC_SET_LOG_ADDRS: 355 val = *(uint16_t *)data & 0x7fff; 356 CEC_SET_CLEAR(sc, CEC_HW_CONTROL_REG, 357 __SHIFTIN(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS), 358 CEC_HW_CONTROL_RX_LOGICAL_ADDRS); 359 return 0; 360 case CEC_GET_VENDOR_ID: 361 *(uint32_t *)data = CEC_VENDORID_NVIDIA; 362 return 0; 363 default: 364 return EINVAL; 365 } 366 } 367 368 static int 369 tegra_cec_send(void *priv, const uint8_t *data, size_t len) 370 { 371 struct tegra_cec_softc * const sc = priv; 372 int error = 0; 373 374 mutex_enter(&sc->sc_lock); 375 376 sc->sc_txdone = false; 377 sc->sc_txcur = 0; 378 sc->sc_txerr = 0; 379 memcpy(sc->sc_txbuf, data, len); 380 sc->sc_txlen = len; 381 382 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 383 CEC_INT_TX_REGISTER_EMPTY | 384 CEC_INT_TX_FRAME_TRANSMITTED | 385 CEC_INT_TX_FRAME_OR_BLOCK_NAKD, 0); 386 387 while (sc->sc_txdone == false) { 388 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, hz); 389 if (error) 390 break; 391 } 392 393 if (sc->sc_txdone) 394 error = sc->sc_txerr; 395 396 mutex_exit(&sc->sc_lock); 397 398 return error; 399 } 400 401 static ssize_t 402 tegra_cec_recv(void *priv, uint8_t *data, size_t len) 403 { 404 struct tegra_cec_softc * const sc = priv; 405 ssize_t alen = -1; 406 int error = 0; 407 408 mutex_enter(&sc->sc_lock); 409 410 while (sc->sc_rxdone == false) { 411 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, hz); 412 if (error) 413 break; 414 } 415 416 if (sc->sc_rxdone) { 417 memcpy(data, sc->sc_rxbuf, sc->sc_rxlen); 418 alen = sc->sc_rxlen; 419 sc->sc_rxlen = 0; 420 sc->sc_rxdone = false; 421 } 422 423 mutex_exit(&sc->sc_lock); 424 425 return alen; 426 } 427 428 static int 429 tegra_cec_poll(void *priv, int events, lwp_t *l) 430 { 431 struct tegra_cec_softc * const sc = priv; 432 int revents; 433 434 revents = events & (POLLOUT | POLLWRNORM); 435 436 if ((events & (POLLIN | POLLRDNORM)) == 0) 437 return revents; 438 439 mutex_enter(&sc->sc_lock); 440 if (sc->sc_rxdone) { 441 revents = (events & (POLLIN | POLLRDNORM)); 442 } else { 443 selrecord(l, &sc->sc_selinfo); 444 revents = 0; 445 } 446 mutex_exit(&sc->sc_lock); 447 448 return revents; 449 } 450
Indexes created Sat Sep 20 22:09:52 GMT 2025