tegra_cec.c revision 1.2
1 /* $NetBSD: tegra_cec.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_cec.c,v 1.2 2015/12/13 17:39:19 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 #include <sys/poll.h> 41 #include <sys/select.h> 42 43 #include <dev/hdmicec/hdmicecio.h> 44 #include <dev/hdmicec/hdmicec_if.h> 45 46 #include <arm/nvidia/tegra_var.h> 47 #include <arm/nvidia/tegra_pmcreg.h> 48 #include <arm/nvidia/tegra_cecreg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #define CEC_VENDORID_NVIDIA 0x00044b 53 54 static int tegra_cec_match(device_t, cfdata_t, void *); 55 static void tegra_cec_attach(device_t, device_t, void *); 56 57 static int tegra_cec_intr(void *); 58 59 struct tegra_cec_softc { 60 device_t sc_dev; 61 bus_space_tag_t sc_bst; 62 bus_space_handle_t sc_bsh; 63 void *sc_ih; 64 65 kmutex_t sc_lock; 66 kcondvar_t sc_cv; 67 68 const char *sc_hdmidevname; 69 device_t sc_cecdev; 70 71 struct selinfo sc_selinfo; 72 73 uint8_t sc_rxbuf[16]; 74 int sc_rxlen; 75 bool sc_rxdone; 76 77 uint8_t sc_txbuf[16]; 78 int sc_txlen; 79 int sc_txcur; 80 int sc_txerr; 81 bool sc_txdone; 82 }; 83 84 static void tegra_cec_reset(struct tegra_cec_softc *); 85 86 static int tegra_cec_open(void *, int); 87 static void tegra_cec_close(void *); 88 static int tegra_cec_ioctl(void *, u_long, void *, int, lwp_t *); 89 static int tegra_cec_send(void *, const uint8_t *, size_t); 90 static ssize_t tegra_cec_recv(void *, uint8_t *, size_t); 91 static int tegra_cec_poll(void *, int, lwp_t *); 92 93 static const struct hdmicec_hw_if tegra_cec_hw_if = { 94 .open = tegra_cec_open, 95 .close = tegra_cec_close, 96 .ioctl = tegra_cec_ioctl, 97 .send = tegra_cec_send, 98 .recv = tegra_cec_recv, 99 .poll = tegra_cec_poll, 100 }; 101 102 CFATTACH_DECL_NEW(tegra_cec, sizeof(struct tegra_cec_softc), 103 tegra_cec_match, tegra_cec_attach, NULL, NULL); 104 105 #define CEC_READ(sc, reg) \ 106 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 107 #define CEC_WRITE(sc, reg, val) \ 108 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 109 #define CEC_SET_CLEAR(sc, reg, set, clr) \ 110 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 111 112 static int 113 tegra_cec_match(device_t parent, cfdata_t cf, void *aux) 114 { 115 const char * const compatible[] = { "nvidia,tegra124-cec", NULL }; 116 struct fdt_attach_args * const faa = aux; 117 118 return of_match_compatible(faa->faa_phandle, compatible); 119 } 120 121 static void 122 tegra_cec_attach(device_t parent, device_t self, void *aux) 123 { 124 struct tegra_cec_softc * const sc = device_private(self); 125 struct fdt_attach_args * const faa = aux; 126 prop_dictionary_t prop = device_properties(self); 127 struct hdmicec_attach_args caa; 128 char intrstr[128]; 129 bus_addr_t addr; 130 bus_size_t size; 131 int error; 132 133 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 134 aprint_error(": couldn't get registers\n"); 135 return; 136 } 137 138 sc->sc_dev = self; 139 sc->sc_bst = faa->faa_bst; 140 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 141 if (error) { 142 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 143 return; 144 } 145 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 146 cv_init(&sc->sc_cv, "tegracec"); 147 selinit(&sc->sc_selinfo); 148 149 aprint_naive("\n"); 150 aprint_normal(": HDMI CEC\n"); 151 152 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 153 aprint_error_dev(self, "failed to decode interrupt\n"); 154 return; 155 } 156 157 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 158 FDT_INTR_MPSAFE, tegra_cec_intr, sc); 159 if (sc->sc_ih == NULL) { 160 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 161 intrstr); 162 return; 163 } 164 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 165 166 prop_dictionary_get_cstring_nocopy(prop, "hdmi-device", 167 &sc->sc_hdmidevname); 168 169 tegra_car_periph_cec_enable(); 170 171 CEC_WRITE(sc, CEC_SW_CONTROL_REG, 0); 172 CEC_WRITE(sc, CEC_INPUT_FILTER_REG, 0); 173 CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0); 174 CEC_WRITE(sc, CEC_INT_MASK_REG, 0); 175 CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff); 176 177 memset(&caa, 0, sizeof(caa)); 178 caa.priv = sc; 179 caa.hwif = &tegra_cec_hw_if; 180 sc->sc_cecdev = config_found(self, &caa, NULL); 181 } 182 183 static int 184 tegra_cec_intr(void *priv) 185 { 186 struct tegra_cec_softc * const sc = priv; 187 uint32_t val; 188 int handled = 0; 189 190 mutex_enter(&sc->sc_lock); 191 const uint32_t int_stat = CEC_READ(sc, CEC_INT_STAT_REG); 192 193 if (int_stat & CEC_INT_RX_REGISTER_FULL) { 194 val = CEC_READ(sc, CEC_RX_REGISTER_REG); 195 sc->sc_rxbuf[sc->sc_rxlen++] = 196 __SHIFTOUT(val, CEC_RX_REGISTER_DATA); 197 if ((val & CEC_RX_REGISTER_EOM) != 0 || 198 sc->sc_rxlen == 16) { 199 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0, 200 CEC_INT_RX_REGISTER_FULL); 201 sc->sc_rxdone = true; 202 cv_broadcast(&sc->sc_cv); 203 selnotify(&sc->sc_selinfo, POLLIN|POLLRDNORM, 204 NOTE_SUBMIT); 205 } 206 CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_RX_REGISTER_FULL); 207 ++handled; 208 } 209 210 if (int_stat & CEC_INT_TX_REGISTER_EMPTY) { 211 if (sc->sc_txcur < sc->sc_txlen) { 212 const uint8_t destination = sc->sc_txbuf[0] & 0xf; 213 val = __SHIFTIN(sc->sc_txbuf[sc->sc_txcur], 214 CEC_TX_REGISTER_DATA); 215 if (sc->sc_txcur == 0) 216 val |= CEC_TX_REGISTER_GENERATE_START_BIT; 217 if (sc->sc_txcur == sc->sc_txlen - 1) 218 val |= CEC_TX_REGISTER_EOM; 219 if (destination == 0xf) 220 val |= CEC_TX_REGISTER_ADDRESS_MODE; 221 222 CEC_WRITE(sc, CEC_TX_REGISTER_REG, val); 223 CEC_WRITE(sc, CEC_INT_STAT_REG, 224 CEC_INT_TX_REGISTER_EMPTY); 225 ++sc->sc_txcur; 226 } else { 227 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0, 228 CEC_INT_TX_REGISTER_EMPTY); 229 } 230 ++handled; 231 } 232 233 if (int_stat & CEC_INT_TX_FRAME_TRANSMITTED) { 234 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0, 235 CEC_INT_TX_FRAME_TRANSMITTED | 236 CEC_INT_TX_FRAME_OR_BLOCK_NAKD); 237 CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_TX_FRAME_TRANSMITTED); 238 if (int_stat & CEC_INT_TX_FRAME_OR_BLOCK_NAKD) { 239 CEC_WRITE(sc, CEC_INT_STAT_REG, 240 CEC_INT_TX_FRAME_OR_BLOCK_NAKD); 241 sc->sc_txerr = ECONNREFUSED; 242 tegra_cec_reset(sc); 243 } 244 sc->sc_txdone = true; 245 cv_broadcast(&sc->sc_cv); 246 ++handled; 247 } 248 249 if (int_stat & CEC_INT_TX_REGISTER_UNDERRUN) { 250 tegra_cec_reset(sc); 251 cv_broadcast(&sc->sc_cv); 252 ++handled; 253 } 254 255 mutex_exit(&sc->sc_lock); 256 257 return handled; 258 } 259 260 static void 261 tegra_cec_reset(struct tegra_cec_softc *sc) 262 { 263 uint32_t val; 264 265 KASSERT(mutex_owned(&sc->sc_lock)); 266 267 val = CEC_READ(sc, CEC_HW_CONTROL_REG); 268 CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0); 269 CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff); 270 CEC_WRITE(sc, CEC_HW_CONTROL_REG, val); 271 } 272 273 static int 274 tegra_cec_open(void *priv, int flag) 275 { 276 struct tegra_cec_softc * const sc = priv; 277 278 mutex_enter(&sc->sc_lock); 279 sc->sc_rxlen = 0; 280 sc->sc_rxdone = false; 281 CEC_WRITE(sc, CEC_INT_MASK_REG, CEC_INT_RX_REGISTER_FULL); 282 CEC_WRITE(sc, CEC_HW_CONTROL_REG, CEC_HW_CONTROL_TX_RX_MODE); 283 mutex_exit(&sc->sc_lock); 284 285 return 0; 286 } 287 288 static void 289 tegra_cec_close(void *priv) 290 { 291 struct tegra_cec_softc * const sc = priv; 292 293 mutex_enter(&sc->sc_lock); 294 CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0); 295 CEC_WRITE(sc, CEC_INT_MASK_REG, 0); 296 CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff); 297 mutex_exit(&sc->sc_lock); 298 } 299 300 static int 301 tegra_cec_get_phys_addr(struct tegra_cec_softc *sc, uint16_t *phys_addr) 302 { 303 device_t hdmidev; 304 305 if (sc->sc_hdmidevname == NULL) 306 return EIO; 307 hdmidev = device_find_by_xname(sc->sc_hdmidevname); 308 if (hdmidev == NULL) 309 return ENXIO; 310 311 const prop_dictionary_t prop = device_properties(hdmidev); 312 if (!prop_dictionary_get_uint16(prop, "physical-address", phys_addr)) 313 return ENOTCONN; 314 315 return 0; 316 } 317 318 static int 319 tegra_cec_ioctl(void *priv, u_long cmd, void *data, int flag, lwp_t *l) 320 { 321 struct tegra_cec_softc * const sc = priv; 322 uint32_t val; 323 324 switch (cmd) { 325 case CEC_GET_PHYS_ADDR: 326 return tegra_cec_get_phys_addr(sc, data); 327 case CEC_GET_LOG_ADDRS: 328 val = CEC_READ(sc, CEC_HW_CONTROL_REG); 329 *(uint16_t *)data = 330 __SHIFTOUT(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS); 331 return 0; 332 case CEC_SET_LOG_ADDRS: 333 val = *(uint16_t *)data & 0x7fff; 334 CEC_SET_CLEAR(sc, CEC_HW_CONTROL_REG, 335 __SHIFTIN(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS), 336 CEC_HW_CONTROL_RX_LOGICAL_ADDRS); 337 return 0; 338 case CEC_GET_VENDOR_ID: 339 *(uint32_t *)data = CEC_VENDORID_NVIDIA; 340 return 0; 341 default: 342 return EINVAL; 343 } 344 } 345 346 static int 347 tegra_cec_send(void *priv, const uint8_t *data, size_t len) 348 { 349 struct tegra_cec_softc * const sc = priv; 350 int error = 0; 351 352 mutex_enter(&sc->sc_lock); 353 354 sc->sc_txdone = false; 355 sc->sc_txcur = 0; 356 sc->sc_txerr = 0; 357 memcpy(sc->sc_txbuf, data, len); 358 sc->sc_txlen = len; 359 360 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 361 CEC_INT_TX_REGISTER_EMPTY | 362 CEC_INT_TX_FRAME_TRANSMITTED | 363 CEC_INT_TX_FRAME_OR_BLOCK_NAKD, 0); 364 365 while (sc->sc_txdone == false) { 366 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, hz); 367 if (error) 368 break; 369 } 370 371 if (sc->sc_txdone) 372 error = sc->sc_txerr; 373 374 mutex_exit(&sc->sc_lock); 375 376 return error; 377 } 378 379 static ssize_t 380 tegra_cec_recv(void *priv, uint8_t *data, size_t len) 381 { 382 struct tegra_cec_softc * const sc = priv; 383 ssize_t alen = -1; 384 int error = 0; 385 386 mutex_enter(&sc->sc_lock); 387 388 while (sc->sc_rxdone == false) { 389 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, hz); 390 if (error) 391 break; 392 } 393 394 if (sc->sc_rxdone) { 395 memcpy(data, sc->sc_rxbuf, sc->sc_rxlen); 396 alen = sc->sc_rxlen; 397 sc->sc_rxlen = 0; 398 sc->sc_rxdone = false; 399 } 400 401 mutex_exit(&sc->sc_lock); 402 403 return alen; 404 } 405 406 static int 407 tegra_cec_poll(void *priv, int events, lwp_t *l) 408 { 409 struct tegra_cec_softc * const sc = priv; 410 int revents; 411 412 revents = events & (POLLOUT | POLLWRNORM); 413 414 if ((events & (POLLIN | POLLRDNORM)) == 0) 415 return revents; 416 417 mutex_enter(&sc->sc_lock); 418 if (sc->sc_rxdone) { 419 revents = (events & (POLLIN | POLLRDNORM)); 420 } else { 421 selrecord(l, &sc->sc_selinfo); 422 revents = 0; 423 } 424 mutex_exit(&sc->sc_lock); 425 426 return revents; 427 } 428
Indexes created Tue Sep 23 14:10:03 GMT 2025