tegra_cec.c revision 1.6
1 /* $NetBSD: tegra_cec.c,v 1.6 2019/10/13 06:11:31 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_cec.c,v 1.6 2019/10/13 06:11:31 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 #include <sys/poll.h> 41 #include <sys/select.h> 42 43 #include <dev/hdmicec/hdmicecio.h> 44 #include <dev/hdmicec/hdmicec_if.h> 45 46 #include <arm/nvidia/tegra_var.h> 47 #include <arm/nvidia/tegra_pmcreg.h> 48 #include <arm/nvidia/tegra_cecreg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #define CEC_VENDORID_NVIDIA 0x00044b 53 54 static int tegra_cec_match(device_t, cfdata_t, void *); 55 static void tegra_cec_attach(device_t, device_t, void *); 56 57 static int tegra_cec_intr(void *); 58 59 struct tegra_cec_softc { 60 device_t sc_dev; 61 bus_space_tag_t sc_bst; 62 bus_space_handle_t sc_bsh; 63 void *sc_ih; 64 struct clk *sc_clk; 65 struct fdtbus_reset *sc_rst; 66 67 kmutex_t sc_lock; 68 kcondvar_t sc_cv; 69 70 const char *sc_hdmidevname; 71 device_t sc_cecdev; 72 73 struct selinfo sc_selinfo; 74 75 uint8_t sc_rxbuf[16]; 76 int sc_rxlen; 77 bool sc_rxdone; 78 79 uint8_t sc_txbuf[16]; 80 int sc_txlen; 81 int sc_txcur; 82 int sc_txerr; 83 bool sc_txdone; 84 }; 85 86 static void tegra_cec_reset(struct tegra_cec_softc *); 87 88 static int tegra_cec_open(void *, int); 89 static void tegra_cec_close(void *); 90 static int tegra_cec_ioctl(void *, u_long, void *, int, lwp_t *); 91 static int tegra_cec_send(void *, const uint8_t *, size_t); 92 static ssize_t tegra_cec_recv(void *, uint8_t *, size_t); 93 static int tegra_cec_poll(void *, int, lwp_t *); 94 95 static const struct hdmicec_hw_if tegra_cec_hw_if = { 96 .open = tegra_cec_open, 97 .close = tegra_cec_close, 98 .ioctl = tegra_cec_ioctl, 99 .send = tegra_cec_send, 100 .recv = tegra_cec_recv, 101 .poll = tegra_cec_poll, 102 }; 103 104 CFATTACH_DECL_NEW(tegra_cec, sizeof(struct tegra_cec_softc), 105 tegra_cec_match, tegra_cec_attach, NULL, NULL); 106 107 #define CEC_READ(sc, reg) \ 108 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 109 #define CEC_WRITE(sc, reg, val) \ 110 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 111 #define CEC_SET_CLEAR(sc, reg, set, clr) \ 112 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 113 114 static int 115 tegra_cec_match(device_t parent, cfdata_t cf, void *aux) 116 { 117 const char * const compatible[] = { "nvidia,tegra124-cec", NULL }; 118 struct fdt_attach_args * const faa = aux; 119 120 return of_match_compatible(faa->faa_phandle, compatible); 121 } 122 123 static void 124 tegra_cec_attach(device_t parent, device_t self, void *aux) 125 { 126 struct tegra_cec_softc * const sc = device_private(self); 127 struct fdt_attach_args * const faa = aux; 128 prop_dictionary_t prop = device_properties(self); 129 struct hdmicec_attach_args caa; 130 char intrstr[128]; 131 bus_addr_t addr; 132 bus_size_t size; 133 int error; 134 135 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 136 aprint_error(": couldn't get registers\n"); 137 return; 138 } 139 sc->sc_clk = fdtbus_clock_get(faa->faa_phandle, "cec"); 140 if (sc->sc_clk == NULL) { 141 aprint_error(": couldn't get clock cec\n"); 142 return; 143 } 144 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "cec"); 145 if (sc->sc_rst == NULL) { 146 aprint_error(": couldn't get reset cec\n"); 147 return; 148 } 149 150 sc->sc_dev = self; 151 sc->sc_bst = faa->faa_bst; 152 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 153 if (error) { 154 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 155 return; 156 } 157 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 158 cv_init(&sc->sc_cv, "tegracec"); 159 selinit(&sc->sc_selinfo); 160 161 aprint_naive("\n"); 162 aprint_normal(": HDMI CEC\n"); 163 164 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 165 aprint_error_dev(self, "failed to decode interrupt\n"); 166 return; 167 } 168 169 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_VM, 170 FDT_INTR_MPSAFE, tegra_cec_intr, sc); 171 if (sc->sc_ih == NULL) { 172 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 173 intrstr); 174 return; 175 } 176 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 177 178 prop_dictionary_get_cstring_nocopy(prop, "hdmi-device", 179 &sc->sc_hdmidevname); 180 181 fdtbus_reset_assert(sc->sc_rst); 182 error = clk_enable(sc->sc_clk); 183 if (error) { 184 aprint_error_dev(self, "couldn't enable cec: %d\n", error); 185 return; 186 } 187 fdtbus_reset_deassert(sc->sc_rst); 188 189 CEC_WRITE(sc, CEC_SW_CONTROL_REG, 0); 190 CEC_WRITE(sc, CEC_INPUT_FILTER_REG, 0); 191 CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0); 192 CEC_WRITE(sc, CEC_INT_MASK_REG, 0); 193 CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff); 194 195 memset(&caa, 0, sizeof(caa)); 196 caa.priv = sc; 197 caa.hwif = &tegra_cec_hw_if; 198 sc->sc_cecdev = config_found(self, &caa, NULL); 199 } 200 201 static int 202 tegra_cec_intr(void *priv) 203 { 204 struct tegra_cec_softc * const sc = priv; 205 uint32_t val; 206 int handled = 0; 207 208 mutex_enter(&sc->sc_lock); 209 const uint32_t int_stat = CEC_READ(sc, CEC_INT_STAT_REG); 210 211 if (int_stat & CEC_INT_RX_REGISTER_FULL) { 212 val = CEC_READ(sc, CEC_RX_REGISTER_REG); 213 sc->sc_rxbuf[sc->sc_rxlen++] = 214 __SHIFTOUT(val, CEC_RX_REGISTER_DATA); 215 if ((val & CEC_RX_REGISTER_EOM) != 0 || 216 sc->sc_rxlen == 16) { 217 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0, 218 CEC_INT_RX_REGISTER_FULL); 219 sc->sc_rxdone = true; 220 cv_broadcast(&sc->sc_cv); 221 selnotify(&sc->sc_selinfo, POLLIN|POLLRDNORM, 222 NOTE_SUBMIT); 223 } 224 CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_RX_REGISTER_FULL); 225 ++handled; 226 } 227 228 if (int_stat & CEC_INT_TX_REGISTER_EMPTY) { 229 if (sc->sc_txcur < sc->sc_txlen) { 230 const uint8_t destination = sc->sc_txbuf[0] & 0xf; 231 val = __SHIFTIN(sc->sc_txbuf[sc->sc_txcur], 232 CEC_TX_REGISTER_DATA); 233 if (sc->sc_txcur == 0) 234 val |= CEC_TX_REGISTER_GENERATE_START_BIT; 235 if (sc->sc_txcur == sc->sc_txlen - 1) 236 val |= CEC_TX_REGISTER_EOM; 237 if (destination == 0xf) 238 val |= CEC_TX_REGISTER_ADDRESS_MODE; 239 240 CEC_WRITE(sc, CEC_TX_REGISTER_REG, val); 241 CEC_WRITE(sc, CEC_INT_STAT_REG, 242 CEC_INT_TX_REGISTER_EMPTY); 243 ++sc->sc_txcur; 244 } else { 245 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0, 246 CEC_INT_TX_REGISTER_EMPTY); 247 } 248 ++handled; 249 } 250 251 if (int_stat & CEC_INT_TX_FRAME_TRANSMITTED) { 252 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 0, 253 CEC_INT_TX_FRAME_TRANSMITTED | 254 CEC_INT_TX_FRAME_OR_BLOCK_NAKD); 255 CEC_WRITE(sc, CEC_INT_STAT_REG, CEC_INT_TX_FRAME_TRANSMITTED); 256 if (int_stat & CEC_INT_TX_FRAME_OR_BLOCK_NAKD) { 257 CEC_WRITE(sc, CEC_INT_STAT_REG, 258 CEC_INT_TX_FRAME_OR_BLOCK_NAKD); 259 sc->sc_txerr = ECONNREFUSED; 260 tegra_cec_reset(sc); 261 } 262 sc->sc_txdone = true; 263 cv_broadcast(&sc->sc_cv); 264 ++handled; 265 } 266 267 if (int_stat & CEC_INT_TX_REGISTER_UNDERRUN) { 268 tegra_cec_reset(sc); 269 cv_broadcast(&sc->sc_cv); 270 ++handled; 271 } 272 273 mutex_exit(&sc->sc_lock); 274 275 return handled; 276 } 277 278 static void 279 tegra_cec_reset(struct tegra_cec_softc *sc) 280 { 281 uint32_t val; 282 283 KASSERT(mutex_owned(&sc->sc_lock)); 284 285 val = CEC_READ(sc, CEC_HW_CONTROL_REG); 286 CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0); 287 CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff); 288 CEC_WRITE(sc, CEC_HW_CONTROL_REG, val); 289 } 290 291 static int 292 tegra_cec_open(void *priv, int flag) 293 { 294 struct tegra_cec_softc * const sc = priv; 295 296 mutex_enter(&sc->sc_lock); 297 sc->sc_rxlen = 0; 298 sc->sc_rxdone = false; 299 CEC_WRITE(sc, CEC_INT_MASK_REG, CEC_INT_RX_REGISTER_FULL); 300 CEC_WRITE(sc, CEC_HW_CONTROL_REG, CEC_HW_CONTROL_TX_RX_MODE); 301 mutex_exit(&sc->sc_lock); 302 303 return 0; 304 } 305 306 static void 307 tegra_cec_close(void *priv) 308 { 309 struct tegra_cec_softc * const sc = priv; 310 311 mutex_enter(&sc->sc_lock); 312 CEC_WRITE(sc, CEC_HW_CONTROL_REG, 0); 313 CEC_WRITE(sc, CEC_INT_MASK_REG, 0); 314 CEC_WRITE(sc, CEC_INT_STAT_REG, 0xffffffff); 315 mutex_exit(&sc->sc_lock); 316 } 317 318 static int 319 tegra_cec_get_phys_addr(struct tegra_cec_softc *sc, uint16_t *phys_addr) 320 { 321 device_t hdmidev; 322 323 if (sc->sc_hdmidevname == NULL) 324 return EIO; 325 hdmidev = device_find_by_xname(sc->sc_hdmidevname); 326 if (hdmidev == NULL) 327 return ENXIO; 328 329 const prop_dictionary_t prop = device_properties(hdmidev); 330 if (!prop_dictionary_get_uint16(prop, "physical-address", phys_addr)) 331 return ENOTCONN; 332 333 return 0; 334 } 335 336 static int 337 tegra_cec_ioctl(void *priv, u_long cmd, void *data, int flag, lwp_t *l) 338 { 339 struct tegra_cec_softc * const sc = priv; 340 uint32_t val; 341 342 switch (cmd) { 343 case CEC_GET_PHYS_ADDR: 344 return tegra_cec_get_phys_addr(sc, data); 345 case CEC_GET_LOG_ADDRS: 346 val = CEC_READ(sc, CEC_HW_CONTROL_REG); 347 *(uint16_t *)data = 348 __SHIFTOUT(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS); 349 return 0; 350 case CEC_SET_LOG_ADDRS: 351 val = *(uint16_t *)data & 0x7fff; 352 CEC_SET_CLEAR(sc, CEC_HW_CONTROL_REG, 353 __SHIFTIN(val, CEC_HW_CONTROL_RX_LOGICAL_ADDRS), 354 CEC_HW_CONTROL_RX_LOGICAL_ADDRS); 355 return 0; 356 case CEC_GET_VENDOR_ID: 357 *(uint32_t *)data = CEC_VENDORID_NVIDIA; 358 return 0; 359 default: 360 return EINVAL; 361 } 362 } 363 364 static int 365 tegra_cec_send(void *priv, const uint8_t *data, size_t len) 366 { 367 struct tegra_cec_softc * const sc = priv; 368 int error = 0; 369 370 mutex_enter(&sc->sc_lock); 371 372 sc->sc_txdone = false; 373 sc->sc_txcur = 0; 374 sc->sc_txerr = 0; 375 memcpy(sc->sc_txbuf, data, len); 376 sc->sc_txlen = len; 377 378 CEC_SET_CLEAR(sc, CEC_INT_MASK_REG, 379 CEC_INT_TX_REGISTER_EMPTY | 380 CEC_INT_TX_FRAME_TRANSMITTED | 381 CEC_INT_TX_FRAME_OR_BLOCK_NAKD, 0); 382 383 while (sc->sc_txdone == false) { 384 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, hz); 385 if (error) 386 break; 387 } 388 389 if (sc->sc_txdone) 390 error = sc->sc_txerr; 391 392 mutex_exit(&sc->sc_lock); 393 394 return error; 395 } 396 397 static ssize_t 398 tegra_cec_recv(void *priv, uint8_t *data, size_t len) 399 { 400 struct tegra_cec_softc * const sc = priv; 401 ssize_t alen = -1; 402 int error = 0; 403 404 mutex_enter(&sc->sc_lock); 405 406 while (sc->sc_rxdone == false) { 407 error = cv_timedwait_sig(&sc->sc_cv, &sc->sc_lock, hz); 408 if (error) 409 break; 410 } 411 412 if (sc->sc_rxdone) { 413 memcpy(data, sc->sc_rxbuf, sc->sc_rxlen); 414 alen = sc->sc_rxlen; 415 sc->sc_rxlen = 0; 416 sc->sc_rxdone = false; 417 } 418 419 mutex_exit(&sc->sc_lock); 420 421 return alen; 422 } 423 424 static int 425 tegra_cec_poll(void *priv, int events, lwp_t *l) 426 { 427 struct tegra_cec_softc * const sc = priv; 428 int revents; 429 430 revents = events & (POLLOUT | POLLWRNORM); 431 432 if ((events & (POLLIN | POLLRDNORM)) == 0) 433 return revents; 434 435 mutex_enter(&sc->sc_lock); 436 if (sc->sc_rxdone) { 437 revents = (events & (POLLIN | POLLRDNORM)); 438 } else { 439 selrecord(l, &sc->sc_selinfo); 440 revents = 0; 441 } 442 mutex_exit(&sc->sc_lock); 443 444 return revents; 445 } 446
Indexes created Thu Sep 25 08:09:54 GMT 2025