1 /* $NetBSD: tegra_com.c,v 1.16 2025/09/06 22:53:47 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: tegra_com.c,v 1.16 2025/09/06 22:53:47 thorpej Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/time.h> 42 #include <sys/termios.h> 43 44 #include <arm/nvidia/tegra_reg.h> 45 #include <arm/nvidia/tegra_var.h> 46 47 #include <dev/ic/comvar.h> 48 49 #include <dev/fdt/fdtvar.h> 50 #include <dev/fdt/fdt_console.h> 51 52 static int tegra_com_match(device_t, cfdata_t, void *); 53 static void tegra_com_attach(device_t, device_t, void *); 54 55 static const struct device_compatible_entry compat_data[] = { 56 { .compat = "nvidia,tegra210-uart" }, 57 { .compat = "nvidia,tegra124-uart" }, 58 { .compat = "nvidia,tegra20-uart" }, 59 DEVICE_COMPAT_EOL 60 }; 61 62 struct tegra_com_softc { 63 struct com_softc tsc_sc; 64 void *tsc_ih; 65 66 struct clk *tsc_clk; 67 struct fdtbus_reset *tsc_rst; 68 }; 69 70 CFATTACH_DECL_NEW(tegra_com, sizeof(struct tegra_com_softc), 71 tegra_com_match, tegra_com_attach, NULL, NULL); 72 73 static int 74 tegra_com_match(device_t parent, cfdata_t cf, void *aux) 75 { 76 struct fdt_attach_args * const faa = aux; 77 78 return of_compatible_match(faa->faa_phandle, compat_data); 79 } 80 81 static void 82 tegra_com_attach(device_t parent, device_t self, void *aux) 83 { 84 struct tegra_com_softc * const tsc = device_private(self); 85 struct com_softc * const sc = &tsc->tsc_sc; 86 struct fdt_attach_args * const faa = aux; 87 bus_space_tag_t bst = faa->faa_bst; 88 bus_space_handle_t bsh; 89 char intrstr[128]; 90 bus_addr_t addr; 91 bus_size_t size; 92 u_int reg_shift; 93 int error; 94 95 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 96 aprint_error(": couldn't get registers\n"); 97 return; 98 } 99 100 if (of_getprop_uint32(faa->faa_phandle, "reg-shift", ®_shift)) { 101 /* missing or bad reg-shift property, assume 2 */ 102 reg_shift = 2; 103 } 104 105 sc->sc_dev = self; 106 107 tsc->tsc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0); 108 tsc->tsc_rst = fdtbus_reset_get(faa->faa_phandle, "serial"); 109 110 if (tsc->tsc_clk == NULL) { 111 aprint_error(": couldn't get frequency\n"); 112 return; 113 } 114 115 sc->sc_frequency = clk_get_rate(tsc->tsc_clk); 116 sc->sc_type = COM_TYPE_TEGRA; 117 118 error = bus_space_map(bst, addr, size, 0, &bsh); 119 if (error) { 120 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 121 return; 122 } 123 124 com_init_regs_stride(&sc->sc_regs, bst, bsh, addr, reg_shift); 125 126 com_attach_subr(sc); 127 aprint_naive("\n"); 128 129 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 130 aprint_error_dev(self, "failed to decode interrupt\n"); 131 return; 132 } 133 134 tsc->tsc_ih = fdtbus_intr_establish_xname(faa->faa_phandle, 0, 135 IPL_SERIAL, FDT_INTR_MPSAFE, comintr, sc, device_xname(self)); 136 if (tsc->tsc_ih == NULL) { 137 aprint_error_dev(self, "failed to establish interrupt on %s\n", 138 intrstr); 139 } 140 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 141 } 142 143 /* 144 * Console support 145 */ 146 147 static int 148 tegra_com_console_match(int phandle) 149 { 150 return of_compatible_match(phandle, compat_data); 151 } 152 153 static void 154 tegra_com_console_consinit(struct fdt_attach_args *faa, u_int uart_freq) 155 { 156 const int phandle = faa->faa_phandle; 157 bus_space_tag_t bst = faa->faa_bst; 158 bus_space_handle_t dummy_bsh; 159 struct com_regs regs; 160 bus_addr_t addr; 161 tcflag_t flags; 162 u_int reg_shift; 163 int speed; 164 165 fdtbus_get_reg(phandle, 0, &addr, NULL); 166 speed = fdtbus_get_stdout_speed(); 167 if (speed < 0) 168 speed = 115200; /* default */ 169 flags = fdtbus_get_stdout_flags(); 170 171 if (of_getprop_uint32(faa->faa_phandle, "reg-shift", ®_shift)) { 172 /* missing or bad reg-shift property, assume 2 */ 173 reg_shift = 2; 174 } 175 176 memset(&dummy_bsh, 0, sizeof(dummy_bsh)); 177 com_init_regs_stride(®s, bst, dummy_bsh, addr, reg_shift); 178 179 if (comcnattach1(®s, speed, uart_freq, COM_TYPE_TEGRA, flags)) 180 panic("Cannot initialize tegra com console"); 181 } 182 183 static const struct fdt_console tegra_com_console = { 184 .match = tegra_com_console_match, 185 .consinit = tegra_com_console_consinit, 186 }; 187 188 FDT_CONSOLE(tegra_com, &tegra_com_console); 189
Indexes created Sat Sep 20 22:09:52 GMT 2025