tegra_com.c revision 1.8.10.1
1 /* $NetBSD: tegra_com.c,v 1.8.10.1 2018/07/28 04:37:28 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2013 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 34 __KERNEL_RCSID(1, "$NetBSD: tegra_com.c,v 1.8.10.1 2018/07/28 04:37:28 pgoyette Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/time.h> 42 #include <sys/termios.h> 43 44 #include <arm/nvidia/tegra_reg.h> 45 #include <arm/nvidia/tegra_var.h> 46 47 #include <dev/ic/comvar.h> 48 49 #include <dev/fdt/fdtvar.h> 50 51 static int tegra_com_match(device_t, cfdata_t, void *); 52 static void tegra_com_attach(device_t, device_t, void *); 53 54 static const char * const compatible[] = { 55 "nvidia,tegra210-uart", 56 "nvidia,tegra124-uart", 57 "nvidia,tegra20-uart", 58 NULL 59 }; 60 61 struct tegra_com_softc { 62 struct com_softc tsc_sc; 63 void *tsc_ih; 64 65 struct clk *tsc_clk; 66 struct fdtbus_reset *tsc_rst; 67 }; 68 69 CFATTACH_DECL_NEW(tegra_com, sizeof(struct tegra_com_softc), 70 tegra_com_match, tegra_com_attach, NULL, NULL); 71 72 static int 73 tegra_com_match(device_t parent, cfdata_t cf, void *aux) 74 { 75 struct fdt_attach_args * const faa = aux; 76 77 return of_match_compatible(faa->faa_phandle, compatible); 78 } 79 80 static void 81 tegra_com_attach(device_t parent, device_t self, void *aux) 82 { 83 struct tegra_com_softc * const tsc = device_private(self); 84 struct com_softc * const sc = &tsc->tsc_sc; 85 struct fdt_attach_args * const faa = aux; 86 bus_space_handle_t bsh; 87 bus_space_tag_t bst; 88 char intrstr[128]; 89 bus_addr_t addr; 90 bus_size_t size; 91 u_int reg_shift; 92 int error; 93 94 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 95 aprint_error(": couldn't get registers\n"); 96 return; 97 } 98 99 if (of_getprop_uint32(faa->faa_phandle, "reg-shift", ®_shift)) { 100 /* missing or bad reg-shift property, assume 2 */ 101 bst = faa->faa_a4x_bst; 102 } else { 103 if (reg_shift == 2) { 104 bst = faa->faa_a4x_bst; 105 } else if (reg_shift == 0) { 106 bst = faa->faa_bst; 107 } else { 108 aprint_error(": unsupported reg-shift value %d\n", 109 reg_shift); 110 return; 111 } 112 } 113 114 sc->sc_dev = self; 115 116 tsc->tsc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0); 117 tsc->tsc_rst = fdtbus_reset_get(faa->faa_phandle, "serial"); 118 119 if (tsc->tsc_clk == NULL) { 120 aprint_error(": couldn't get frequency\n"); 121 return; 122 } 123 124 sc->sc_frequency = clk_get_rate(tsc->tsc_clk); 125 sc->sc_type = COM_TYPE_TEGRA; 126 127 error = bus_space_map(bst, addr, size, 0, &bsh); 128 if (error) { 129 aprint_error(": couldn't map %#" PRIx64 ": %d", 130 (uint64_t)addr, error); 131 return; 132 } 133 134 COM_INIT_REGS(sc->sc_regs, bst, bsh, addr); 135 136 com_attach_subr(sc); 137 aprint_naive("\n"); 138 139 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 140 aprint_error_dev(self, "failed to decode interrupt\n"); 141 return; 142 } 143 144 tsc->tsc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SERIAL, 145 FDT_INTR_MPSAFE, comintr, sc); 146 if (tsc->tsc_ih == NULL) { 147 aprint_error_dev(self, "failed to establish interrupt on %s\n", 148 intrstr); 149 } 150 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 151 } 152 153 /* 154 * Console support 155 */ 156 157 static int 158 tegra_com_console_match(int phandle) 159 { 160 return of_match_compatible(phandle, compatible); 161 } 162 163 static void 164 tegra_com_console_consinit(struct fdt_attach_args *faa, u_int uart_freq) 165 { 166 const int phandle = faa->faa_phandle; 167 bus_space_tag_t bst = faa->faa_a4x_bst; 168 bus_addr_t addr; 169 tcflag_t flags; 170 int speed; 171 172 fdtbus_get_reg(phandle, 0, &addr, NULL); 173 speed = fdtbus_get_stdout_speed(); 174 if (speed < 0) 175 speed = 115200; /* default */ 176 flags = fdtbus_get_stdout_flags(); 177 178 if (comcnattach(bst, addr, speed, uart_freq, COM_TYPE_TEGRA, flags)) 179 panic("Cannot initialize tegra com console"); 180 } 181 182 static const struct fdt_console tegra_com_console = { 183 .match = tegra_com_console_match, 184 .consinit = tegra_com_console_consinit, 185 }; 186 187 FDT_CONSOLE(tegra_com, &tegra_com_console); 188
Indexes created Fri Oct 17 23:09:53 GMT 2025