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tegra_platform.c revision 1.19
      1  1.19  jmcneill /* $NetBSD: tegra_platform.c,v 1.19 2018/12/15 13:17:12 jmcneill Exp $ */
      2   1.1  jmcneill 
      3   1.1  jmcneill /*-
      4   1.1  jmcneill  * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca>
      5   1.1  jmcneill  * All rights reserved.
      6   1.1  jmcneill  *
      7   1.1  jmcneill  * Redistribution and use in source and binary forms, with or without
      8   1.1  jmcneill  * modification, are permitted provided that the following conditions
      9   1.1  jmcneill  * are met:
     10   1.1  jmcneill  * 1. Redistributions of source code must retain the above copyright
     11   1.1  jmcneill  *    notice, this list of conditions and the following disclaimer.
     12   1.1  jmcneill  * 2. Redistributions in binary form must reproduce the above copyright
     13   1.1  jmcneill  *    notice, this list of conditions and the following disclaimer in the
     14   1.1  jmcneill  *    documentation and/or other materials provided with the distribution.
     15   1.1  jmcneill  *
     16   1.1  jmcneill  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17   1.1  jmcneill  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18   1.1  jmcneill  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19   1.1  jmcneill  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20   1.1  jmcneill  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21   1.1  jmcneill  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22   1.1  jmcneill  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23   1.1  jmcneill  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24   1.1  jmcneill  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25   1.1  jmcneill  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26   1.1  jmcneill  * SUCH DAMAGE.
     27   1.1  jmcneill  */
     28   1.1  jmcneill 
     29  1.17     skrll #include "opt_arm_debug.h"
     30  1.17     skrll #include "opt_console.h"
     31  1.17     skrll #include "opt_multiprocessor.h"
     32   1.1  jmcneill #include "opt_tegra.h"
     33   1.1  jmcneill 
     34   1.1  jmcneill #include "ukbd.h"
     35   1.1  jmcneill 
     36   1.1  jmcneill #include <sys/cdefs.h>
     37  1.19  jmcneill __KERNEL_RCSID(0, "$NetBSD: tegra_platform.c,v 1.19 2018/12/15 13:17:12 jmcneill Exp $");
     38   1.1  jmcneill 
     39   1.1  jmcneill #include <sys/param.h>
     40   1.1  jmcneill #include <sys/bus.h>
     41   1.1  jmcneill #include <sys/cpu.h>
     42   1.1  jmcneill #include <sys/device.h>
     43   1.1  jmcneill #include <sys/termios.h>
     44   1.1  jmcneill 
     45   1.1  jmcneill #include <dev/fdt/fdtvar.h>
     46   1.1  jmcneill 
     47   1.1  jmcneill #include <uvm/uvm_extern.h>
     48   1.1  jmcneill 
     49   1.1  jmcneill #include <machine/bootconfig.h>
     50   1.1  jmcneill #include <arm/cpufunc.h>
     51   1.1  jmcneill 
     52   1.1  jmcneill #include <arm/nvidia/tegra_reg.h>
     53   1.1  jmcneill #include <arm/nvidia/tegra_var.h>
     54  1.11       ryo #include <arm/nvidia/tegra_platform.h>
     55   1.1  jmcneill 
     56   1.3  jmcneill #include <arm/fdt/arm_fdtvar.h>
     57   1.1  jmcneill 
     58  1.12  jmcneill #include <arm/arm/psci.h>
     59  1.15       ryo #include <arm/fdt/psci_fdtvar.h>
     60  1.12  jmcneill 
     61   1.1  jmcneill #if NUKBD > 0
     62   1.1  jmcneill #include <dev/usb/ukbdvar.h>
     63   1.1  jmcneill #endif
     64   1.1  jmcneill 
     65   1.4  jmcneill #include <dev/ic/ns16550reg.h>
     66   1.4  jmcneill #include <dev/ic/comreg.h>
     67   1.4  jmcneill 
     68   1.6  jmcneill #define	PLLP_OUT0_FREQ	408000000
     69   1.6  jmcneill 
     70  1.11       ryo void tegra_platform_early_putchar(char);
     71  1.11       ryo 
     72  1.18     skrll void
     73  1.18     skrll tegra_platform_early_putchar(char c)
     74  1.18     skrll {
     75  1.18     skrll #ifdef CONSADDR
     76  1.18     skrll #define CONSADDR_VA	(CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE)
     77  1.18     skrll 
     78  1.18     skrll 	volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
     79  1.18     skrll 	    (volatile uint32_t *)CONSADDR_VA :
     80  1.18     skrll 	    (volatile uint32_t *)CONSADDR;
     81  1.18     skrll 
     82  1.18     skrll 	while ((uartaddr[com_lsr] & LSR_TXRDY) == 0)
     83  1.18     skrll 		;
     84  1.18     skrll 
     85  1.18     skrll 	uartaddr[com_data] = c;
     86  1.18     skrll #endif
     87  1.18     skrll }
     88  1.18     skrll 
     89   1.1  jmcneill static const struct pmap_devmap *
     90   1.1  jmcneill tegra_platform_devmap(void)
     91   1.1  jmcneill {
     92   1.1  jmcneill 	static const struct pmap_devmap devmap[] = {
     93   1.1  jmcneill 		DEVMAP_ENTRY(TEGRA_HOST1X_VBASE,
     94   1.1  jmcneill 			     TEGRA_HOST1X_BASE,
     95   1.1  jmcneill 			     TEGRA_HOST1X_SIZE),
     96   1.1  jmcneill 		DEVMAP_ENTRY(TEGRA_PPSB_VBASE,
     97   1.1  jmcneill 			     TEGRA_PPSB_BASE,
     98   1.1  jmcneill 			     TEGRA_PPSB_SIZE),
     99   1.1  jmcneill 		DEVMAP_ENTRY(TEGRA_APB_VBASE,
    100   1.1  jmcneill 			     TEGRA_APB_BASE,
    101   1.1  jmcneill 			     TEGRA_APB_SIZE),
    102   1.1  jmcneill 		DEVMAP_ENTRY(TEGRA_AHB_A2_VBASE,
    103   1.1  jmcneill 			     TEGRA_AHB_A2_BASE,
    104   1.1  jmcneill 			     TEGRA_AHB_A2_SIZE),
    105   1.1  jmcneill 		DEVMAP_ENTRY_END
    106   1.9     skrll 	};
    107   1.1  jmcneill 
    108   1.1  jmcneill 	return devmap;
    109   1.1  jmcneill }
    110   1.1  jmcneill 
    111  1.17     skrll #if defined(SOC_TEGRA124)
    112   1.1  jmcneill static void
    113   1.7  jmcneill tegra124_platform_bootstrap(void)
    114   1.1  jmcneill {
    115  1.11       ryo #ifdef MULTIPROCESSOR
    116  1.17     skrll 	arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
    117  1.11       ryo #endif
    118  1.17     skrll 
    119  1.17     skrll 	tegra_bootstrap();
    120   1.7  jmcneill }
    121  1.12  jmcneill #endif
    122   1.7  jmcneill 
    123  1.17     skrll #if defined(SOC_TEGRA210)
    124   1.7  jmcneill static void
    125   1.7  jmcneill tegra210_platform_bootstrap(void)
    126   1.7  jmcneill {
    127  1.17     skrll 
    128   1.7  jmcneill 	tegra_bootstrap();
    129  1.19  jmcneill 
    130  1.19  jmcneill #if defined(MULTIPROCESSOR) && defined(__aarch64__)
    131  1.19  jmcneill 	arm_fdt_cpu_bootstrap();
    132  1.19  jmcneill #endif
    133  1.17     skrll }
    134  1.17     skrll 
    135  1.17     skrll static void
    136  1.17     skrll tegra210_platform_mpstart(void)
    137  1.17     skrll {
    138   1.7  jmcneill 
    139  1.13  jmcneill #if defined(MULTIPROCESSOR) && defined(__aarch64__)
    140  1.19  jmcneill 	arm_fdt_cpu_mpstart();
    141  1.11       ryo #endif
    142   1.1  jmcneill }
    143  1.12  jmcneill #endif
    144   1.1  jmcneill 
    145   1.1  jmcneill static void
    146   1.2  jmcneill tegra_platform_init_attach_args(struct fdt_attach_args *faa)
    147   1.2  jmcneill {
    148  1.11       ryo 	extern struct bus_space arm_generic_bs_tag;
    149  1.11       ryo 	extern struct bus_space arm_generic_a4x_bs_tag;
    150  1.10       ryo 	extern struct arm32_bus_dma_tag arm_generic_dma_tag;
    151   1.2  jmcneill 
    152  1.11       ryo 	faa->faa_bst = &arm_generic_bs_tag;
    153  1.11       ryo 	faa->faa_a4x_bst = &arm_generic_a4x_bs_tag;
    154  1.10       ryo 	faa->faa_dmat = &arm_generic_dma_tag;
    155   1.2  jmcneill }
    156   1.2  jmcneill 
    157   1.1  jmcneill static void
    158   1.1  jmcneill tegra_platform_device_register(device_t self, void *aux)
    159   1.1  jmcneill {
    160   1.1  jmcneill 	prop_dictionary_t dict = device_properties(self);
    161   1.1  jmcneill 
    162   1.1  jmcneill 	if (device_is_a(self, "tegrafb") &&
    163   1.1  jmcneill 	    match_bootconf_option(boot_args, "console", "fb")) {
    164   1.1  jmcneill 		prop_dictionary_set_bool(dict, "is_console", true);
    165   1.1  jmcneill #if NUKBD > 0
    166   1.1  jmcneill 		ukbd_cnattach();
    167   1.1  jmcneill #endif
    168   1.1  jmcneill 	}
    169   1.1  jmcneill 
    170   1.1  jmcneill 	if (device_is_a(self, "tegradrm")) {
    171   1.1  jmcneill 		const char *video = get_bootconf_string(boot_args, "video");
    172   1.1  jmcneill 		if (video)
    173   1.1  jmcneill 			prop_dictionary_set_cstring(dict, "HDMI-A-1", video);
    174   1.1  jmcneill 		if (match_bootconf_option(boot_args, "hdmi.forcemode", "dvi"))
    175   1.1  jmcneill 			prop_dictionary_set_bool(dict, "force-dvi", true);
    176   1.1  jmcneill 	}
    177   1.1  jmcneill 
    178   1.1  jmcneill 	if (device_is_a(self, "tegracec"))
    179   1.1  jmcneill 		prop_dictionary_set_cstring(dict, "hdmi-device", "tegradrm0");
    180   1.1  jmcneill 
    181   1.1  jmcneill 	if (device_is_a(self, "nouveau")) {
    182   1.1  jmcneill 		const char *config = get_bootconf_string(boot_args,
    183   1.1  jmcneill 		    "nouveau.config");
    184   1.1  jmcneill 		if (config)
    185   1.1  jmcneill 			prop_dictionary_set_cstring(dict, "config", config);
    186   1.1  jmcneill 		const char *debug = get_bootconf_string(boot_args,
    187   1.1  jmcneill 		    "nouveau.debug");
    188   1.1  jmcneill 		if (debug)
    189   1.1  jmcneill 			prop_dictionary_set_cstring(dict, "debug", debug);
    190   1.1  jmcneill 	}
    191   1.1  jmcneill 
    192   1.1  jmcneill 	if (device_is_a(self, "tegrapcie")) {
    193   1.1  jmcneill 		const char * const jetsontk1_compat[] = {
    194   1.1  jmcneill 		    "nvidia,jetson-tk1", NULL
    195   1.1  jmcneill 		};
    196   1.1  jmcneill 		const int phandle = OF_peer(0);
    197   1.1  jmcneill 		if (of_match_compatible(phandle, jetsontk1_compat)) {
    198   1.1  jmcneill 			/* rfkill GPIO at GPIO X7 */
    199   1.1  jmcneill 			struct tegra_gpio_pin *pin =
    200   1.1  jmcneill 			    tegra_gpio_acquire("X7", GPIO_PIN_OUTPUT);
    201   1.1  jmcneill 			if (pin)
    202   1.1  jmcneill 				tegra_gpio_write(pin, 1);
    203   1.1  jmcneill 		}
    204   1.1  jmcneill 	}
    205   1.1  jmcneill }
    206   1.1  jmcneill 
    207   1.1  jmcneill static void
    208   1.1  jmcneill tegra_platform_reset(void)
    209   1.1  jmcneill {
    210   1.1  jmcneill 	tegra_pmc_reset();
    211   1.1  jmcneill }
    212   1.1  jmcneill 
    213   1.5  jmcneill static void
    214   1.5  jmcneill tegra_platform_delay(u_int us)
    215   1.5  jmcneill {
    216   1.5  jmcneill 	tegra_timer_delay(us);
    217   1.5  jmcneill }
    218   1.5  jmcneill 
    219   1.6  jmcneill static u_int
    220   1.6  jmcneill tegra_platform_uart_freq(void)
    221   1.6  jmcneill {
    222   1.6  jmcneill 	return PLLP_OUT0_FREQ;
    223   1.6  jmcneill }
    224   1.6  jmcneill 
    225  1.17     skrll #if defined(SOC_TEGRA124)
    226   1.7  jmcneill static const struct arm_platform tegra124_platform = {
    227  1.14     skrll 	.ap_devmap = tegra_platform_devmap,
    228  1.14     skrll 	.ap_bootstrap = tegra124_platform_bootstrap,
    229  1.14     skrll 	.ap_init_attach_args = tegra_platform_init_attach_args,
    230  1.14     skrll 	.ap_device_register = tegra_platform_device_register,
    231  1.14     skrll 	.ap_reset = tegra_platform_reset,
    232  1.14     skrll 	.ap_delay = tegra_platform_delay,
    233  1.14     skrll 	.ap_uart_freq = tegra_platform_uart_freq,
    234  1.17     skrll 	.ap_mpstart = tegra124_mpstart,
    235   1.7  jmcneill };
    236   1.7  jmcneill 
    237   1.7  jmcneill ARM_PLATFORM(tegra124, "nvidia,tegra124", &tegra124_platform);
    238  1.12  jmcneill #endif
    239   1.7  jmcneill 
    240  1.17     skrll #if defined(SOC_TEGRA210)
    241   1.7  jmcneill static const struct arm_platform tegra210_platform = {
    242  1.14     skrll 	.ap_devmap = tegra_platform_devmap,
    243  1.14     skrll 	.ap_bootstrap = tegra210_platform_bootstrap,
    244  1.14     skrll 	.ap_init_attach_args = tegra_platform_init_attach_args,
    245  1.14     skrll 	.ap_device_register = tegra_platform_device_register,
    246  1.14     skrll 	.ap_reset = tegra_platform_reset,
    247  1.14     skrll 	.ap_delay = tegra_platform_delay,
    248  1.14     skrll 	.ap_uart_freq = tegra_platform_uart_freq,
    249  1.17     skrll 	.ap_mpstart = tegra210_platform_mpstart,
    250   1.1  jmcneill };
    251   1.1  jmcneill 
    252   1.7  jmcneill ARM_PLATFORM(tegra210, "nvidia,tegra210", &tegra210_platform);
    253  1.12  jmcneill #endif
    254