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tegra_platform.c revision 1.1 
      1 /* $NetBSD: tegra_platform.c,v 1.1 2017/05/28 23:39:30 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #include "opt_tegra.h"
     30 #include "opt_multiprocessor.h"
     31 
     32 #include "com.h"
     33 #include "ukbd.h"
     34 
     35 #include <sys/cdefs.h>
     36 __KERNEL_RCSID(0, "$NetBSD: tegra_platform.c,v 1.1 2017/05/28 23:39:30 jmcneill Exp $");
     37 
     38 #include <sys/param.h>
     39 #include <sys/bus.h>
     40 #include <sys/cpu.h>
     41 #include <sys/device.h>
     42 #include <sys/termios.h>
     43 
     44 #include <dev/fdt/fdtvar.h>
     45 
     46 #include <uvm/uvm_extern.h>
     47 
     48 #include <machine/bootconfig.h>
     49 #include <arm/cpufunc.h>
     50 
     51 #include <arm/nvidia/tegra_reg.h>
     52 #include <arm/nvidia/tegra_var.h>
     53 
     54 #include <arm/fdt/armv7_fdtvar.h>
     55 
     56 #if NUKBD > 0
     57 #include <dev/usb/ukbdvar.h>
     58 #endif
     59 
     60 #if NCOM > 0
     61 #include <dev/ic/ns16550reg.h>
     62 #include <dev/ic/comreg.h>
     63 #include <dev/ic/comvar.h>
     64 #ifndef CONMODE
     65 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
     66 #endif
     67 #endif
     68 
     69 #define	DEVMAP_ALIGN(a)	((a) & ~L1_S_OFFSET)
     70 #define	DEVMAP_SIZE(s)	roundup2((s), L1_S_SIZE)
     71 #define	DEVMAP_ENTRY(va, pa, sz)			\
     72 	{						\
     73 		.pd_va = DEVMAP_ALIGN(va),		\
     74 		.pd_pa = DEVMAP_ALIGN(pa),		\
     75 		.pd_size = DEVMAP_SIZE(sz),		\
     76 		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,	\
     77 		.pd_cache = PTE_NOCACHE			\
     78 	}
     79 #define	DEVMAP_ENTRY_END	{ 0 }
     80 
     81 static const struct pmap_devmap *
     82 tegra_platform_devmap(void)
     83 {
     84 	static const struct pmap_devmap devmap[] = {
     85 		DEVMAP_ENTRY(TEGRA_HOST1X_VBASE,
     86 			     TEGRA_HOST1X_BASE,
     87 			     TEGRA_HOST1X_SIZE),
     88 		DEVMAP_ENTRY(TEGRA_PPSB_VBASE,
     89 			     TEGRA_PPSB_BASE,
     90 			     TEGRA_PPSB_SIZE),
     91 		DEVMAP_ENTRY(TEGRA_APB_VBASE,
     92 			     TEGRA_APB_BASE,
     93 			     TEGRA_APB_SIZE),
     94 		DEVMAP_ENTRY(TEGRA_AHB_A2_VBASE,
     95 			     TEGRA_AHB_A2_BASE,
     96 			     TEGRA_AHB_A2_SIZE),
     97 		DEVMAP_ENTRY_END
     98 	};
     99 
    100 	return devmap;
    101 }
    102 
    103 static void
    104 tegra_platform_bootstrap(void)
    105 {
    106 	tegra_bootstrap();
    107 }
    108 
    109 static void
    110 tegra_platform_early_putchar(char c)
    111 {
    112 #ifdef CONSADDR
    113 #define CONSADDR_VA	(CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE)
    114 	volatile uint32_t *uartaddr = (volatile uint32_t *)CONSADDR_VA;
    115 
    116 	while ((uartaddr[com_lsr] & LSR_TXRDY) == 0)
    117 		;
    118 
    119 	uartaddr[com_data] = c;
    120 #endif
    121 }
    122 
    123 static void
    124 tegra_platform_device_register(device_t self, void *aux)
    125 {
    126 	prop_dictionary_t dict = device_properties(self);
    127 
    128 	if (device_is_a(self, "tegrafb") &&
    129 	    match_bootconf_option(boot_args, "console", "fb")) {
    130 		prop_dictionary_set_bool(dict, "is_console", true);
    131 #if NUKBD > 0
    132 		ukbd_cnattach();
    133 #endif
    134 	}
    135 
    136 	if (device_is_a(self, "tegradrm")) {
    137 		const char *video = get_bootconf_string(boot_args, "video");
    138 		if (video)
    139 			prop_dictionary_set_cstring(dict, "HDMI-A-1", video);
    140 		if (match_bootconf_option(boot_args, "hdmi.forcemode", "dvi"))
    141 			prop_dictionary_set_bool(dict, "force-dvi", true);
    142 	}
    143 
    144 	if (device_is_a(self, "tegracec"))
    145 		prop_dictionary_set_cstring(dict, "hdmi-device", "tegradrm0");
    146 
    147 	if (device_is_a(self, "nouveau")) {
    148 		const char *config = get_bootconf_string(boot_args,
    149 		    "nouveau.config");
    150 		if (config)
    151 			prop_dictionary_set_cstring(dict, "config", config);
    152 		const char *debug = get_bootconf_string(boot_args,
    153 		    "nouveau.debug");
    154 		if (debug)
    155 			prop_dictionary_set_cstring(dict, "debug", debug);
    156 	}
    157 
    158 	if (device_is_a(self, "tegrapcie")) {
    159 		const char * const jetsontk1_compat[] = {
    160 		    "nvidia,jetson-tk1", NULL
    161 		};
    162 		const int phandle = OF_peer(0);
    163 		if (of_match_compatible(phandle, jetsontk1_compat)) {
    164 			/* rfkill GPIO at GPIO X7 */
    165 			struct tegra_gpio_pin *pin =
    166 			    tegra_gpio_acquire("X7", GPIO_PIN_OUTPUT);
    167 			if (pin)
    168 				tegra_gpio_write(pin, 1);
    169 		}
    170 	}
    171 }
    172 
    173 static void
    174 tegra_platform_reset(void)
    175 {
    176 	tegra_pmc_reset();
    177 }
    178 
    179 static void
    180 tegra_platform_consinit(void)
    181 {
    182 	static bool consinit_called = false;
    183 
    184 	if (consinit_called)
    185 		return;
    186 	consinit_called = true;
    187 
    188 #if NCOM > 0
    189 	bus_addr_t addr;
    190 	int speed;
    191 
    192 #ifdef CONSADDR
    193 	addr = CONSADDR;
    194 #else
    195 	fdtbus_get_reg(fdtbus_get_stdout_phandle(), 0, &addr, NULL);
    196 #endif
    197 
    198 #ifdef CONSPEED
    199 	speed = CONSPEED;
    200 #else
    201 	speed = fdtbus_get_stdout_speed();
    202 	if (speed < 0)
    203 		speed = 115200;	/* default */
    204 #endif
    205 
    206 	const bus_space_tag_t bst = &armv7_generic_a4x_bs_tag;
    207 	const u_int freq = 408000000;	/* 408MHz PLLP_OUT0 */
    208 	if (comcnattach(bst, addr, speed, freq, COM_TYPE_TEGRA, CONMODE))
    209 		panic("Serial console cannot be initialized.");
    210 #endif
    211 }
    212 
    213 static const struct armv7_platform tegra_platform = {
    214 	.devmap = tegra_platform_devmap,
    215 	.bootstrap = tegra_platform_bootstrap,
    216 	.early_putchar = tegra_platform_early_putchar,
    217 	.device_register = tegra_platform_device_register,
    218 	.reset = tegra_platform_reset,
    219 	.consinit = tegra_platform_consinit,
    220 };
    221 
    222 ARMV7_PLATFORM(tegra124, "nvidia,tegra124", &tegra_platform);
    223 ARMV7_PLATFORM(tegra210, "nvidia,tegra210", &tegra_platform);
    224