tegra_platform.c revision 1.21
1 /* $NetBSD: tegra_platform.c,v 1.21 2020/06/20 15:48:19 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_arm_debug.h" 30 #include "opt_console.h" 31 #include "opt_multiprocessor.h" 32 #include "opt_tegra.h" 33 34 #include "ukbd.h" 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: tegra_platform.c,v 1.21 2020/06/20 15:48:19 skrll Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 #include <sys/termios.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bootconfig.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/nvidia/tegra_reg.h> 53 #include <arm/nvidia/tegra_var.h> 54 #include <arm/nvidia/tegra_platform.h> 55 56 #include <arm/fdt/arm_fdtvar.h> 57 58 #include <arm/arm/psci.h> 59 #include <arm/fdt/psci_fdtvar.h> 60 61 #if NUKBD > 0 62 #include <dev/usb/ukbdvar.h> 63 #endif 64 65 #include <dev/ic/ns16550reg.h> 66 #include <dev/ic/comreg.h> 67 68 #define PLLP_OUT0_FREQ 408000000 69 70 void tegra_platform_early_putchar(char); 71 72 void 73 tegra_platform_early_putchar(char c) 74 { 75 #ifdef CONSADDR 76 #define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE) 77 78 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 79 (volatile uint32_t *)CONSADDR_VA : 80 (volatile uint32_t *)CONSADDR; 81 82 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 83 ; 84 85 uartaddr[com_data] = c; 86 #endif 87 } 88 89 static const struct pmap_devmap * 90 tegra_platform_devmap(void) 91 { 92 static const struct pmap_devmap devmap[] = { 93 DEVMAP_ENTRY(TEGRA_HOST1X_VBASE, 94 TEGRA_HOST1X_BASE, 95 TEGRA_HOST1X_SIZE), 96 DEVMAP_ENTRY(TEGRA_PPSB_VBASE, 97 TEGRA_PPSB_BASE, 98 TEGRA_PPSB_SIZE), 99 DEVMAP_ENTRY(TEGRA_APB_VBASE, 100 TEGRA_APB_BASE, 101 TEGRA_APB_SIZE), 102 DEVMAP_ENTRY(TEGRA_AHB_A2_VBASE, 103 TEGRA_AHB_A2_BASE, 104 TEGRA_AHB_A2_SIZE), 105 DEVMAP_ENTRY_END 106 }; 107 108 return devmap; 109 } 110 111 #if defined(SOC_TEGRA124) 112 static void 113 tegra124_platform_bootstrap(void) 114 { 115 #ifdef MULTIPROCESSOR 116 arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU); 117 #endif 118 119 tegra_bootstrap(); 120 } 121 #endif 122 123 #if defined(SOC_TEGRA210) 124 static void 125 tegra210_platform_bootstrap(void) 126 { 127 128 tegra_bootstrap(); 129 130 #if defined(MULTIPROCESSOR) && defined(__aarch64__) 131 arm_fdt_cpu_bootstrap(); 132 #endif 133 } 134 #endif 135 136 static void 137 tegra_platform_init_attach_args(struct fdt_attach_args *faa) 138 { 139 extern struct bus_space arm_generic_bs_tag; 140 extern struct bus_space arm_generic_a4x_bs_tag; 141 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 142 143 faa->faa_bst = &arm_generic_bs_tag; 144 faa->faa_a4x_bst = &arm_generic_a4x_bs_tag; 145 faa->faa_dmat = &arm_generic_dma_tag; 146 } 147 148 static void 149 tegra_platform_device_register(device_t self, void *aux) 150 { 151 prop_dictionary_t dict = device_properties(self); 152 153 if (device_is_a(self, "tegrafb") && 154 match_bootconf_option(boot_args, "console", "fb")) { 155 prop_dictionary_set_bool(dict, "is_console", true); 156 #if NUKBD > 0 157 ukbd_cnattach(); 158 #endif 159 } 160 161 if (device_is_a(self, "tegradrm")) { 162 const char *video = get_bootconf_string(boot_args, "video"); 163 if (video) 164 prop_dictionary_set_string(dict, "HDMI-A-1", video); 165 if (match_bootconf_option(boot_args, "hdmi.forcemode", "dvi")) 166 prop_dictionary_set_bool(dict, "force-dvi", true); 167 } 168 169 if (device_is_a(self, "tegracec")) 170 prop_dictionary_set_string(dict, "hdmi-device", "tegradrm0"); 171 172 if (device_is_a(self, "nouveau")) { 173 const char *config = get_bootconf_string(boot_args, 174 "nouveau.config"); 175 if (config) 176 prop_dictionary_set_string(dict, "config", config); 177 const char *debug = get_bootconf_string(boot_args, 178 "nouveau.debug"); 179 if (debug) 180 prop_dictionary_set_string(dict, "debug", debug); 181 } 182 183 if (device_is_a(self, "tegrapcie")) { 184 const char * const jetsontk1_compat[] = { 185 "nvidia,jetson-tk1", NULL 186 }; 187 const int phandle = OF_peer(0); 188 if (of_match_compatible(phandle, jetsontk1_compat)) { 189 /* rfkill GPIO at GPIO X7 */ 190 struct tegra_gpio_pin *pin = 191 tegra_gpio_acquire("X7", GPIO_PIN_OUTPUT); 192 if (pin) 193 tegra_gpio_write(pin, 1); 194 } 195 } 196 } 197 198 static void 199 tegra_platform_reset(void) 200 { 201 tegra_pmc_reset(); 202 } 203 204 static void 205 tegra_platform_delay(u_int us) 206 { 207 tegra_timer_delay(us); 208 } 209 210 static u_int 211 tegra_platform_uart_freq(void) 212 { 213 return PLLP_OUT0_FREQ; 214 } 215 216 #if defined(SOC_TEGRA124) 217 static const struct arm_platform tegra124_platform = { 218 .ap_devmap = tegra_platform_devmap, 219 .ap_bootstrap = tegra124_platform_bootstrap, 220 .ap_init_attach_args = tegra_platform_init_attach_args, 221 .ap_device_register = tegra_platform_device_register, 222 .ap_reset = tegra_platform_reset, 223 .ap_delay = tegra_platform_delay, 224 .ap_uart_freq = tegra_platform_uart_freq, 225 .ap_mpstart = tegra124_mpstart, 226 }; 227 228 ARM_PLATFORM(tegra124, "nvidia,tegra124", &tegra124_platform); 229 #endif 230 231 #if defined(SOC_TEGRA210) 232 static const struct arm_platform tegra210_platform = { 233 .ap_devmap = tegra_platform_devmap, 234 .ap_bootstrap = tegra210_platform_bootstrap, 235 .ap_init_attach_args = tegra_platform_init_attach_args, 236 .ap_device_register = tegra_platform_device_register, 237 .ap_reset = tegra_platform_reset, 238 .ap_delay = tegra_platform_delay, 239 .ap_uart_freq = tegra_platform_uart_freq, 240 .ap_mpstart = arm_fdt_cpu_mpstart, 241 }; 242 243 ARM_PLATFORM(tegra210, "nvidia,tegra210", &tegra210_platform); 244 #endif 245
Indexes created Wed Sep 24 05:09:52 GMT 2025