tegra_platform.c revision 1.25
1 /* $NetBSD: tegra_platform.c,v 1.25 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include "opt_arm_debug.h" 30 #include "opt_console.h" 31 #include "opt_multiprocessor.h" 32 #include "opt_tegra.h" 33 34 #include "ukbd.h" 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: tegra_platform.c,v 1.25 2021/01/27 03:10:19 thorpej Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/cpu.h> 42 #include <sys/device.h> 43 #include <sys/termios.h> 44 45 #include <dev/fdt/fdtvar.h> 46 47 #include <uvm/uvm_extern.h> 48 49 #include <machine/bootconfig.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/nvidia/tegra_reg.h> 53 #include <arm/nvidia/tegra_var.h> 54 #include <arm/nvidia/tegra_platform.h> 55 56 #include <arm/fdt/arm_fdtvar.h> 57 58 #include <arm/arm/psci.h> 59 #include <arm/fdt/psci_fdtvar.h> 60 61 #if NUKBD > 0 62 #include <dev/usb/ukbdvar.h> 63 #endif 64 65 #include <dev/ic/ns16550reg.h> 66 #include <dev/ic/comreg.h> 67 68 #define PLLP_OUT0_FREQ 408000000 69 70 void tegra_platform_early_putchar(char); 71 72 void __noasan 73 tegra_platform_early_putchar(char c) 74 { 75 #ifdef CONSADDR 76 #define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE) 77 78 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? 79 (volatile uint32_t *)CONSADDR_VA : 80 (volatile uint32_t *)CONSADDR; 81 82 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 83 ; 84 85 uartaddr[com_data] = c; 86 #endif 87 } 88 89 #if defined(SOC_TEGRA124) || defined(SOC_TEGRA210) 90 static const struct pmap_devmap * 91 tegra_platform_devmap(void) 92 { 93 static const struct pmap_devmap devmap[] = { 94 DEVMAP_ENTRY(TEGRA_HOST1X_VBASE, 95 TEGRA_HOST1X_BASE, 96 TEGRA_HOST1X_SIZE), 97 DEVMAP_ENTRY(TEGRA_PPSB_VBASE, 98 TEGRA_PPSB_BASE, 99 TEGRA_PPSB_SIZE), 100 DEVMAP_ENTRY(TEGRA_APB_VBASE, 101 TEGRA_APB_BASE, 102 TEGRA_APB_SIZE), 103 DEVMAP_ENTRY(TEGRA_AHB_A2_VBASE, 104 TEGRA_AHB_A2_BASE, 105 TEGRA_AHB_A2_SIZE), 106 DEVMAP_ENTRY_END 107 }; 108 109 return devmap; 110 } 111 #endif /* SOC_TEGRA124 || SOC_TEGRA210 */ 112 113 #if defined(SOC_TEGRA124) 114 static void 115 tegra124_platform_bootstrap(void) 116 { 117 #ifdef MULTIPROCESSOR 118 arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU); 119 #endif 120 121 tegra_bootstrap(); 122 } 123 #endif 124 125 #if defined(SOC_TEGRA210) 126 static void 127 tegra210_platform_bootstrap(void) 128 { 129 130 tegra_bootstrap(); 131 132 #if defined(MULTIPROCESSOR) && defined(__aarch64__) 133 arm_fdt_cpu_bootstrap(); 134 #endif 135 } 136 #endif 137 138 #if defined(SOC_TEGRA124) || defined(SOC_TEGRA210) 139 static void 140 tegra_platform_init_attach_args(struct fdt_attach_args *faa) 141 { 142 extern struct bus_space arm_generic_bs_tag; 143 extern struct arm32_bus_dma_tag arm_generic_dma_tag; 144 145 faa->faa_bst = &arm_generic_bs_tag; 146 faa->faa_dmat = &arm_generic_dma_tag; 147 } 148 149 static void 150 tegra_platform_device_register(device_t self, void *aux) 151 { 152 prop_dictionary_t dict = device_properties(self); 153 154 if (device_is_a(self, "tegrafb") && 155 match_bootconf_option(boot_args, "console", "fb")) { 156 prop_dictionary_set_bool(dict, "is_console", true); 157 #if NUKBD > 0 158 ukbd_cnattach(); 159 #endif 160 } 161 162 if (device_is_a(self, "tegradrm")) { 163 const char *video = get_bootconf_string(boot_args, "video"); 164 if (video) 165 prop_dictionary_set_string(dict, "HDMI-A-1", video); 166 if (match_bootconf_option(boot_args, "hdmi.forcemode", "dvi")) 167 prop_dictionary_set_bool(dict, "force-dvi", true); 168 } 169 170 if (device_is_a(self, "tegracec")) 171 prop_dictionary_set_string(dict, "hdmi-device", "tegradrm0"); 172 173 if (device_is_a(self, "nouveau")) { 174 const char *config = get_bootconf_string(boot_args, 175 "nouveau.config"); 176 if (config) 177 prop_dictionary_set_string(dict, "config", config); 178 const char *debug = get_bootconf_string(boot_args, 179 "nouveau.debug"); 180 if (debug) 181 prop_dictionary_set_string(dict, "debug", debug); 182 } 183 184 if (device_is_a(self, "tegrapcie")) { 185 static const struct device_compatible_entry jetsontk1[] = { 186 { .compat = "nvidia,jetson-tk1" }, 187 DEVICE_COMPAT_EOL 188 }; 189 const int phandle = OF_peer(0); 190 if (of_compatible_match(phandle, jetsontk1)) { 191 /* rfkill GPIO at GPIO X7 */ 192 struct tegra_gpio_pin *pin = 193 tegra_gpio_acquire("X7", GPIO_PIN_OUTPUT); 194 if (pin) 195 tegra_gpio_write(pin, 1); 196 } 197 } 198 } 199 200 static void 201 tegra_platform_reset(void) 202 { 203 tegra_pmc_reset(); 204 } 205 206 static void 207 tegra_platform_delay(u_int us) 208 { 209 tegra_timer_delay(us); 210 } 211 212 static u_int 213 tegra_platform_uart_freq(void) 214 { 215 return PLLP_OUT0_FREQ; 216 } 217 #endif /* SOC_TEGRA124 || SOC_TEGRA210 */ 218 219 #if defined(SOC_TEGRA124) 220 static const struct arm_platform tegra124_platform = { 221 .ap_devmap = tegra_platform_devmap, 222 .ap_bootstrap = tegra124_platform_bootstrap, 223 .ap_init_attach_args = tegra_platform_init_attach_args, 224 .ap_device_register = tegra_platform_device_register, 225 .ap_reset = tegra_platform_reset, 226 .ap_delay = tegra_platform_delay, 227 .ap_uart_freq = tegra_platform_uart_freq, 228 .ap_mpstart = tegra124_mpstart, 229 }; 230 231 ARM_PLATFORM(tegra124, "nvidia,tegra124", &tegra124_platform); 232 #endif 233 234 #if defined(SOC_TEGRA210) 235 static const struct arm_platform tegra210_platform = { 236 .ap_devmap = tegra_platform_devmap, 237 .ap_bootstrap = tegra210_platform_bootstrap, 238 .ap_init_attach_args = tegra_platform_init_attach_args, 239 .ap_device_register = tegra_platform_device_register, 240 .ap_reset = tegra_platform_reset, 241 .ap_delay = tegra_platform_delay, 242 .ap_uart_freq = tegra_platform_uart_freq, 243 .ap_mpstart = arm_fdt_cpu_mpstart, 244 }; 245 246 ARM_PLATFORM(tegra210, "nvidia,tegra210", &tegra210_platform); 247 #endif 248
Indexes created Thu Sep 25 16:09:42 GMT 2025