tegra_platform.c revision 1.29 1 /* $NetBSD: tegra_platform.c,v 1.29 2025/09/06 21:02:40 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared D. McNeill <jmcneill (at) invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_arm_debug.h"
30 #include "opt_console.h"
31 #include "opt_multiprocessor.h"
32 #include "opt_tegra.h"
33
34 #include "ukbd.h"
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: tegra_platform.c,v 1.29 2025/09/06 21:02:40 thorpej Exp $");
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/cpu.h>
42 #include <sys/device.h>
43 #include <sys/termios.h>
44
45 #include <dev/fdt/fdtvar.h>
46 #include <dev/fdt/fdt_platform.h>
47
48 #include <uvm/uvm_extern.h>
49
50 #include <machine/bootconfig.h>
51 #include <arm/cpufunc.h>
52
53 #include <arm/nvidia/tegra_reg.h>
54 #include <arm/nvidia/tegra_var.h>
55 #include <arm/nvidia/tegra_platform.h>
56
57 #include <arm/fdt/arm_fdtvar.h>
58
59 #include <arm/arm/psci.h>
60 #include <arm/fdt/psci_fdtvar.h>
61
62 #if NUKBD > 0
63 #include <dev/usb/ukbdvar.h>
64 #endif
65
66 #include <dev/ic/ns16550reg.h>
67 #include <dev/ic/comreg.h>
68
69 #define PLLP_OUT0_FREQ 408000000
70
71 void tegra_platform_early_putchar(char);
72
73 void __noasan
74 tegra_platform_early_putchar(char c)
75 {
76 #ifdef CONSADDR
77 #define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE)
78
79 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ?
80 (volatile uint32_t *)CONSADDR_VA :
81 (volatile uint32_t *)CONSADDR;
82
83 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0)
84 ;
85
86 uartaddr[com_data] = c;
87 #endif
88 }
89
90 #if defined(SOC_TEGRA124) || defined(SOC_TEGRA210)
91 static const struct pmap_devmap *
92 tegra_platform_devmap(void)
93 {
94 static const struct pmap_devmap devmap[] = {
95 DEVMAP_ENTRY(TEGRA_HOST1X_VBASE,
96 TEGRA_HOST1X_BASE,
97 TEGRA_HOST1X_SIZE),
98 DEVMAP_ENTRY(TEGRA_PPSB_VBASE,
99 TEGRA_PPSB_BASE,
100 TEGRA_PPSB_SIZE),
101 DEVMAP_ENTRY(TEGRA_APB_VBASE,
102 TEGRA_APB_BASE,
103 TEGRA_APB_SIZE),
104 DEVMAP_ENTRY(TEGRA_AHB_A2_VBASE,
105 TEGRA_AHB_A2_BASE,
106 TEGRA_AHB_A2_SIZE),
107 DEVMAP_ENTRY_END
108 };
109
110 return devmap;
111 }
112 #endif /* SOC_TEGRA124 || SOC_TEGRA210 */
113
114 #if defined(SOC_TEGRA124)
115 static void
116 tegra124_platform_bootstrap(void)
117 {
118 #ifdef MULTIPROCESSOR
119 arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
120 #endif
121
122 tegra_bootstrap();
123 }
124 #endif
125
126 #if defined(SOC_TEGRA210)
127 static void
128 tegra210_platform_bootstrap(void)
129 {
130
131 tegra_bootstrap();
132
133 #if defined(MULTIPROCESSOR) && defined(__aarch64__)
134 arm_fdt_cpu_bootstrap();
135 #endif
136 }
137 #endif
138
139 #if defined(SOC_TEGRA124) || defined(SOC_TEGRA210)
140 static void
141 tegra_platform_init_attach_args(struct fdt_attach_args *faa)
142 {
143 extern struct bus_space arm_generic_bs_tag;
144 extern struct arm32_bus_dma_tag arm_generic_dma_tag;
145
146 faa->faa_bst = &arm_generic_bs_tag;
147 faa->faa_dmat = &arm_generic_dma_tag;
148 }
149
150 static void
151 tegra_platform_device_register(device_t self, void *aux)
152 {
153 prop_dictionary_t dict = device_properties(self);
154
155 if (device_is_a(self, "tegrafb") &&
156 match_bootconf_option(boot_args, "console", "fb")) {
157 prop_dictionary_set_bool(dict, "is_console", true);
158 #if NUKBD > 0
159 ukbd_cnattach();
160 #endif
161 }
162
163 if (device_is_a(self, "tegradrm")) {
164 const char *video = get_bootconf_string(boot_args, "video");
165 if (video)
166 prop_dictionary_set_string(dict, "HDMI-A-1", video);
167 if (match_bootconf_option(boot_args, "hdmi.forcemode", "dvi"))
168 prop_dictionary_set_bool(dict, "force-dvi", true);
169 }
170
171 if (device_is_a(self, "tegracec"))
172 prop_dictionary_set_string(dict, "hdmi-device", "tegradrm0");
173
174 if (device_is_a(self, "nouveau")) {
175 const char *config = get_bootconf_string(boot_args,
176 "nouveau.config");
177 if (config)
178 prop_dictionary_set_string(dict, "config", config);
179 const char *debug = get_bootconf_string(boot_args,
180 "nouveau.debug");
181 if (debug)
182 prop_dictionary_set_string(dict, "debug", debug);
183 }
184
185 if (device_is_a(self, "tegrapcie")) {
186 static const struct device_compatible_entry jetsontk1[] = {
187 { .compat = "nvidia,jetson-tk1" },
188 DEVICE_COMPAT_EOL
189 };
190 const int phandle = OF_peer(0);
191 if (of_compatible_match(phandle, jetsontk1)) {
192 /* rfkill GPIO at GPIO X7 */
193 struct tegra_gpio_pin *pin =
194 tegra_gpio_acquire("X7", GPIO_PIN_OUTPUT);
195 if (pin)
196 tegra_gpio_write(pin, 1);
197 }
198 }
199 }
200
201 static void
202 tegra_platform_reset(void)
203 {
204 tegra_pmc_reset();
205 }
206
207 static void
208 tegra_platform_delay(u_int us)
209 {
210 tegra_timer_delay(us);
211 }
212
213 static u_int
214 tegra_platform_uart_freq(void)
215 {
216 return PLLP_OUT0_FREQ;
217 }
218 #endif /* SOC_TEGRA124 || SOC_TEGRA210 */
219
220 #if defined(SOC_TEGRA124)
221 static const struct fdt_platform tegra124_platform = {
222 .fp_devmap = tegra_platform_devmap,
223 .fp_bootstrap = tegra124_platform_bootstrap,
224 .fp_init_attach_args = tegra_platform_init_attach_args,
225 .fp_device_register = tegra_platform_device_register,
226 .fp_reset = tegra_platform_reset,
227 .fp_delay = tegra_platform_delay,
228 .fp_uart_freq = tegra_platform_uart_freq,
229 .fp_mpstart = tegra124_mpstart,
230 };
231
232 FDT_PLATFORM(tegra124, "nvidia,tegra124", &tegra124_platform);
233 #endif
234
235 #if defined(SOC_TEGRA210)
236 static const struct fdt_platform tegra210_platform = {
237 .fp_devmap = tegra_platform_devmap,
238 .fp_bootstrap = tegra210_platform_bootstrap,
239 .fp_init_attach_args = tegra_platform_init_attach_args,
240 .fp_device_register = tegra_platform_device_register,
241 .fp_reset = tegra_platform_reset,
242 .fp_delay = tegra_platform_delay,
243 .fp_uart_freq = tegra_platform_uart_freq,
244 .fp_mpstart = arm_fdt_cpu_mpstart,
245 };
246
247 FDT_PLATFORM(tegra210, "nvidia,tegra210", &tegra210_platform);
248 #endif
249