tegra_sdhc.c revision 1.15.2.1
1 /* $NetBSD: tegra_sdhc.c,v 1.15.2.1 2017/04/26 02:53:01 pgoyette Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define TEGRA_SDHC_NO_SDR104 30 31 #include "locators.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.15.2.1 2017/04/26 02:53:01 pgoyette Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 43 #include <dev/sdmmc/sdhcreg.h> 44 #include <dev/sdmmc/sdhcvar.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #include <arm/nvidia/tegra_reg.h> 48 #include <arm/nvidia/tegra_var.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 static int tegra_sdhc_match(device_t, cfdata_t, void *); 53 static void tegra_sdhc_attach(device_t, device_t, void *); 54 55 static int tegra_sdhc_card_detect(struct sdhc_softc *); 56 static int tegra_sdhc_write_protect(struct sdhc_softc *); 57 static int tegra_sdhc_signal_voltage(struct sdhc_softc *, int); 58 59 struct tegra_sdhc_softc { 60 struct sdhc_softc sc; 61 62 struct clk *sc_clk; 63 struct fdtbus_reset *sc_rst; 64 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; 67 bus_size_t sc_bsz; 68 struct sdhc_host *sc_host; 69 void *sc_ih; 70 71 struct fdtbus_gpio_pin *sc_pin_cd; 72 struct fdtbus_gpio_pin *sc_pin_power; 73 struct fdtbus_gpio_pin *sc_pin_wp; 74 75 struct fdtbus_regulator *sc_reg_vqmmc; 76 }; 77 78 CFATTACH_DECL_NEW(tegra_sdhc, sizeof(struct tegra_sdhc_softc), 79 tegra_sdhc_match, tegra_sdhc_attach, NULL, NULL); 80 81 static int 82 tegra_sdhc_match(device_t parent, cfdata_t cf, void *aux) 83 { 84 const char * const compatible[] = { "nvidia,tegra124-sdhci", NULL }; 85 struct fdt_attach_args * const faa = aux; 86 87 return of_match_compatible(faa->faa_phandle, compatible); 88 } 89 90 static void 91 tegra_sdhc_attach(device_t parent, device_t self, void *aux) 92 { 93 struct tegra_sdhc_softc * const sc = device_private(self); 94 struct fdt_attach_args * const faa = aux; 95 char intrstr[128]; 96 bus_addr_t addr; 97 bus_size_t size; 98 u_int bus_width; 99 int error; 100 101 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 102 aprint_error(": couldn't get registers\n"); 103 return; 104 } 105 106 if (of_getprop_uint32(faa->faa_phandle, "bus-width", &bus_width)) 107 bus_width = 4; 108 109 sc->sc.sc_dev = self; 110 sc->sc.sc_dmat = faa->faa_dmat; 111 sc->sc.sc_flags = SDHC_FLAG_32BIT_ACCESS | 112 SDHC_FLAG_NO_PWR0 | 113 SDHC_FLAG_NO_CLKBASE | 114 SDHC_FLAG_NO_TIMEOUT | 115 SDHC_FLAG_SINGLE_POWER_WRITE | 116 SDHC_FLAG_NO_HS_BIT | 117 SDHC_FLAG_USE_DMA | 118 SDHC_FLAG_USE_ADMA2; 119 if (bus_width == 8) { 120 sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE; 121 } 122 sc->sc.sc_host = &sc->sc_host; 123 124 sc->sc_bst = faa->faa_bst; 125 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 126 if (error) { 127 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 128 return; 129 } 130 sc->sc_bsz = size; 131 132 #ifdef TEGRA_SDHC_NO_SDR104 133 /* XXX SDR104 requires a custom tuning method on Tegra K1 */ 134 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 135 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 136 SDHC_CAPABILITIES); 137 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 138 SDHC_CAPABILITIES2); 139 sc->sc.sc_caps2 &= ~SDHC_SDR104_SUPP; 140 #endif 141 142 sc->sc_pin_power = fdtbus_gpio_acquire(faa->faa_phandle, 143 "power-gpios", GPIO_PIN_OUTPUT); 144 if (sc->sc_pin_power) 145 fdtbus_gpio_write(sc->sc_pin_power, 1); 146 147 sc->sc_pin_cd = fdtbus_gpio_acquire(faa->faa_phandle, 148 "cd-gpios", GPIO_PIN_INPUT); 149 sc->sc_pin_wp = fdtbus_gpio_acquire(faa->faa_phandle, 150 "wp-gpios", GPIO_PIN_INPUT); 151 152 if (sc->sc_pin_cd) { 153 sc->sc.sc_vendor_card_detect = tegra_sdhc_card_detect; 154 sc->sc.sc_flags |= SDHC_FLAG_POLL_CARD_DET; 155 } 156 if (sc->sc_pin_wp) { 157 sc->sc.sc_vendor_write_protect = tegra_sdhc_write_protect; 158 } 159 160 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(faa->faa_phandle, 161 "vqmmc-supply"); 162 if (sc->sc_reg_vqmmc) { 163 sc->sc.sc_vendor_signal_voltage = tegra_sdhc_signal_voltage; 164 } 165 166 sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0); 167 if (sc->sc_clk == NULL) { 168 aprint_error(": couldn't get clock\n"); 169 return; 170 } 171 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "sdhci"); 172 if (sc->sc_rst == NULL) { 173 aprint_error(": couldn't get reset\n"); 174 return; 175 } 176 177 fdtbus_reset_assert(sc->sc_rst); 178 #ifdef TEGRA_SDHC_NO_SDR104 179 error = clk_set_rate(sc->sc_clk, 100000000); 180 #else 181 error = clk_set_rate(sc->sc_clk, 204000000); 182 #endif 183 if (error) { 184 aprint_error(": couldn't set frequency: %d\n", error); 185 return; 186 } 187 error = clk_enable(sc->sc_clk); 188 if (error) { 189 aprint_error(": couldn't enable clock: %d\n", error); 190 return; 191 } 192 fdtbus_reset_deassert(sc->sc_rst); 193 194 sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000; 195 196 aprint_naive("\n"); 197 aprint_normal(": SDMMC (%u kHz)\n", sc->sc.sc_clkbase); 198 199 if (sc->sc.sc_clkbase == 0) { 200 aprint_error_dev(self, "couldn't determine frequency\n"); 201 return; 202 } 203 204 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 205 aprint_error_dev(self, "failed to decode interrupt\n"); 206 return; 207 } 208 209 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SDMMC, 0, 210 sdhc_intr, &sc->sc); 211 if (sc->sc_ih == NULL) { 212 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 213 intrstr); 214 return; 215 } 216 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 217 218 error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz); 219 if (error) { 220 aprint_error_dev(self, "couldn't initialize host, error = %d\n", 221 error); 222 fdtbus_intr_disestablish(faa->faa_phandle, sc->sc_ih); 223 sc->sc_ih = NULL; 224 return; 225 } 226 } 227 228 static int 229 tegra_sdhc_card_detect(struct sdhc_softc *ssc) 230 { 231 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 232 233 KASSERT(sc->sc_pin_cd != NULL); 234 235 return fdtbus_gpio_read(sc->sc_pin_cd); 236 } 237 238 static int 239 tegra_sdhc_write_protect(struct sdhc_softc *ssc) 240 { 241 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 242 243 KASSERT(sc->sc_pin_wp != NULL); 244 245 return fdtbus_gpio_read(sc->sc_pin_wp); 246 } 247 248 static int 249 tegra_sdhc_signal_voltage(struct sdhc_softc *ssc, int signal_voltage) 250 { 251 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 252 u_int uvol; 253 int error; 254 255 KASSERT(sc->sc_reg_vqmmc != NULL); 256 257 switch (signal_voltage) { 258 case SDMMC_SIGNAL_VOLTAGE_330: 259 uvol = 3300000; 260 break; 261 case SDMMC_SIGNAL_VOLTAGE_180: 262 uvol = 1800000; 263 break; 264 default: 265 return EINVAL; 266 } 267 268 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 269 if (error != 0) 270 return error; 271 272 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 273 } 274
Indexes created Thu Oct 30 16:09:53 GMT 2025