tegra_sdhc.c revision 1.18
1 /* $NetBSD: tegra_sdhc.c,v 1.18 2017/04/22 17:41:20 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define TEGRA_SDHC_NO_SDR104 30 31 #include "locators.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.18 2017/04/22 17:41:20 jmcneill Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 43 #include <dev/sdmmc/sdhcreg.h> 44 #include <dev/sdmmc/sdhcvar.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #include <arm/nvidia/tegra_reg.h> 48 #include <arm/nvidia/tegra_var.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 static int tegra_sdhc_match(device_t, cfdata_t, void *); 53 static void tegra_sdhc_attach(device_t, device_t, void *); 54 55 static int tegra_sdhc_card_detect(struct sdhc_softc *); 56 static int tegra_sdhc_write_protect(struct sdhc_softc *); 57 58 struct tegra_sdhc_softc { 59 struct sdhc_softc sc; 60 61 struct clk *sc_clk; 62 struct fdtbus_reset *sc_rst; 63 64 bus_space_tag_t sc_bst; 65 bus_space_handle_t sc_bsh; 66 bus_size_t sc_bsz; 67 struct sdhc_host *sc_host; 68 void *sc_ih; 69 70 struct fdtbus_gpio_pin *sc_pin_cd; 71 struct fdtbus_gpio_pin *sc_pin_power; 72 struct fdtbus_gpio_pin *sc_pin_wp; 73 }; 74 75 CFATTACH_DECL_NEW(tegra_sdhc, sizeof(struct tegra_sdhc_softc), 76 tegra_sdhc_match, tegra_sdhc_attach, NULL, NULL); 77 78 static int 79 tegra_sdhc_match(device_t parent, cfdata_t cf, void *aux) 80 { 81 const char * const compatible[] = { "nvidia,tegra124-sdhci", NULL }; 82 struct fdt_attach_args * const faa = aux; 83 84 return of_match_compatible(faa->faa_phandle, compatible); 85 } 86 87 static void 88 tegra_sdhc_attach(device_t parent, device_t self, void *aux) 89 { 90 struct tegra_sdhc_softc * const sc = device_private(self); 91 struct fdt_attach_args * const faa = aux; 92 char intrstr[128]; 93 bus_addr_t addr; 94 bus_size_t size; 95 u_int bus_width; 96 int error; 97 98 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 99 aprint_error(": couldn't get registers\n"); 100 return; 101 } 102 103 if (of_getprop_uint32(faa->faa_phandle, "bus-width", &bus_width)) 104 bus_width = 4; 105 106 sc->sc.sc_dev = self; 107 sc->sc.sc_dmat = faa->faa_dmat; 108 sc->sc.sc_flags = SDHC_FLAG_32BIT_ACCESS | 109 SDHC_FLAG_NO_PWR0 | 110 SDHC_FLAG_NO_CLKBASE | 111 SDHC_FLAG_NO_TIMEOUT | 112 SDHC_FLAG_SINGLE_POWER_WRITE | 113 SDHC_FLAG_NO_HS_BIT | 114 SDHC_FLAG_USE_DMA | 115 SDHC_FLAG_USE_ADMA2; 116 if (bus_width == 8) { 117 sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE; 118 } 119 sc->sc.sc_host = &sc->sc_host; 120 121 sc->sc_bst = faa->faa_bst; 122 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 123 if (error) { 124 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 125 return; 126 } 127 sc->sc_bsz = size; 128 129 #ifdef TEGRA_SDHC_NO_SDR104 130 /* XXX SDR104 requires a custom tuning method on Tegra K1 */ 131 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 132 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 133 SDHC_CAPABILITIES); 134 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 135 SDHC_CAPABILITIES2); 136 sc->sc.sc_caps2 &= ~SDHC_SDR104_SUPP; 137 #endif 138 139 sc->sc_pin_power = fdtbus_gpio_acquire(faa->faa_phandle, 140 "power-gpios", GPIO_PIN_OUTPUT); 141 if (sc->sc_pin_power) 142 fdtbus_gpio_write(sc->sc_pin_power, 1); 143 144 sc->sc_pin_cd = fdtbus_gpio_acquire(faa->faa_phandle, 145 "cd-gpios", GPIO_PIN_INPUT); 146 sc->sc_pin_wp = fdtbus_gpio_acquire(faa->faa_phandle, 147 "wp-gpios", GPIO_PIN_INPUT); 148 149 if (sc->sc_pin_cd) { 150 sc->sc.sc_vendor_card_detect = tegra_sdhc_card_detect; 151 sc->sc.sc_flags |= SDHC_FLAG_POLL_CARD_DET; 152 } 153 if (sc->sc_pin_wp) { 154 sc->sc.sc_vendor_write_protect = tegra_sdhc_write_protect; 155 } 156 157 sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0); 158 if (sc->sc_clk == NULL) { 159 aprint_error(": couldn't get clock\n"); 160 return; 161 } 162 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "sdhci"); 163 if (sc->sc_rst == NULL) { 164 aprint_error(": couldn't get reset\n"); 165 return; 166 } 167 168 fdtbus_reset_assert(sc->sc_rst); 169 #ifdef TEGRA_SDHC_NO_SDR104 170 error = clk_set_rate(sc->sc_clk, 100000000); 171 #else 172 error = clk_set_rate(sc->sc_clk, 204000000); 173 #endif 174 if (error) { 175 aprint_error(": couldn't set frequency: %d\n", error); 176 return; 177 } 178 error = clk_enable(sc->sc_clk); 179 if (error) { 180 aprint_error(": couldn't enable clock: %d\n", error); 181 return; 182 } 183 fdtbus_reset_deassert(sc->sc_rst); 184 185 sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000; 186 187 aprint_naive("\n"); 188 aprint_normal(": SDMMC (%u kHz)\n", sc->sc.sc_clkbase); 189 190 if (sc->sc.sc_clkbase == 0) { 191 aprint_error_dev(self, "couldn't determine frequency\n"); 192 return; 193 } 194 195 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 196 aprint_error_dev(self, "failed to decode interrupt\n"); 197 return; 198 } 199 200 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SDMMC, 0, 201 sdhc_intr, &sc->sc); 202 if (sc->sc_ih == NULL) { 203 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 204 intrstr); 205 return; 206 } 207 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 208 209 error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz); 210 if (error) { 211 aprint_error_dev(self, "couldn't initialize host, error = %d\n", 212 error); 213 fdtbus_intr_disestablish(faa->faa_phandle, sc->sc_ih); 214 sc->sc_ih = NULL; 215 return; 216 } 217 } 218 219 static int 220 tegra_sdhc_card_detect(struct sdhc_softc *ssc) 221 { 222 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 223 224 KASSERT(sc->sc_pin_cd != NULL); 225 226 return fdtbus_gpio_read(sc->sc_pin_cd); 227 } 228 229 static int 230 tegra_sdhc_write_protect(struct sdhc_softc *ssc) 231 { 232 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 233 234 KASSERT(sc->sc_pin_wp != NULL); 235 236 return fdtbus_gpio_read(sc->sc_pin_wp); 237 } 238
Indexes created Mon Oct 27 20:09:55 GMT 2025