tegra_sdhc.c revision 1.21.2.2
1 /* $NetBSD: tegra_sdhc.c,v 1.21.2.2 2017/12/03 11:35:54 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define TEGRA_SDHC_NO_SDR104 30 31 #include "locators.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.21.2.2 2017/12/03 11:35:54 jdolecek Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 43 #include <dev/sdmmc/sdhcreg.h> 44 #include <dev/sdmmc/sdhcvar.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #include <arm/nvidia/tegra_reg.h> 48 #include <arm/nvidia/tegra_var.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 static int tegra_sdhc_match(device_t, cfdata_t, void *); 53 static void tegra_sdhc_attach(device_t, device_t, void *); 54 55 static int tegra_sdhc_card_detect(struct sdhc_softc *); 56 static int tegra_sdhc_write_protect(struct sdhc_softc *); 57 static int tegra_sdhc_signal_voltage(struct sdhc_softc *, int); 58 59 struct tegra_sdhc_softc { 60 struct sdhc_softc sc; 61 62 struct clk *sc_clk; 63 struct fdtbus_reset *sc_rst; 64 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; 67 bus_size_t sc_bsz; 68 struct sdhc_host *sc_host; 69 void *sc_ih; 70 71 struct fdtbus_gpio_pin *sc_pin_cd; 72 struct fdtbus_gpio_pin *sc_pin_power; 73 struct fdtbus_gpio_pin *sc_pin_wp; 74 75 struct fdtbus_regulator *sc_reg_vqmmc; 76 }; 77 78 CFATTACH_DECL_NEW(tegra_sdhc, sizeof(struct tegra_sdhc_softc), 79 tegra_sdhc_match, tegra_sdhc_attach, NULL, NULL); 80 81 static int 82 tegra_sdhc_match(device_t parent, cfdata_t cf, void *aux) 83 { 84 const char * const compatible[] = { 85 "nvidia,tegra210-sdhci", 86 "nvidia,tegra124-sdhci", 87 NULL 88 }; 89 struct fdt_attach_args * const faa = aux; 90 91 return of_match_compatible(faa->faa_phandle, compatible); 92 } 93 94 static void 95 tegra_sdhc_attach(device_t parent, device_t self, void *aux) 96 { 97 struct tegra_sdhc_softc * const sc = device_private(self); 98 struct fdt_attach_args * const faa = aux; 99 char intrstr[128]; 100 bus_addr_t addr; 101 bus_size_t size; 102 u_int bus_width; 103 int error; 104 105 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 106 aprint_error(": couldn't get registers\n"); 107 return; 108 } 109 110 if (of_getprop_uint32(faa->faa_phandle, "bus-width", &bus_width)) 111 bus_width = 4; 112 113 sc->sc.sc_dev = self; 114 sc->sc.sc_dmat = faa->faa_dmat; 115 sc->sc.sc_flags = SDHC_FLAG_32BIT_ACCESS | 116 SDHC_FLAG_NO_PWR0 | 117 SDHC_FLAG_NO_CLKBASE | 118 SDHC_FLAG_NO_TIMEOUT | 119 SDHC_FLAG_SINGLE_POWER_WRITE | 120 SDHC_FLAG_NO_HS_BIT | 121 SDHC_FLAG_USE_DMA | 122 SDHC_FLAG_USE_ADMA2; 123 if (bus_width == 8) { 124 sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE; 125 } 126 sc->sc.sc_host = &sc->sc_host; 127 128 sc->sc_bst = faa->faa_bst; 129 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 130 if (error) { 131 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 132 return; 133 } 134 sc->sc_bsz = size; 135 136 #ifdef TEGRA_SDHC_NO_SDR104 137 /* XXX SDR104 requires a custom tuning method on Tegra K1 */ 138 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 139 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 140 SDHC_CAPABILITIES); 141 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 142 SDHC_CAPABILITIES2); 143 sc->sc.sc_caps2 &= ~SDHC_SDR104_SUPP; 144 #endif 145 146 sc->sc_pin_power = fdtbus_gpio_acquire(faa->faa_phandle, 147 "power-gpios", GPIO_PIN_OUTPUT); 148 if (sc->sc_pin_power) 149 fdtbus_gpio_write(sc->sc_pin_power, 1); 150 151 sc->sc_pin_cd = fdtbus_gpio_acquire(faa->faa_phandle, 152 "cd-gpios", GPIO_PIN_INPUT); 153 sc->sc_pin_wp = fdtbus_gpio_acquire(faa->faa_phandle, 154 "wp-gpios", GPIO_PIN_INPUT); 155 156 if (sc->sc_pin_cd) { 157 sc->sc.sc_vendor_card_detect = tegra_sdhc_card_detect; 158 sc->sc.sc_flags |= SDHC_FLAG_POLL_CARD_DET; 159 } 160 if (sc->sc_pin_wp) { 161 sc->sc.sc_vendor_write_protect = tegra_sdhc_write_protect; 162 } 163 164 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(faa->faa_phandle, 165 "vqmmc-supply"); 166 if (sc->sc_reg_vqmmc) { 167 sc->sc.sc_vendor_signal_voltage = tegra_sdhc_signal_voltage; 168 } else { 169 /* Regulator required for UHS signaling */ 170 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 171 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 172 SDHC_CAPABILITIES); 173 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 174 SDHC_CAPABILITIES2); 175 sc->sc.sc_caps2 &= ~(SDHC_SDR50_SUPP|SDHC_SDR104_SUPP|SDHC_DDR50_SUPP); 176 } 177 178 sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0); 179 if (sc->sc_clk == NULL) { 180 aprint_error(": couldn't get clock\n"); 181 return; 182 } 183 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "sdhci"); 184 if (sc->sc_rst == NULL) { 185 aprint_error(": couldn't get reset\n"); 186 return; 187 } 188 189 fdtbus_reset_assert(sc->sc_rst); 190 #ifdef TEGRA_SDHC_NO_SDR104 191 error = clk_set_rate(sc->sc_clk, 100000000); 192 #else 193 error = clk_set_rate(sc->sc_clk, 204000000); 194 #endif 195 if (error) { 196 aprint_error(": couldn't set frequency: %d\n", error); 197 return; 198 } 199 error = clk_enable(sc->sc_clk); 200 if (error) { 201 aprint_error(": couldn't enable clock: %d\n", error); 202 return; 203 } 204 fdtbus_reset_deassert(sc->sc_rst); 205 206 sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000; 207 208 aprint_naive("\n"); 209 aprint_normal(": SDMMC (%u kHz)\n", sc->sc.sc_clkbase); 210 211 if (sc->sc.sc_clkbase == 0) { 212 aprint_error_dev(self, "couldn't determine frequency\n"); 213 return; 214 } 215 216 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 217 aprint_error_dev(self, "failed to decode interrupt\n"); 218 return; 219 } 220 221 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SDMMC, 0, 222 sdhc_intr, &sc->sc); 223 if (sc->sc_ih == NULL) { 224 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 225 intrstr); 226 return; 227 } 228 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 229 230 error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz); 231 if (error) { 232 aprint_error_dev(self, "couldn't initialize host, error = %d\n", 233 error); 234 fdtbus_intr_disestablish(faa->faa_phandle, sc->sc_ih); 235 sc->sc_ih = NULL; 236 return; 237 } 238 } 239 240 static int 241 tegra_sdhc_card_detect(struct sdhc_softc *ssc) 242 { 243 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 244 245 KASSERT(sc->sc_pin_cd != NULL); 246 247 return fdtbus_gpio_read(sc->sc_pin_cd); 248 } 249 250 static int 251 tegra_sdhc_write_protect(struct sdhc_softc *ssc) 252 { 253 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 254 255 KASSERT(sc->sc_pin_wp != NULL); 256 257 return fdtbus_gpio_read(sc->sc_pin_wp); 258 } 259 260 static int 261 tegra_sdhc_signal_voltage(struct sdhc_softc *ssc, int signal_voltage) 262 { 263 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 264 u_int uvol; 265 int error; 266 267 KASSERT(sc->sc_reg_vqmmc != NULL); 268 269 switch (signal_voltage) { 270 case SDMMC_SIGNAL_VOLTAGE_330: 271 uvol = 3300000; 272 break; 273 case SDMMC_SIGNAL_VOLTAGE_180: 274 uvol = 1800000; 275 break; 276 default: 277 return EINVAL; 278 } 279 280 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 281 if (error != 0) 282 return error; 283 284 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 285 } 286
Indexes created Mon Oct 27 02:09:54 GMT 2025