tegra_sdhc.c revision 1.21.6.1
1 /* $NetBSD: tegra_sdhc.c,v 1.21.6.1 2019/06/10 22:05:55 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define TEGRA_SDHC_NO_SDR104 30 31 #include "locators.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.21.6.1 2019/06/10 22:05:55 christos Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 43 #include <dev/sdmmc/sdhcreg.h> 44 #include <dev/sdmmc/sdhcvar.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #include <arm/nvidia/tegra_reg.h> 48 #include <arm/nvidia/tegra_var.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 static int tegra_sdhc_match(device_t, cfdata_t, void *); 53 static void tegra_sdhc_attach(device_t, device_t, void *); 54 55 static int tegra_sdhc_card_detect(struct sdhc_softc *); 56 static int tegra_sdhc_write_protect(struct sdhc_softc *); 57 static int tegra_sdhc_signal_voltage(struct sdhc_softc *, int); 58 59 struct tegra_sdhc_softc { 60 struct sdhc_softc sc; 61 62 struct clk *sc_clk; 63 struct fdtbus_reset *sc_rst; 64 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; 67 bus_size_t sc_bsz; 68 struct sdhc_host *sc_host; 69 void *sc_ih; 70 71 struct fdtbus_gpio_pin *sc_pin_cd; 72 struct fdtbus_gpio_pin *sc_pin_power; 73 struct fdtbus_gpio_pin *sc_pin_wp; 74 75 struct fdtbus_regulator *sc_reg_vqmmc; 76 }; 77 78 CFATTACH_DECL_NEW(tegra_sdhc, sizeof(struct tegra_sdhc_softc), 79 tegra_sdhc_match, tegra_sdhc_attach, NULL, NULL); 80 81 static int 82 tegra_sdhc_match(device_t parent, cfdata_t cf, void *aux) 83 { 84 const char * const compatible[] = { 85 "nvidia,tegra210-sdhci", 86 "nvidia,tegra124-sdhci", 87 NULL 88 }; 89 struct fdt_attach_args * const faa = aux; 90 91 return of_match_compatible(faa->faa_phandle, compatible); 92 } 93 94 static void 95 tegra_sdhc_attach(device_t parent, device_t self, void *aux) 96 { 97 struct tegra_sdhc_softc * const sc = device_private(self); 98 struct fdt_attach_args * const faa = aux; 99 char intrstr[128]; 100 bus_addr_t addr; 101 bus_size_t size; 102 u_int bus_width; 103 int error; 104 105 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 106 aprint_error(": couldn't get registers\n"); 107 return; 108 } 109 110 if (of_getprop_uint32(faa->faa_phandle, "bus-width", &bus_width)) 111 bus_width = 4; 112 113 sc->sc.sc_dev = self; 114 sc->sc.sc_dmat = faa->faa_dmat; 115 sc->sc.sc_flags = SDHC_FLAG_32BIT_ACCESS | 116 SDHC_FLAG_NO_PWR0 | 117 SDHC_FLAG_NO_CLKBASE | 118 SDHC_FLAG_NO_TIMEOUT | 119 SDHC_FLAG_SINGLE_POWER_WRITE | 120 SDHC_FLAG_NO_HS_BIT | 121 SDHC_FLAG_USE_DMA | 122 SDHC_FLAG_USE_ADMA2; 123 if (bus_width == 8) { 124 sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE; 125 } 126 sc->sc.sc_host = &sc->sc_host; 127 128 sc->sc_bst = faa->faa_bst; 129 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 130 if (error) { 131 aprint_error(": couldn't map %#" PRIx64 ": %d", 132 (uint64_t)addr, error); 133 return; 134 } 135 sc->sc_bsz = size; 136 137 #ifdef TEGRA_SDHC_NO_SDR104 138 /* XXX SDR104 requires a custom tuning method on Tegra K1 */ 139 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 140 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 141 SDHC_CAPABILITIES); 142 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 143 SDHC_CAPABILITIES2); 144 sc->sc.sc_caps2 &= ~SDHC_SDR104_SUPP; 145 #endif 146 147 sc->sc_pin_power = fdtbus_gpio_acquire(faa->faa_phandle, 148 "power-gpios", GPIO_PIN_OUTPUT); 149 if (sc->sc_pin_power) 150 fdtbus_gpio_write(sc->sc_pin_power, 1); 151 152 sc->sc_pin_cd = fdtbus_gpio_acquire(faa->faa_phandle, 153 "cd-gpios", GPIO_PIN_INPUT); 154 sc->sc_pin_wp = fdtbus_gpio_acquire(faa->faa_phandle, 155 "wp-gpios", GPIO_PIN_INPUT); 156 157 if (sc->sc_pin_cd) { 158 sc->sc.sc_vendor_card_detect = tegra_sdhc_card_detect; 159 sc->sc.sc_flags |= SDHC_FLAG_POLL_CARD_DET; 160 } 161 if (sc->sc_pin_wp) { 162 sc->sc.sc_vendor_write_protect = tegra_sdhc_write_protect; 163 } 164 165 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(faa->faa_phandle, 166 "vqmmc-supply"); 167 if (sc->sc_reg_vqmmc) { 168 sc->sc.sc_vendor_signal_voltage = tegra_sdhc_signal_voltage; 169 } else { 170 /* Regulator required for UHS signaling */ 171 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 172 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 173 SDHC_CAPABILITIES); 174 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 175 SDHC_CAPABILITIES2); 176 sc->sc.sc_caps2 &= ~(SDHC_SDR50_SUPP|SDHC_SDR104_SUPP|SDHC_DDR50_SUPP); 177 } 178 179 sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0); 180 if (sc->sc_clk == NULL) { 181 aprint_error(": couldn't get clock\n"); 182 return; 183 } 184 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "sdhci"); 185 if (sc->sc_rst == NULL) { 186 aprint_error(": couldn't get reset\n"); 187 return; 188 } 189 190 fdtbus_reset_assert(sc->sc_rst); 191 #ifdef TEGRA_SDHC_NO_SDR104 192 error = clk_set_rate(sc->sc_clk, 100000000); 193 #else 194 error = clk_set_rate(sc->sc_clk, 204000000); 195 #endif 196 if (error) { 197 aprint_error(": couldn't set frequency: %d\n", error); 198 return; 199 } 200 error = clk_enable(sc->sc_clk); 201 if (error) { 202 aprint_error(": couldn't enable clock: %d\n", error); 203 return; 204 } 205 fdtbus_reset_deassert(sc->sc_rst); 206 207 sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000; 208 209 aprint_naive("\n"); 210 aprint_normal(": SDMMC (%u kHz)\n", sc->sc.sc_clkbase); 211 212 if (sc->sc.sc_clkbase == 0) { 213 aprint_error_dev(self, "couldn't determine frequency\n"); 214 return; 215 } 216 217 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 218 aprint_error_dev(self, "failed to decode interrupt\n"); 219 return; 220 } 221 222 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SDMMC, 0, 223 sdhc_intr, &sc->sc); 224 if (sc->sc_ih == NULL) { 225 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 226 intrstr); 227 return; 228 } 229 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 230 231 error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz); 232 if (error) { 233 aprint_error_dev(self, "couldn't initialize host, error = %d\n", 234 error); 235 fdtbus_intr_disestablish(faa->faa_phandle, sc->sc_ih); 236 sc->sc_ih = NULL; 237 return; 238 } 239 } 240 241 static int 242 tegra_sdhc_card_detect(struct sdhc_softc *ssc) 243 { 244 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 245 246 KASSERT(sc->sc_pin_cd != NULL); 247 248 return fdtbus_gpio_read(sc->sc_pin_cd); 249 } 250 251 static int 252 tegra_sdhc_write_protect(struct sdhc_softc *ssc) 253 { 254 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 255 256 KASSERT(sc->sc_pin_wp != NULL); 257 258 return fdtbus_gpio_read(sc->sc_pin_wp); 259 } 260 261 static int 262 tegra_sdhc_signal_voltage(struct sdhc_softc *ssc, int signal_voltage) 263 { 264 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 265 u_int uvol; 266 int error; 267 268 KASSERT(sc->sc_reg_vqmmc != NULL); 269 270 switch (signal_voltage) { 271 case SDMMC_SIGNAL_VOLTAGE_330: 272 uvol = 3300000; 273 break; 274 case SDMMC_SIGNAL_VOLTAGE_180: 275 uvol = 1800000; 276 break; 277 default: 278 return EINVAL; 279 } 280 281 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 282 if (error != 0) 283 return error; 284 285 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 286 } 287
Indexes created Sun Oct 26 17:10:13 GMT 2025