tegra_sdhc.c revision 1.25
1 /* $NetBSD: tegra_sdhc.c,v 1.25 2020/02/15 12:45:05 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #define TEGRA_SDHC_NO_SDR104 30 31 #include "locators.h" 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tegra_sdhc.c,v 1.25 2020/02/15 12:45:05 skrll Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 #include <sys/intr.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 43 #include <dev/sdmmc/sdhcreg.h> 44 #include <dev/sdmmc/sdhcvar.h> 45 #include <dev/sdmmc/sdmmcvar.h> 46 47 #include <arm/nvidia/tegra_reg.h> 48 #include <arm/nvidia/tegra_var.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 static int tegra_sdhc_match(device_t, cfdata_t, void *); 53 static void tegra_sdhc_attach(device_t, device_t, void *); 54 55 static int tegra_sdhc_card_detect(struct sdhc_softc *); 56 static int tegra_sdhc_write_protect(struct sdhc_softc *); 57 static int tegra_sdhc_signal_voltage(struct sdhc_softc *, int); 58 59 struct tegra_sdhc_softc { 60 struct sdhc_softc sc; 61 62 struct clk *sc_clk; 63 struct fdtbus_reset *sc_rst; 64 65 bus_space_tag_t sc_bst; 66 bus_space_handle_t sc_bsh; 67 bus_size_t sc_bsz; 68 struct sdhc_host *sc_host; 69 void *sc_ih; 70 71 struct fdtbus_gpio_pin *sc_pin_cd; 72 struct fdtbus_gpio_pin *sc_pin_power; 73 struct fdtbus_gpio_pin *sc_pin_wp; 74 75 struct fdtbus_regulator *sc_reg_vqmmc; 76 }; 77 78 CFATTACH_DECL_NEW(tegra_sdhc, sizeof(struct tegra_sdhc_softc), 79 tegra_sdhc_match, tegra_sdhc_attach, NULL, NULL); 80 81 static int 82 tegra_sdhc_match(device_t parent, cfdata_t cf, void *aux) 83 { 84 const char * const compatible[] = { 85 "nvidia,tegra210-sdhci", 86 "nvidia,tegra124-sdhci", 87 NULL 88 }; 89 struct fdt_attach_args * const faa = aux; 90 91 return of_match_compatible(faa->faa_phandle, compatible); 92 } 93 94 static void 95 tegra_sdhc_attach(device_t parent, device_t self, void *aux) 96 { 97 struct tegra_sdhc_softc * const sc = device_private(self); 98 struct fdt_attach_args * const faa = aux; 99 char intrstr[128]; 100 bus_addr_t addr; 101 bus_size_t size; 102 u_int bus_width; 103 int error; 104 105 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 106 aprint_error(": couldn't get registers\n"); 107 return; 108 } 109 110 if (of_getprop_uint32(faa->faa_phandle, "bus-width", &bus_width)) 111 bus_width = 4; 112 113 sc->sc.sc_dev = self; 114 115 error = bus_dmatag_subregion(faa->faa_dmat, 0, 0xffffffff, 116 &sc->sc.sc_dmat, BUS_DMA_WAITOK); 117 if (error != 0) { 118 aprint_error(": couldn't create DMA tag: %d\n", error); 119 return; 120 } 121 122 sc->sc.sc_flags = SDHC_FLAG_32BIT_ACCESS | 123 SDHC_FLAG_NO_PWR0 | 124 SDHC_FLAG_NO_CLKBASE | 125 SDHC_FLAG_NO_TIMEOUT | 126 SDHC_FLAG_SINGLE_POWER_WRITE | 127 SDHC_FLAG_NO_HS_BIT | 128 SDHC_FLAG_USE_DMA | 129 SDHC_FLAG_USE_ADMA2; 130 if (bus_width == 8) { 131 sc->sc.sc_flags |= SDHC_FLAG_8BIT_MODE; 132 } 133 sc->sc.sc_host = &sc->sc_host; 134 135 sc->sc_bst = faa->faa_bst; 136 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 137 if (error) { 138 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 139 return; 140 } 141 sc->sc_bsz = size; 142 143 #ifdef TEGRA_SDHC_NO_SDR104 144 /* XXX SDR104 requires a custom tuning method on Tegra K1 */ 145 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 146 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 147 SDHC_CAPABILITIES); 148 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 149 SDHC_CAPABILITIES2); 150 sc->sc.sc_caps2 &= ~SDHC_SDR104_SUPP; 151 #endif 152 153 sc->sc_pin_power = fdtbus_gpio_acquire(faa->faa_phandle, 154 "power-gpios", GPIO_PIN_OUTPUT); 155 if (sc->sc_pin_power) 156 fdtbus_gpio_write(sc->sc_pin_power, 1); 157 158 sc->sc_pin_cd = fdtbus_gpio_acquire(faa->faa_phandle, 159 "cd-gpios", GPIO_PIN_INPUT); 160 sc->sc_pin_wp = fdtbus_gpio_acquire(faa->faa_phandle, 161 "wp-gpios", GPIO_PIN_INPUT); 162 163 if (sc->sc_pin_cd) { 164 sc->sc.sc_vendor_card_detect = tegra_sdhc_card_detect; 165 sc->sc.sc_flags |= SDHC_FLAG_POLL_CARD_DET; 166 } 167 if (sc->sc_pin_wp) { 168 sc->sc.sc_vendor_write_protect = tegra_sdhc_write_protect; 169 } 170 171 sc->sc_reg_vqmmc = fdtbus_regulator_acquire(faa->faa_phandle, 172 "vqmmc-supply"); 173 if (sc->sc_reg_vqmmc) { 174 sc->sc.sc_vendor_signal_voltage = tegra_sdhc_signal_voltage; 175 } else { 176 /* Regulator required for UHS signaling */ 177 sc->sc.sc_flags |= SDHC_FLAG_HOSTCAPS; 178 sc->sc.sc_caps = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 179 SDHC_CAPABILITIES); 180 sc->sc.sc_caps2 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 181 SDHC_CAPABILITIES2); 182 sc->sc.sc_caps2 &= ~(SDHC_SDR50_SUPP|SDHC_SDR104_SUPP|SDHC_DDR50_SUPP); 183 } 184 185 sc->sc_clk = fdtbus_clock_get_index(faa->faa_phandle, 0); 186 if (sc->sc_clk == NULL) { 187 aprint_error(": couldn't get clock\n"); 188 return; 189 } 190 sc->sc_rst = fdtbus_reset_get(faa->faa_phandle, "sdhci"); 191 if (sc->sc_rst == NULL) { 192 aprint_error(": couldn't get reset\n"); 193 return; 194 } 195 196 fdtbus_reset_assert(sc->sc_rst); 197 #ifdef TEGRA_SDHC_NO_SDR104 198 error = clk_set_rate(sc->sc_clk, 100000000); 199 #else 200 error = clk_set_rate(sc->sc_clk, 204000000); 201 #endif 202 if (error) { 203 aprint_error(": couldn't set frequency: %d\n", error); 204 return; 205 } 206 error = clk_enable(sc->sc_clk); 207 if (error) { 208 aprint_error(": couldn't enable clock: %d\n", error); 209 return; 210 } 211 fdtbus_reset_deassert(sc->sc_rst); 212 213 sc->sc.sc_clkbase = clk_get_rate(sc->sc_clk) / 1000; 214 215 aprint_naive("\n"); 216 aprint_normal(": SDMMC (%u kHz)\n", sc->sc.sc_clkbase); 217 218 if (sc->sc.sc_clkbase == 0) { 219 aprint_error_dev(self, "couldn't determine frequency\n"); 220 return; 221 } 222 223 if (!fdtbus_intr_str(faa->faa_phandle, 0, intrstr, sizeof(intrstr))) { 224 aprint_error_dev(self, "failed to decode interrupt\n"); 225 return; 226 } 227 228 sc->sc_ih = fdtbus_intr_establish(faa->faa_phandle, 0, IPL_SDMMC, 0, 229 sdhc_intr, &sc->sc); 230 if (sc->sc_ih == NULL) { 231 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 232 intrstr); 233 return; 234 } 235 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 236 237 error = sdhc_host_found(&sc->sc, sc->sc_bst, sc->sc_bsh, sc->sc_bsz); 238 if (error) { 239 aprint_error_dev(self, "couldn't initialize host, error = %d\n", 240 error); 241 fdtbus_intr_disestablish(faa->faa_phandle, sc->sc_ih); 242 sc->sc_ih = NULL; 243 return; 244 } 245 } 246 247 static int 248 tegra_sdhc_card_detect(struct sdhc_softc *ssc) 249 { 250 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 251 252 KASSERT(sc->sc_pin_cd != NULL); 253 254 return fdtbus_gpio_read(sc->sc_pin_cd); 255 } 256 257 static int 258 tegra_sdhc_write_protect(struct sdhc_softc *ssc) 259 { 260 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 261 262 KASSERT(sc->sc_pin_wp != NULL); 263 264 return fdtbus_gpio_read(sc->sc_pin_wp); 265 } 266 267 static int 268 tegra_sdhc_signal_voltage(struct sdhc_softc *ssc, int signal_voltage) 269 { 270 struct tegra_sdhc_softc *sc = device_private(ssc->sc_dev); 271 u_int uvol; 272 int error; 273 274 KASSERT(sc->sc_reg_vqmmc != NULL); 275 276 switch (signal_voltage) { 277 case SDMMC_SIGNAL_VOLTAGE_330: 278 uvol = 3300000; 279 break; 280 case SDMMC_SIGNAL_VOLTAGE_180: 281 uvol = 1800000; 282 break; 283 default: 284 return EINVAL; 285 } 286 287 error = fdtbus_regulator_set_voltage(sc->sc_reg_vqmmc, uvol, uvol); 288 if (error != 0) 289 return error; 290 291 return fdtbus_regulator_enable(sc->sc_reg_vqmmc); 292 } 293
Indexes created Mon Oct 27 20:09:55 GMT 2025