tegra_soctherm.c revision 1.3
1 /* $NetBSD: tegra_soctherm.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_soctherm.c,v 1.3 2015/12/22 22:10:36 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 40 #include <dev/sysmon/sysmonvar.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_socthermreg.h> 44 #include <arm/nvidia/tegra_var.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define FUSE_TSENSOR_CALIB_CP_TS_BASE __BITS(12,0) 49 #define FUSE_TSENSOR_CALIB_FT_TS_BASE __BITS(25,13) 50 51 #define FUSE_TSENSOR8_CALIB_REG 0x180 52 #define FUSE_TSENSOR8_CALIB_CP_TS_BASE __BITS(9,0) 53 #define FUSE_TSENSOR8_CALIB_FT_TS_BASE __BITS(20,10) 54 55 #define FUSE_SPARE_REALIGNMENT_REG 0x1fc 56 #define FUSE_SPARE_REALIGNMENT_CP __BITS(5,0) 57 #define FUSE_SPARE_REALIGNMENT_FT __BITS(25,21) 58 59 static int tegra_soctherm_match(device_t, cfdata_t, void *); 60 static void tegra_soctherm_attach(device_t, device_t, void *); 61 62 struct tegra_soctherm_config { 63 uint32_t init_pdiv; 64 uint32_t init_hotspot_off; 65 uint32_t nominal_calib_ft; 66 uint32_t nominal_calib_cp; 67 uint32_t tall; 68 uint32_t tsample; 69 uint32_t tiddq_en; 70 uint32_t ten_count; 71 uint32_t pdiv; 72 uint32_t tsample_ate; 73 uint32_t pdiv_ate; 74 }; 75 76 static const struct tegra_soctherm_config tegra124_soctherm_config = { 77 .init_pdiv = 0x8888, 78 .init_hotspot_off = 0x60600, 79 .nominal_calib_ft = 105, 80 .nominal_calib_cp = 25, 81 .tall = 16300, 82 .tsample = 120, 83 .tiddq_en = 1, 84 .ten_count = 1, 85 .pdiv = 8, 86 .tsample_ate = 480, 87 .pdiv_ate = 8 88 }; 89 90 struct tegra_soctherm_sensor { 91 envsys_data_t s_data; 92 u_int s_base; 93 u_int s_fuse; 94 int s_fuse_corr_alpha; 95 int s_fuse_corr_beta; 96 int16_t s_therm_a; 97 int16_t s_therm_b; 98 }; 99 100 static const struct tegra_soctherm_sensor tegra_soctherm_sensors[] = { 101 { .s_data = { .desc = "CPU0" }, .s_base = 0x0c0, .s_fuse = 0x098, 102 .s_fuse_corr_alpha = 1135400, .s_fuse_corr_beta = -6266900 }, 103 { .s_data = { .desc = "CPU1" }, .s_base = 0x0e0, .s_fuse = 0x084, 104 .s_fuse_corr_alpha = 1122220, .s_fuse_corr_beta = -5700700 }, 105 { .s_data = { .desc = "CPU2" }, .s_base = 0x100, .s_fuse = 0x088, 106 .s_fuse_corr_alpha = 1127000, .s_fuse_corr_beta = -6768200 }, 107 { .s_data = { .desc = "CPU3" }, .s_base = 0x120, .s_fuse = 0x12c, 108 .s_fuse_corr_alpha = 1110900, .s_fuse_corr_beta = -6232000 }, 109 { .s_data = { .desc = "MEM0" }, .s_base = 0x140, .s_fuse = 0x158, 110 .s_fuse_corr_alpha = 1122300, .s_fuse_corr_beta = -5936400 }, 111 { .s_data = { .desc = "MEM1" }, .s_base = 0x160, .s_fuse = 0x15c, 112 .s_fuse_corr_alpha = 1145700, .s_fuse_corr_beta = -7124600 }, 113 { .s_data = { .desc = "GPU" }, .s_base = 0x180, .s_fuse = 0x154, 114 .s_fuse_corr_alpha = 1120100, .s_fuse_corr_beta = -6000500 }, 115 { .s_data = { .desc = "PLLX" }, .s_base = 0x1a0, .s_fuse = 0x160, 116 .s_fuse_corr_alpha = 1106500, .s_fuse_corr_beta = -6729300 }, 117 }; 118 119 struct tegra_soctherm_softc { 120 device_t sc_dev; 121 bus_space_tag_t sc_bst; 122 bus_space_handle_t sc_bsh; 123 struct clk *sc_clk_tsensor; 124 struct clk *sc_clk_soctherm; 125 struct fdtbus_reset *sc_rst_soctherm; 126 127 struct sysmon_envsys *sc_sme; 128 struct tegra_soctherm_sensor *sc_sensors; 129 const struct tegra_soctherm_config *sc_config; 130 131 uint32_t sc_base_cp; 132 uint32_t sc_base_ft; 133 int32_t sc_actual_temp_cp; 134 int32_t sc_actual_temp_ft; 135 }; 136 137 static int tegra_soctherm_init_clocks(struct tegra_soctherm_softc *); 138 static void tegra_soctherm_init_sensors(struct tegra_soctherm_softc *); 139 static void tegra_soctherm_init_sensor(struct tegra_soctherm_softc *, 140 struct tegra_soctherm_sensor *); 141 static void tegra_soctherm_refresh(struct sysmon_envsys *, envsys_data_t *); 142 static int tegra_soctherm_decodeint(uint32_t, uint32_t); 143 static int64_t tegra_soctherm_divide(int64_t, int64_t); 144 145 CFATTACH_DECL_NEW(tegra_soctherm, sizeof(struct tegra_soctherm_softc), 146 tegra_soctherm_match, tegra_soctherm_attach, NULL, NULL); 147 148 #define SOCTHERM_READ(sc, reg) \ 149 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 150 #define SOCTHERM_WRITE(sc, reg, val) \ 151 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 152 #define SOCTHERM_SET_CLEAR(sc, reg, set, clr) \ 153 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 154 155 #define SENSOR_READ(sc, s, reg) \ 156 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg)) 157 #define SENSOR_WRITE(sc, s, reg, val) \ 158 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (val)) 159 #define SENSOR_SET_CLEAR(sc, s, reg, set, clr) \ 160 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (set), (clr)) 161 162 static int 163 tegra_soctherm_match(device_t parent, cfdata_t cf, void *aux) 164 { 165 const char * const compatible[] = { "nvidia,tegra124-soctherm", NULL }; 166 struct fdt_attach_args * const faa = aux; 167 168 return of_match_compatible(faa->faa_phandle, compatible); 169 } 170 171 static void 172 tegra_soctherm_attach(device_t parent, device_t self, void *aux) 173 { 174 struct tegra_soctherm_softc * const sc = device_private(self); 175 struct fdt_attach_args * const faa = aux; 176 bus_addr_t addr; 177 bus_size_t size; 178 int error; 179 180 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 181 aprint_error(": couldn't get registers\n"); 182 return; 183 } 184 sc->sc_clk_tsensor = fdtbus_clock_get(faa->faa_phandle, "tsensor"); 185 if (sc->sc_clk_tsensor == NULL) { 186 aprint_error(": couldn't get clock tsensor\n"); 187 return; 188 } 189 sc->sc_clk_soctherm = fdtbus_clock_get(faa->faa_phandle, "soctherm"); 190 if (sc->sc_clk_soctherm == NULL) { 191 aprint_error(": couldn't get clock soctherm\n"); 192 return; 193 } 194 sc->sc_rst_soctherm = fdtbus_reset_get(faa->faa_phandle, "soctherm"); 195 if (sc->sc_rst_soctherm == NULL) { 196 aprint_error(": couldn't get reset soctherm\n"); 197 return; 198 } 199 200 sc->sc_dev = self; 201 sc->sc_bst = faa->faa_bst; 202 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 203 if (error) { 204 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 205 return; 206 } 207 208 aprint_naive("\n"); 209 aprint_normal(": SOC_THERM\n"); 210 211 if (tegra_chip_id() == CHIP_ID_TEGRA124) { 212 sc->sc_config = &tegra124_soctherm_config; 213 } 214 215 if (sc->sc_config == NULL) { 216 aprint_error_dev(self, "unsupported chip ID\n"); 217 return; 218 } 219 220 if (tegra_soctherm_init_clocks(sc) != 0) 221 return; 222 223 tegra_soctherm_init_sensors(sc); 224 } 225 226 static int 227 tegra_soctherm_init_clocks(struct tegra_soctherm_softc *sc) 228 { 229 struct clk *pll_p_out0; 230 struct clk *clk_m; 231 int error; 232 233 pll_p_out0 = clk_get("pll_p_out0"); 234 if (pll_p_out0 == NULL) { 235 aprint_error_dev(sc->sc_dev, "couldn't find pll_p_out0\n"); 236 return ENOENT; 237 } 238 clk_m = clk_get("clk_m"); 239 if (clk_m == NULL) { 240 aprint_error_dev(sc->sc_dev, "couldn't find clk_m\n"); 241 return ENOENT; 242 } 243 244 fdtbus_reset_assert(sc->sc_rst_soctherm); 245 246 error = clk_set_parent(sc->sc_clk_soctherm, pll_p_out0); 247 if (error) { 248 aprint_error_dev(sc->sc_dev, 249 "couldn't set soctherm parent: %d\n", error); 250 return error; 251 } 252 error = clk_set_rate(sc->sc_clk_soctherm, 51000000); 253 if (error) { 254 aprint_error_dev(sc->sc_dev, 255 "couldn't set soctherm rate: %d\n", error); 256 return error; 257 } 258 259 error = clk_set_parent(sc->sc_clk_tsensor, clk_m); 260 if (error) { 261 aprint_error_dev(sc->sc_dev, 262 "couldn't set tsensor parent: %d\n", error); 263 return error; 264 } 265 error = clk_set_rate(sc->sc_clk_tsensor, 400000); 266 if (error) { 267 aprint_error_dev(sc->sc_dev, 268 "couldn't set tsensor rate: %d\n", error); 269 return error; 270 } 271 272 error = clk_enable(sc->sc_clk_tsensor); 273 if (error) { 274 aprint_error_dev(sc->sc_dev, "couldn't enable tsensor: %d\n", 275 error); 276 return error; 277 } 278 279 error = clk_enable(sc->sc_clk_soctherm); 280 if (error) { 281 aprint_error_dev(sc->sc_dev, "couldn't enable soctherm: %d\n", 282 error); 283 return error; 284 } 285 286 fdtbus_reset_deassert(sc->sc_rst_soctherm); 287 288 return 0; 289 } 290 291 static void 292 tegra_soctherm_init_sensors(struct tegra_soctherm_softc *sc) 293 { 294 const struct tegra_soctherm_config *config = sc->sc_config; 295 const u_int nsensors = __arraycount(tegra_soctherm_sensors); 296 const size_t len = sizeof(*sc->sc_sensors) * nsensors; 297 uint32_t val; 298 u_int n; 299 300 val = tegra_fuse_read(FUSE_TSENSOR8_CALIB_REG); 301 sc->sc_base_cp = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_CP_TS_BASE); 302 sc->sc_base_ft = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_FT_TS_BASE); 303 val = tegra_fuse_read(FUSE_SPARE_REALIGNMENT_REG); 304 const int calib_cp = tegra_soctherm_decodeint(val, 305 FUSE_SPARE_REALIGNMENT_CP); 306 const int calib_ft = tegra_soctherm_decodeint(val, 307 FUSE_SPARE_REALIGNMENT_FT); 308 sc->sc_actual_temp_cp = 2 * config->nominal_calib_cp + calib_cp; 309 sc->sc_actual_temp_ft = 2 * config->nominal_calib_ft + calib_ft; 310 311 sc->sc_sme = sysmon_envsys_create(); 312 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 313 sc->sc_sme->sme_cookie = sc; 314 sc->sc_sme->sme_refresh = tegra_soctherm_refresh; 315 316 sc->sc_sensors = kmem_zalloc(len, KM_SLEEP); 317 for (n = 0; n < nsensors; n++) { 318 sc->sc_sensors[n] = tegra_soctherm_sensors[n]; 319 tegra_soctherm_init_sensor(sc, &sc->sc_sensors[n]); 320 } 321 322 SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_PDIV_REG, config->init_pdiv); 323 SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_HOTSPOT_OFF_REG, 324 config->init_hotspot_off); 325 326 sysmon_envsys_register(sc->sc_sme); 327 } 328 329 static void 330 tegra_soctherm_init_sensor(struct tegra_soctherm_softc *sc, 331 struct tegra_soctherm_sensor *s) 332 { 333 const struct tegra_soctherm_config *config = sc->sc_config; 334 int64_t temp_a, temp_b, tmp; 335 uint32_t val; 336 337 val = tegra_fuse_read(s->s_fuse); 338 const int calib_cp = tegra_soctherm_decodeint(val, 339 FUSE_TSENSOR_CALIB_CP_TS_BASE); 340 const int calib_ft = tegra_soctherm_decodeint(val, 341 FUSE_TSENSOR_CALIB_FT_TS_BASE); 342 const int actual_cp = sc->sc_base_cp * 64 + calib_cp; 343 const int actual_ft = sc->sc_base_ft * 32 + calib_ft; 344 345 const int64_t d_sensor = actual_ft - actual_cp; 346 const int64_t d_temp = sc->sc_actual_temp_ft - sc->sc_actual_temp_cp; 347 const int mult = config->pdiv * config->tsample_ate; 348 const int div = config->tsample * config->pdiv_ate; 349 350 temp_a = tegra_soctherm_divide(d_temp * 0x2000 * mult, 351 d_sensor * div); 352 tmp = (int64_t)actual_ft * sc->sc_actual_temp_cp - 353 (int64_t)actual_cp * sc->sc_actual_temp_ft; 354 temp_b = tegra_soctherm_divide(tmp, d_sensor); 355 temp_a = tegra_soctherm_divide( 356 temp_a * s->s_fuse_corr_alpha, 1000000); 357 temp_b = (uint16_t)tegra_soctherm_divide( 358 temp_b * s->s_fuse_corr_alpha + s->s_fuse_corr_beta, 1000000); 359 360 s->s_therm_a = (int16_t)temp_a; 361 s->s_therm_b = (int16_t)temp_b; 362 363 SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET, 364 SOC_THERM_TSENSOR_CONFIG0_STATUS_CLR | 365 SOC_THERM_TSENSOR_CONFIG0_STOP, 0); 366 SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET, 367 __SHIFTIN(config->tall, SOC_THERM_TSENSOR_CONFIG0_TALL) | 368 SOC_THERM_TSENSOR_CONFIG0_STOP); 369 370 SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG1_OFFSET, 371 __SHIFTIN(config->tsample - 1, SOC_THERM_TSENSOR_CONFIG1_TSAMPLE) | 372 __SHIFTIN(config->tiddq_en, SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN) | 373 __SHIFTIN(config->ten_count, SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT) | 374 SOC_THERM_TSENSOR_CONFIG1_TEMP_ENABLE); 375 376 SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG2_OFFSET, 377 __SHIFTIN((uint16_t)s->s_therm_a, 378 SOC_THERM_TSENSOR_CONFIG2_THERM_A) | 379 __SHIFTIN((uint16_t)s->s_therm_b, 380 SOC_THERM_TSENSOR_CONFIG2_THERM_B)); 381 382 SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET, 383 0, SOC_THERM_TSENSOR_CONFIG0_STOP); 384 385 s->s_data.units = ENVSYS_STEMP; 386 s->s_data.state = ENVSYS_SINVALID; 387 sysmon_envsys_sensor_attach(sc->sc_sme, &s->s_data); 388 } 389 390 static void 391 tegra_soctherm_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 392 { 393 struct tegra_soctherm_softc * const sc = sme->sme_cookie; 394 struct tegra_soctherm_sensor *s = (struct tegra_soctherm_sensor *)edata; 395 uint32_t status; 396 397 status = SENSOR_READ(sc, s, SOC_THERM_TSENSOR_STATUS1_OFFSET); 398 if (status & SOC_THERM_TSENSOR_STATUS1_TEMP_VALID) { 399 const u_int temp = __SHIFTOUT(status, 400 SOC_THERM_TSENSOR_STATUS1_TEMP); 401 int64_t val = ((temp >> 8) & 0xff) * 1000000; 402 if (temp & 0x80) 403 val += 500000; 404 if (temp & 0x02) 405 val = -val; 406 edata->value_cur = val + 273150000; 407 edata->state = ENVSYS_SVALID; 408 } else { 409 edata->state = ENVSYS_SINVALID; 410 } 411 } 412 413 static int 414 tegra_soctherm_decodeint(uint32_t val, uint32_t bitmask) 415 { 416 const uint32_t v = __SHIFTOUT(val, bitmask); 417 const int bits = popcount32(bitmask); 418 int ret = v << (32 - bits); 419 return ret >> (32 - bits); 420 } 421 422 static int64_t 423 tegra_soctherm_divide(int64_t num, int64_t denom) 424 { 425 int64_t ret = ((num << 16) * 2 + 1) / (2 * denom); 426 return ret >> 16; 427 } 428
Indexes created Sun Sep 28 16:09:52 GMT 2025