tegra_soctherm.c revision 1.3.6.1
1 /* $NetBSD: tegra_soctherm.c,v 1.3.6.1 2017/04/21 16:53:23 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_soctherm.c,v 1.3.6.1 2017/04/21 16:53:23 bouyer Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 40 #include <dev/sysmon/sysmonvar.h> 41 42 #include <arm/nvidia/tegra_reg.h> 43 #include <arm/nvidia/tegra_socthermreg.h> 44 #include <arm/nvidia/tegra_var.h> 45 46 #include <dev/fdt/fdtvar.h> 47 48 #define FUSE_TSENSOR_CALIB_CP_TS_BASE __BITS(12,0) 49 #define FUSE_TSENSOR_CALIB_FT_TS_BASE __BITS(25,13) 50 51 #define FUSE_TSENSOR8_CALIB_REG 0x180 52 #define FUSE_TSENSOR8_CALIB_CP_TS_BASE __BITS(9,0) 53 #define FUSE_TSENSOR8_CALIB_FT_TS_BASE __BITS(20,10) 54 55 #define FUSE_SPARE_REALIGNMENT_REG 0x1fc 56 #define FUSE_SPARE_REALIGNMENT_CP __BITS(5,0) 57 #define FUSE_SPARE_REALIGNMENT_FT __BITS(25,21) 58 59 static int tegra_soctherm_match(device_t, cfdata_t, void *); 60 static void tegra_soctherm_attach(device_t, device_t, void *); 61 62 struct tegra_soctherm_config { 63 uint32_t init_pdiv; 64 uint32_t init_hotspot_off; 65 uint32_t nominal_calib_ft; 66 uint32_t nominal_calib_cp; 67 uint32_t tall; 68 uint32_t tsample; 69 uint32_t tiddq_en; 70 uint32_t ten_count; 71 uint32_t pdiv; 72 uint32_t tsample_ate; 73 uint32_t pdiv_ate; 74 }; 75 76 static const struct tegra_soctherm_config tegra124_soctherm_config = { 77 .init_pdiv = 0x8888, 78 .init_hotspot_off = 0x60600, 79 .nominal_calib_ft = 105, 80 .nominal_calib_cp = 25, 81 .tall = 16300, 82 .tsample = 120, 83 .tiddq_en = 1, 84 .ten_count = 1, 85 .pdiv = 8, 86 .tsample_ate = 480, 87 .pdiv_ate = 8 88 }; 89 90 struct tegra_soctherm_sensor { 91 envsys_data_t s_data; 92 u_int s_base; 93 u_int s_fuse; 94 int s_fuse_corr_alpha; 95 int s_fuse_corr_beta; 96 int16_t s_therm_a; 97 int16_t s_therm_b; 98 }; 99 100 static const struct tegra_soctherm_sensor tegra_soctherm_sensors[] = { 101 { .s_data = { .desc = "CPU0" }, .s_base = 0x0c0, .s_fuse = 0x098, 102 .s_fuse_corr_alpha = 1135400, .s_fuse_corr_beta = -6266900 }, 103 { .s_data = { .desc = "CPU1" }, .s_base = 0x0e0, .s_fuse = 0x084, 104 .s_fuse_corr_alpha = 1122220, .s_fuse_corr_beta = -5700700 }, 105 { .s_data = { .desc = "CPU2" }, .s_base = 0x100, .s_fuse = 0x088, 106 .s_fuse_corr_alpha = 1127000, .s_fuse_corr_beta = -6768200 }, 107 { .s_data = { .desc = "CPU3" }, .s_base = 0x120, .s_fuse = 0x12c, 108 .s_fuse_corr_alpha = 1110900, .s_fuse_corr_beta = -6232000 }, 109 { .s_data = { .desc = "MEM0" }, .s_base = 0x140, .s_fuse = 0x158, 110 .s_fuse_corr_alpha = 1122300, .s_fuse_corr_beta = -5936400 }, 111 { .s_data = { .desc = "MEM1" }, .s_base = 0x160, .s_fuse = 0x15c, 112 .s_fuse_corr_alpha = 1145700, .s_fuse_corr_beta = -7124600 }, 113 { .s_data = { .desc = "GPU" }, .s_base = 0x180, .s_fuse = 0x154, 114 .s_fuse_corr_alpha = 1120100, .s_fuse_corr_beta = -6000500 }, 115 { .s_data = { .desc = "PLLX" }, .s_base = 0x1a0, .s_fuse = 0x160, 116 .s_fuse_corr_alpha = 1106500, .s_fuse_corr_beta = -6729300 }, 117 }; 118 119 struct tegra_soctherm_softc { 120 device_t sc_dev; 121 bus_space_tag_t sc_bst; 122 bus_space_handle_t sc_bsh; 123 struct clk *sc_clk_tsensor; 124 struct clk *sc_clk_soctherm; 125 struct fdtbus_reset *sc_rst_soctherm; 126 127 struct sysmon_envsys *sc_sme; 128 struct tegra_soctherm_sensor *sc_sensors; 129 const struct tegra_soctherm_config *sc_config; 130 131 uint32_t sc_base_cp; 132 uint32_t sc_base_ft; 133 int32_t sc_actual_temp_cp; 134 int32_t sc_actual_temp_ft; 135 }; 136 137 static int tegra_soctherm_init_clocks(struct tegra_soctherm_softc *); 138 static void tegra_soctherm_init_sensors(device_t); 139 static void tegra_soctherm_init_sensor(struct tegra_soctherm_softc *, 140 struct tegra_soctherm_sensor *); 141 static void tegra_soctherm_refresh(struct sysmon_envsys *, envsys_data_t *); 142 static int tegra_soctherm_decodeint(uint32_t, uint32_t); 143 static int64_t tegra_soctherm_divide(int64_t, int64_t); 144 145 CFATTACH_DECL_NEW(tegra_soctherm, sizeof(struct tegra_soctherm_softc), 146 tegra_soctherm_match, tegra_soctherm_attach, NULL, NULL); 147 148 #define SOCTHERM_READ(sc, reg) \ 149 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 150 #define SOCTHERM_WRITE(sc, reg, val) \ 151 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 152 #define SOCTHERM_SET_CLEAR(sc, reg, set, clr) \ 153 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (reg), (set), (clr)) 154 155 #define SENSOR_READ(sc, s, reg) \ 156 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg)) 157 #define SENSOR_WRITE(sc, s, reg, val) \ 158 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (val)) 159 #define SENSOR_SET_CLEAR(sc, s, reg, set, clr) \ 160 tegra_reg_set_clear((sc)->sc_bst, (sc)->sc_bsh, (s)->s_base + (reg), (set), (clr)) 161 162 static int 163 tegra_soctherm_match(device_t parent, cfdata_t cf, void *aux) 164 { 165 const char * const compatible[] = { "nvidia,tegra124-soctherm", NULL }; 166 struct fdt_attach_args * const faa = aux; 167 168 return of_match_compatible(faa->faa_phandle, compatible); 169 } 170 171 static void 172 tegra_soctherm_attach(device_t parent, device_t self, void *aux) 173 { 174 struct tegra_soctherm_softc * const sc = device_private(self); 175 struct fdt_attach_args * const faa = aux; 176 bus_addr_t addr; 177 bus_size_t size; 178 int error; 179 180 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) { 181 aprint_error(": couldn't get registers\n"); 182 return; 183 } 184 sc->sc_clk_tsensor = fdtbus_clock_get(faa->faa_phandle, "tsensor"); 185 if (sc->sc_clk_tsensor == NULL) { 186 aprint_error(": couldn't get clock tsensor\n"); 187 return; 188 } 189 sc->sc_clk_soctherm = fdtbus_clock_get(faa->faa_phandle, "soctherm"); 190 if (sc->sc_clk_soctherm == NULL) { 191 aprint_error(": couldn't get clock soctherm\n"); 192 return; 193 } 194 sc->sc_rst_soctherm = fdtbus_reset_get(faa->faa_phandle, "soctherm"); 195 if (sc->sc_rst_soctherm == NULL) { 196 aprint_error(": couldn't get reset soctherm\n"); 197 return; 198 } 199 200 sc->sc_dev = self; 201 sc->sc_bst = faa->faa_bst; 202 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 203 if (error) { 204 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 205 return; 206 } 207 208 aprint_naive("\n"); 209 aprint_normal(": SOC_THERM\n"); 210 211 if (tegra_chip_id() == CHIP_ID_TEGRA124) { 212 sc->sc_config = &tegra124_soctherm_config; 213 } 214 215 if (sc->sc_config == NULL) { 216 aprint_error_dev(self, "unsupported chip ID\n"); 217 return; 218 } 219 220 if (tegra_soctherm_init_clocks(sc) != 0) 221 return; 222 223 config_defer(self, tegra_soctherm_init_sensors); 224 } 225 226 static int 227 tegra_soctherm_init_clocks(struct tegra_soctherm_softc *sc) 228 { 229 int error; 230 231 fdtbus_reset_assert(sc->sc_rst_soctherm); 232 233 error = clk_set_rate(sc->sc_clk_soctherm, 51000000); 234 if (error) { 235 aprint_error_dev(sc->sc_dev, 236 "couldn't set soctherm rate: %d\n", error); 237 return error; 238 } 239 240 error = clk_set_rate(sc->sc_clk_tsensor, 400000); 241 if (error) { 242 aprint_error_dev(sc->sc_dev, 243 "couldn't set tsensor rate: %d\n", error); 244 return error; 245 } 246 247 error = clk_enable(sc->sc_clk_tsensor); 248 if (error) { 249 aprint_error_dev(sc->sc_dev, "couldn't enable tsensor: %d\n", 250 error); 251 return error; 252 } 253 254 error = clk_enable(sc->sc_clk_soctherm); 255 if (error) { 256 aprint_error_dev(sc->sc_dev, "couldn't enable soctherm: %d\n", 257 error); 258 return error; 259 } 260 261 fdtbus_reset_deassert(sc->sc_rst_soctherm); 262 263 return 0; 264 } 265 266 static void 267 tegra_soctherm_init_sensors(device_t dev) 268 { 269 struct tegra_soctherm_softc * const sc = device_private(dev); 270 const struct tegra_soctherm_config *config = sc->sc_config; 271 const u_int nsensors = __arraycount(tegra_soctherm_sensors); 272 const size_t len = sizeof(*sc->sc_sensors) * nsensors; 273 uint32_t val; 274 u_int n; 275 276 val = tegra_fuse_read(FUSE_TSENSOR8_CALIB_REG); 277 sc->sc_base_cp = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_CP_TS_BASE); 278 sc->sc_base_ft = __SHIFTOUT(val, FUSE_TSENSOR8_CALIB_FT_TS_BASE); 279 val = tegra_fuse_read(FUSE_SPARE_REALIGNMENT_REG); 280 const int calib_cp = tegra_soctherm_decodeint(val, 281 FUSE_SPARE_REALIGNMENT_CP); 282 const int calib_ft = tegra_soctherm_decodeint(val, 283 FUSE_SPARE_REALIGNMENT_FT); 284 sc->sc_actual_temp_cp = 2 * config->nominal_calib_cp + calib_cp; 285 sc->sc_actual_temp_ft = 2 * config->nominal_calib_ft + calib_ft; 286 287 sc->sc_sme = sysmon_envsys_create(); 288 sc->sc_sme->sme_name = device_xname(sc->sc_dev); 289 sc->sc_sme->sme_cookie = sc; 290 sc->sc_sme->sme_refresh = tegra_soctherm_refresh; 291 292 sc->sc_sensors = kmem_zalloc(len, KM_SLEEP); 293 for (n = 0; n < nsensors; n++) { 294 sc->sc_sensors[n] = tegra_soctherm_sensors[n]; 295 tegra_soctherm_init_sensor(sc, &sc->sc_sensors[n]); 296 } 297 298 SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_PDIV_REG, config->init_pdiv); 299 SOCTHERM_WRITE(sc, SOC_THERM_TSENSOR_HOTSPOT_OFF_REG, 300 config->init_hotspot_off); 301 302 sysmon_envsys_register(sc->sc_sme); 303 } 304 305 static void 306 tegra_soctherm_init_sensor(struct tegra_soctherm_softc *sc, 307 struct tegra_soctherm_sensor *s) 308 { 309 const struct tegra_soctherm_config *config = sc->sc_config; 310 int64_t temp_a, temp_b, tmp; 311 uint32_t val; 312 313 val = tegra_fuse_read(s->s_fuse); 314 const int calib_cp = tegra_soctherm_decodeint(val, 315 FUSE_TSENSOR_CALIB_CP_TS_BASE); 316 const int calib_ft = tegra_soctherm_decodeint(val, 317 FUSE_TSENSOR_CALIB_FT_TS_BASE); 318 const int actual_cp = sc->sc_base_cp * 64 + calib_cp; 319 const int actual_ft = sc->sc_base_ft * 32 + calib_ft; 320 321 const int64_t d_sensor = actual_ft - actual_cp; 322 const int64_t d_temp = sc->sc_actual_temp_ft - sc->sc_actual_temp_cp; 323 const int mult = config->pdiv * config->tsample_ate; 324 const int div = config->tsample * config->pdiv_ate; 325 326 temp_a = tegra_soctherm_divide(d_temp * 0x2000 * mult, 327 d_sensor * div); 328 tmp = (int64_t)actual_ft * sc->sc_actual_temp_cp - 329 (int64_t)actual_cp * sc->sc_actual_temp_ft; 330 temp_b = tegra_soctherm_divide(tmp, d_sensor); 331 temp_a = tegra_soctherm_divide( 332 temp_a * s->s_fuse_corr_alpha, 1000000); 333 temp_b = (uint16_t)tegra_soctherm_divide( 334 temp_b * s->s_fuse_corr_alpha + s->s_fuse_corr_beta, 1000000); 335 336 s->s_therm_a = (int16_t)temp_a; 337 s->s_therm_b = (int16_t)temp_b; 338 339 SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET, 340 SOC_THERM_TSENSOR_CONFIG0_STATUS_CLR | 341 SOC_THERM_TSENSOR_CONFIG0_STOP, 0); 342 SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET, 343 __SHIFTIN(config->tall, SOC_THERM_TSENSOR_CONFIG0_TALL) | 344 SOC_THERM_TSENSOR_CONFIG0_STOP); 345 346 SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG1_OFFSET, 347 __SHIFTIN(config->tsample - 1, SOC_THERM_TSENSOR_CONFIG1_TSAMPLE) | 348 __SHIFTIN(config->tiddq_en, SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN) | 349 __SHIFTIN(config->ten_count, SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT) | 350 SOC_THERM_TSENSOR_CONFIG1_TEMP_ENABLE); 351 352 SENSOR_WRITE(sc, s, SOC_THERM_TSENSOR_CONFIG2_OFFSET, 353 __SHIFTIN((uint16_t)s->s_therm_a, 354 SOC_THERM_TSENSOR_CONFIG2_THERM_A) | 355 __SHIFTIN((uint16_t)s->s_therm_b, 356 SOC_THERM_TSENSOR_CONFIG2_THERM_B)); 357 358 SENSOR_SET_CLEAR(sc, s, SOC_THERM_TSENSOR_CONFIG0_OFFSET, 359 0, SOC_THERM_TSENSOR_CONFIG0_STOP); 360 361 s->s_data.units = ENVSYS_STEMP; 362 s->s_data.state = ENVSYS_SINVALID; 363 sysmon_envsys_sensor_attach(sc->sc_sme, &s->s_data); 364 } 365 366 static void 367 tegra_soctherm_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 368 { 369 struct tegra_soctherm_softc * const sc = sme->sme_cookie; 370 struct tegra_soctherm_sensor *s = (struct tegra_soctherm_sensor *)edata; 371 uint32_t status; 372 373 status = SENSOR_READ(sc, s, SOC_THERM_TSENSOR_STATUS1_OFFSET); 374 if (status & SOC_THERM_TSENSOR_STATUS1_TEMP_VALID) { 375 const u_int temp = __SHIFTOUT(status, 376 SOC_THERM_TSENSOR_STATUS1_TEMP); 377 int64_t val = ((temp >> 8) & 0xff) * 1000000; 378 if (temp & 0x80) 379 val += 500000; 380 if (temp & 0x02) 381 val = -val; 382 edata->value_cur = val + 273150000; 383 edata->state = ENVSYS_SVALID; 384 } else { 385 edata->state = ENVSYS_SINVALID; 386 } 387 } 388 389 static int 390 tegra_soctherm_decodeint(uint32_t val, uint32_t bitmask) 391 { 392 const uint32_t v = __SHIFTOUT(val, bitmask); 393 const int bits = popcount32(bitmask); 394 int ret = v << (32 - bits); 395 return ret >> (32 - bits); 396 } 397 398 static int64_t 399 tegra_soctherm_divide(int64_t num, int64_t denom) 400 { 401 int64_t ret = ((num << 16) * 2 + 1) / (2 * denom); 402 return ret >> 16; 403 } 404
Indexes created Tue Oct 21 16:10:11 GMT 2025