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      1 /* $NetBSD: tegra_socthermreg.h,v 1.1 2015/11/21 22:55:32 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_TEGRA_SOCTHERMREG_H
     30 #define _ARM_TEGRA_SOCTHERMREG_H
     31 
     32 #define SOC_THERM_TSENSOR_PDIV_REG		0x1c0
     33 #define SOC_THERM_TSENSOR_HOTSPOT_OFF_REG	0x1c4
     34 #define SOC_THERM_TSENSOR_TEMP1_REG		0x1c8
     35 #define SOC_THERM_TSENSOR_TEMP2_REG		0x1cc
     36 
     37 #define SOC_THERM_TSENSOR_CONFIG0_OFFSET	0x00
     38 #define SOC_THERM_TSENSOR_CONFIG0_TALL		__BITS(27,8)
     39 #define SOC_THERM_TSENSOR_CONFIG0_STATUS_CLR	__BIT(5)
     40 #define SOC_THERM_TSENSOR_CONFIG0_TCALC_OVERFLOW __BIT(4)
     41 #define SOC_THERM_TSENSOR_CONFIG0_OVERFLOW	__BIT(3)
     42 #define SOC_THERM_TSENSOR_CONFIG0_CPTR_OVERFLOW	__BIT(2)
     43 #define SOC_THERM_TSENSOR_CONFIG0_RO_SEL	__BIT(1)
     44 #define SOC_THERM_TSENSOR_CONFIG0_STOP		__BIT(0)
     45 
     46 #define SOC_THERM_TSENSOR_CONFIG1_OFFSET	0x04
     47 #define SOC_THERM_TSENSOR_CONFIG1_TEMP_ENABLE	__BIT(31)
     48 #define SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT	__BITS(29,24)
     49 #define SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN	__BITS(20,15)
     50 #define SOC_THERM_TSENSOR_CONFIG1_TSAMPLE	__BITS(9,0)
     51 
     52 #define SOC_THERM_TSENSOR_CONFIG2_OFFSET	0x08
     53 #define SOC_THERM_TSENSOR_CONFIG2_THERM_A	__BITS(31,16)
     54 #define SOC_THERM_TSENSOR_CONFIG2_THERM_B	__BITS(15,0)
     55 
     56 #define SOC_THERM_TSENSOR_STATUS0_OFFSET	0x0c
     57 #define SOC_THERM_TSENSOR_STATUS0_CAPTURE_VALID	__BIT(31)
     58 #define SOC_THERM_TSENSOR_STATUS0_CAPTURE	__BITS(15,0)
     59 
     60 #define SOC_THERM_TSENSOR_STATUS1_OFFSET	0x10
     61 #define SOC_THERM_TSENSOR_STATUS1_TEMP_VALID	__BIT(31)
     62 #define SOC_THERM_TSENSOR_STATUS1_TEMP		__BITS(15,0)
     63 
     64 #define SOC_THERM_TSENSOR_STATUS2_OFFSET	0x14
     65 #define SOC_THERM_TSENSOR_STATUS2_TEMP_MAX	__BITS(31,16)
     66 #define SOC_THERM_TSENSOR_STATUS2_TEMP_MIN	__BITS(15,0)
     67 
     68 #endif /* _ARM_TEGRA_SOCTHERMREG_H */
     69