tegra_socthermreg.h revision 1.1.2.2
1 1.1.2.2 skrll /* $NetBSD: tegra_socthermreg.h,v 1.1.2.2 2015/12/27 12:09:31 skrll Exp $ */ 2 1.1.2.2 skrll 3 1.1.2.2 skrll /*- 4 1.1.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 1.1.2.2 skrll * All rights reserved. 6 1.1.2.2 skrll * 7 1.1.2.2 skrll * Redistribution and use in source and binary forms, with or without 8 1.1.2.2 skrll * modification, are permitted provided that the following conditions 9 1.1.2.2 skrll * are met: 10 1.1.2.2 skrll * 1. Redistributions of source code must retain the above copyright 11 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer. 12 1.1.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright 13 1.1.2.2 skrll * notice, this list of conditions and the following disclaimer in the 14 1.1.2.2 skrll * documentation and/or other materials provided with the distribution. 15 1.1.2.2 skrll * 16 1.1.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 1.1.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 1.1.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 1.1.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 1.1.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 1.1.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 1.1.2.2 skrll * SUCH DAMAGE. 27 1.1.2.2 skrll */ 28 1.1.2.2 skrll 29 1.1.2.2 skrll #ifndef _ARM_TEGRA_SOCTHERMREG_H 30 1.1.2.2 skrll #define _ARM_TEGRA_SOCTHERMREG_H 31 1.1.2.2 skrll 32 1.1.2.2 skrll #define SOC_THERM_TSENSOR_PDIV_REG 0x1c0 33 1.1.2.2 skrll #define SOC_THERM_TSENSOR_HOTSPOT_OFF_REG 0x1c4 34 1.1.2.2 skrll #define SOC_THERM_TSENSOR_TEMP1_REG 0x1c8 35 1.1.2.2 skrll #define SOC_THERM_TSENSOR_TEMP2_REG 0x1cc 36 1.1.2.2 skrll 37 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG0_OFFSET 0x00 38 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG0_TALL __BITS(27,8) 39 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG0_STATUS_CLR __BIT(5) 40 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG0_TCALC_OVERFLOW __BIT(4) 41 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG0_OVERFLOW __BIT(3) 42 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG0_CPTR_OVERFLOW __BIT(2) 43 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG0_RO_SEL __BIT(1) 44 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG0_STOP __BIT(0) 45 1.1.2.2 skrll 46 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG1_OFFSET 0x04 47 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG1_TEMP_ENABLE __BIT(31) 48 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG1_TEN_COUNT __BITS(29,24) 49 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG1_TIDDQ_EN __BITS(20,15) 50 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG1_TSAMPLE __BITS(9,0) 51 1.1.2.2 skrll 52 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG2_OFFSET 0x08 53 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG2_THERM_A __BITS(31,16) 54 1.1.2.2 skrll #define SOC_THERM_TSENSOR_CONFIG2_THERM_B __BITS(15,0) 55 1.1.2.2 skrll 56 1.1.2.2 skrll #define SOC_THERM_TSENSOR_STATUS0_OFFSET 0x0c 57 1.1.2.2 skrll #define SOC_THERM_TSENSOR_STATUS0_CAPTURE_VALID __BIT(31) 58 1.1.2.2 skrll #define SOC_THERM_TSENSOR_STATUS0_CAPTURE __BITS(15,0) 59 1.1.2.2 skrll 60 1.1.2.2 skrll #define SOC_THERM_TSENSOR_STATUS1_OFFSET 0x10 61 1.1.2.2 skrll #define SOC_THERM_TSENSOR_STATUS1_TEMP_VALID __BIT(31) 62 1.1.2.2 skrll #define SOC_THERM_TSENSOR_STATUS1_TEMP __BITS(15,0) 63 1.1.2.2 skrll 64 1.1.2.2 skrll #define SOC_THERM_TSENSOR_STATUS2_OFFSET 0x14 65 1.1.2.2 skrll #define SOC_THERM_TSENSOR_STATUS2_TEMP_MAX __BITS(31,16) 66 1.1.2.2 skrll #define SOC_THERM_TSENSOR_STATUS2_TEMP_MIN __BITS(15,0) 67 1.1.2.2 skrll 68 1.1.2.2 skrll #endif /* _ARM_TEGRA_SOCTHERMREG_H */ 69
Indexes created Sun Oct 26 21:10:03 GMT 2025