1 /* $NetBSD: tegra_usbphy.c,v 1.11 2021/01/27 03:10:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_usbphy.c,v 1.11 2021/01/27 03:10:19 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/atomic.h> 39 40 #include <arm/nvidia/tegra_reg.h> 41 #include <arm/nvidia/tegra_var.h> 42 #include <arm/nvidia/tegra_usbreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 static int tegra_usbphy_match(device_t, cfdata_t, void *); 47 static void tegra_usbphy_attach(device_t, device_t, void *); 48 49 struct tegra_usbphy_softc { 50 device_t sc_dev; 51 bus_space_tag_t sc_bst; 52 bus_space_handle_t sc_bsh; 53 int sc_phandle; 54 struct clk *sc_clk_reg; 55 struct clk *sc_clk_pll; 56 struct clk *sc_clk_utmip; 57 struct fdtbus_reset *sc_rst_usb; 58 struct fdtbus_reset *sc_rst_utmip; 59 60 struct tegra_gpio_pin *sc_pin_vbus; 61 uint32_t sc_hssync_start_delay; 62 uint32_t sc_idle_wait_delay; 63 uint32_t sc_elastic_limit; 64 uint32_t sc_term_range_adj; 65 uint32_t sc_xcvr_setup; 66 uint32_t sc_xcvr_lsfslew; 67 uint32_t sc_xcvr_lsrslew; 68 uint32_t sc_hssquelch_level; 69 uint32_t sc_hsdiscon_level; 70 uint32_t sc_xcvr_hsslew; 71 }; 72 73 static int tegra_usbphy_parse_properties(struct tegra_usbphy_softc *); 74 static void tegra_usbphy_utmip_init(struct tegra_usbphy_softc *); 75 76 CFATTACH_DECL_NEW(tegra_usbphy, sizeof(struct tegra_usbphy_softc), 77 tegra_usbphy_match, tegra_usbphy_attach, NULL, NULL); 78 79 static const struct device_compatible_entry compat_data[] = { 80 { .compat = "nvidia,tegra210-usb-phy" }, 81 { .compat = "nvidia,tegra124-usb-phy" }, 82 { .compat = "nvidia,tegra30-usb-phy" }, 83 DEVICE_COMPAT_EOL 84 }; 85 86 static int 87 tegra_usbphy_match(device_t parent, cfdata_t cf, void *aux) 88 { 89 struct fdt_attach_args * const faa = aux; 90 91 return of_compatible_match(faa->faa_phandle, compat_data); 92 } 93 94 static void 95 tegra_usbphy_attach(device_t parent, device_t self, void *aux) 96 { 97 struct tegra_usbphy_softc * const sc = device_private(self); 98 struct fdt_attach_args * const faa = aux; 99 struct fdtbus_regulator *reg; 100 const int phandle = faa->faa_phandle; 101 bus_addr_t addr; 102 bus_size_t size; 103 int error; 104 105 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 106 aprint_error(": couldn't get registers\n"); 107 return; 108 } 109 sc->sc_clk_reg = fdtbus_clock_get(phandle, "reg"); 110 if (sc->sc_clk_reg == NULL) { 111 aprint_error(": couldn't get clock reg\n"); 112 return; 113 } 114 sc->sc_clk_pll = fdtbus_clock_get(phandle, "pll_u"); 115 if (sc->sc_clk_pll == NULL) { 116 aprint_error(": couldn't get clock pll_u\n"); 117 return; 118 } 119 sc->sc_clk_utmip = fdtbus_clock_get(phandle, "utmi-pads"); 120 if (sc->sc_clk_utmip == NULL) { 121 aprint_error(": couldn't get clock utmi-pads\n"); 122 return; 123 } 124 sc->sc_rst_usb = fdtbus_reset_get(phandle, "usb"); 125 if (sc->sc_rst_usb == NULL) { 126 aprint_error(": couldn't get reset usb\n"); 127 return; 128 } 129 sc->sc_rst_utmip = fdtbus_reset_get(phandle, "utmi-pads"); 130 if (sc->sc_rst_utmip == NULL) { 131 aprint_error(": couldn't get reset utmi-pads\n"); 132 return; 133 } 134 135 sc->sc_dev = self; 136 sc->sc_phandle = phandle; 137 sc->sc_bst = faa->faa_bst; 138 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 139 if (error) { 140 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr, error); 141 return; 142 } 143 144 aprint_naive("\n"); 145 aprint_normal(": USB PHY\n"); 146 147 if (tegra_usbphy_parse_properties(sc) != 0) 148 return; 149 150 fdtbus_reset_assert(sc->sc_rst_usb); 151 error = clk_enable(sc->sc_clk_reg); 152 if (error) { 153 aprint_error_dev(self, "couldn't enable clock reg: %d\n", 154 error); 155 return; 156 } 157 fdtbus_reset_deassert(sc->sc_rst_usb); 158 159 tegra_usbphy_utmip_init(sc); 160 161 reg = fdtbus_regulator_acquire(phandle, "vbus-supply"); 162 if (reg) { 163 const uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 164 TEGRA_EHCI_PHY_VBUS_SENSORS_REG); 165 if ((v & TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS) == 0) { 166 fdtbus_regulator_enable(reg); 167 } else { 168 aprint_normal_dev(self, "VBUS input active\n"); 169 } 170 } 171 } 172 173 static int 174 tegra_usbphy_parse_properties(struct tegra_usbphy_softc *sc) 175 { 176 #define PROPGET(k, v) \ 177 if (of_getprop_uint32(sc->sc_phandle, (k), (v))) { \ 178 aprint_error_dev(sc->sc_dev, \ 179 "missing property '%s'\n", (k)); \ 180 return EIO; \ 181 } 182 183 PROPGET("nvidia,hssync-start-delay", &sc->sc_hssync_start_delay); 184 PROPGET("nvidia,idle-wait-delay", &sc->sc_idle_wait_delay); 185 PROPGET("nvidia,elastic-limit", &sc->sc_elastic_limit); 186 PROPGET("nvidia,term-range-adj", &sc->sc_term_range_adj); 187 PROPGET("nvidia,xcvr-setup", &sc->sc_xcvr_setup); 188 PROPGET("nvidia,xcvr-lsfslew", &sc->sc_xcvr_lsfslew); 189 PROPGET("nvidia,xcvr-lsrslew", &sc->sc_xcvr_lsrslew); 190 PROPGET("nvidia,hssquelch-level", &sc->sc_hssquelch_level); 191 PROPGET("nvidia,hsdiscon-level", &sc->sc_hsdiscon_level); 192 PROPGET("nvidia,xcvr-hsslew", &sc->sc_xcvr_hsslew); 193 194 return 0; 195 #undef PROPGET 196 } 197 198 static void 199 tegra_usbphy_utmip_init(struct tegra_usbphy_softc *sc) 200 { 201 bus_space_tag_t bst = sc->sc_bst; 202 bus_space_handle_t bsh = sc->sc_bsh; 203 int retry; 204 205 /* Put UTMIP PHY into reset before programming UTMIP config registers */ 206 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 207 TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET, 0); 208 209 /* Enable UTMIP PHY mode */ 210 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 211 TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB, 0); 212 213 /* Stop crystal clock */ 214 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG, 215 0, TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN); 216 delay(1); 217 218 /* Clear session status */ 219 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_PHY_VBUS_SENSORS_REG, 220 0, 221 TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE | 222 TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN); 223 224 /* Transceiver configuration */ 225 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 226 __SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) | 227 __SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) | 228 __SHIFTIN(sc->sc_xcvr_hsslew, 229 TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB), 230 TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP | 231 TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB | 232 TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB); 233 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG, 234 __SHIFTIN(sc->sc_term_range_adj, 235 TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ), 236 TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ); 237 238 if (of_getprop_bool(sc->sc_phandle, "nvidia,has-utmi-pad-registers")) { 239 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG, 240 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB | 241 __SHIFTIN(sc->sc_hsdiscon_level, 242 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL), 243 TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD | 244 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL); 245 delay(25); 246 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG, 247 0, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN); 248 } 249 250 /* Misc config */ 251 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG0_REG, 252 0, 253 TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE); 254 255 /* BIAS cell power down lag */ 256 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG, 257 __SHIFTIN(5, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT), 258 TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT); 259 260 /* Debounce config */ 261 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG, 262 __SHIFTIN(0x7530, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A), 263 TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A); 264 265 /* Transmit signal preamble config */ 266 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_TX_CFG0_REG, 267 TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J, 0); 268 269 /* Power-down battery charger circuit */ 270 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG, 271 TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG, 0); 272 273 /* Select low speed bias method */ 274 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 275 0, TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL); 276 277 /* High speed receive config */ 278 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG0_REG, 279 __SHIFTIN(sc->sc_idle_wait_delay, 280 TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) | 281 __SHIFTIN(sc->sc_elastic_limit, 282 TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT), 283 TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT | 284 TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT); 285 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG, 286 __SHIFTIN(sc->sc_hssync_start_delay, 287 TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY), 288 TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY); 289 290 /* Start crystal clock */ 291 delay(1); 292 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG, 293 TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN, 0); 294 295 /* Bring UTMIP PHY out of reset */ 296 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 297 0, TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET); 298 for (retry = 100000; retry > 0; retry--) { 299 const uint32_t susp = bus_space_read_4(bst, bsh, 300 TEGRA_EHCI_SUSP_CTRL_REG); 301 if (susp & TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID) 302 break; 303 delay(1); 304 } 305 if (retry == 0) { 306 aprint_error_dev(sc->sc_dev, "PHY clock is not valid\n"); 307 return; 308 } 309 310 /* Disable ICUSB transceiver */ 311 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_ICUSB_CTRL_REG, 312 0, 313 TEGRA_EHCI_ICUSB_CTRL_ENB1); 314 315 /* Power up UTMPI transceiver */ 316 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 317 0, 318 TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN | 319 TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN | 320 TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN); 321 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG, 322 0, 323 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN | 324 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN | 325 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN); 326 } 327
Indexes created Sat Sep 20 22:09:52 GMT 2025