tegra_usbphy.c revision 1.5.2.2 1 1.5.2.2 skrll /* $NetBSD: tegra_usbphy.c,v 1.5.2.2 2015/12/27 12:09:31 skrll Exp $ */
2 1.5.2.2 skrll
3 1.5.2.2 skrll /*-
4 1.5.2.2 skrll * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
5 1.5.2.2 skrll * All rights reserved.
6 1.5.2.2 skrll *
7 1.5.2.2 skrll * Redistribution and use in source and binary forms, with or without
8 1.5.2.2 skrll * modification, are permitted provided that the following conditions
9 1.5.2.2 skrll * are met:
10 1.5.2.2 skrll * 1. Redistributions of source code must retain the above copyright
11 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer.
12 1.5.2.2 skrll * 2. Redistributions in binary form must reproduce the above copyright
13 1.5.2.2 skrll * notice, this list of conditions and the following disclaimer in the
14 1.5.2.2 skrll * documentation and/or other materials provided with the distribution.
15 1.5.2.2 skrll *
16 1.5.2.2 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 1.5.2.2 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 1.5.2.2 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 1.5.2.2 skrll * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 1.5.2.2 skrll * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 1.5.2.2 skrll * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 1.5.2.2 skrll * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 1.5.2.2 skrll * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 1.5.2.2 skrll * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 1.5.2.2 skrll * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 1.5.2.2 skrll * SUCH DAMAGE.
27 1.5.2.2 skrll */
28 1.5.2.2 skrll
29 1.5.2.2 skrll #include <sys/cdefs.h>
30 1.5.2.2 skrll __KERNEL_RCSID(0, "$NetBSD: tegra_usbphy.c,v 1.5.2.2 2015/12/27 12:09:31 skrll Exp $");
31 1.5.2.2 skrll
32 1.5.2.2 skrll #include <sys/param.h>
33 1.5.2.2 skrll #include <sys/bus.h>
34 1.5.2.2 skrll #include <sys/device.h>
35 1.5.2.2 skrll #include <sys/intr.h>
36 1.5.2.2 skrll #include <sys/systm.h>
37 1.5.2.2 skrll #include <sys/kernel.h>
38 1.5.2.2 skrll #include <sys/atomic.h>
39 1.5.2.2 skrll
40 1.5.2.2 skrll #include <arm/nvidia/tegra_reg.h>
41 1.5.2.2 skrll #include <arm/nvidia/tegra_var.h>
42 1.5.2.2 skrll #include <arm/nvidia/tegra_usbreg.h>
43 1.5.2.2 skrll
44 1.5.2.2 skrll #include <dev/fdt/fdtvar.h>
45 1.5.2.2 skrll
46 1.5.2.2 skrll static int tegra_usbphy_match(device_t, cfdata_t, void *);
47 1.5.2.2 skrll static void tegra_usbphy_attach(device_t, device_t, void *);
48 1.5.2.2 skrll
49 1.5.2.2 skrll struct tegra_usbphy_softc {
50 1.5.2.2 skrll device_t sc_dev;
51 1.5.2.2 skrll bus_space_tag_t sc_bst;
52 1.5.2.2 skrll bus_space_handle_t sc_bsh;
53 1.5.2.2 skrll int sc_phandle;
54 1.5.2.2 skrll struct clk *sc_clk_reg;
55 1.5.2.2 skrll struct clk *sc_clk_pll;
56 1.5.2.2 skrll struct clk *sc_clk_utmip;
57 1.5.2.2 skrll struct fdtbus_reset *sc_rst_usb;
58 1.5.2.2 skrll struct fdtbus_reset *sc_rst_utmip;
59 1.5.2.2 skrll
60 1.5.2.2 skrll struct tegra_gpio_pin *sc_pin_vbus;
61 1.5.2.2 skrll uint32_t sc_hssync_start_delay;
62 1.5.2.2 skrll uint32_t sc_idle_wait_delay;
63 1.5.2.2 skrll uint32_t sc_elastic_limit;
64 1.5.2.2 skrll uint32_t sc_term_range_adj;
65 1.5.2.2 skrll uint32_t sc_xcvr_setup;
66 1.5.2.2 skrll uint32_t sc_xcvr_lsfslew;
67 1.5.2.2 skrll uint32_t sc_xcvr_lsrslew;
68 1.5.2.2 skrll uint32_t sc_hssquelch_level;
69 1.5.2.2 skrll uint32_t sc_hsdiscon_level;
70 1.5.2.2 skrll uint32_t sc_xcvr_hsslew;
71 1.5.2.2 skrll };
72 1.5.2.2 skrll
73 1.5.2.2 skrll static int tegra_usbphy_parse_properties(struct tegra_usbphy_softc *);
74 1.5.2.2 skrll static void tegra_usbphy_utmip_init(struct tegra_usbphy_softc *);
75 1.5.2.2 skrll
76 1.5.2.2 skrll CFATTACH_DECL_NEW(tegra_usbphy, sizeof(struct tegra_usbphy_softc),
77 1.5.2.2 skrll tegra_usbphy_match, tegra_usbphy_attach, NULL, NULL);
78 1.5.2.2 skrll
79 1.5.2.2 skrll static int
80 1.5.2.2 skrll tegra_usbphy_match(device_t parent, cfdata_t cf, void *aux)
81 1.5.2.2 skrll {
82 1.5.2.2 skrll const char * const compatible[] = { "nvidia,tegra124-usb-phy", NULL };
83 1.5.2.2 skrll struct fdt_attach_args * const faa = aux;
84 1.5.2.2 skrll
85 1.5.2.2 skrll return of_match_compatible(faa->faa_phandle, compatible);
86 1.5.2.2 skrll }
87 1.5.2.2 skrll
88 1.5.2.2 skrll static void
89 1.5.2.2 skrll tegra_usbphy_attach(device_t parent, device_t self, void *aux)
90 1.5.2.2 skrll {
91 1.5.2.2 skrll struct tegra_usbphy_softc * const sc = device_private(self);
92 1.5.2.2 skrll struct fdt_attach_args * const faa = aux;
93 1.5.2.2 skrll struct fdtbus_regulator *reg;
94 1.5.2.2 skrll const int phandle = faa->faa_phandle;
95 1.5.2.2 skrll bus_addr_t addr;
96 1.5.2.2 skrll bus_size_t size;
97 1.5.2.2 skrll int error;
98 1.5.2.2 skrll
99 1.5.2.2 skrll if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
100 1.5.2.2 skrll aprint_error(": couldn't get registers\n");
101 1.5.2.2 skrll return;
102 1.5.2.2 skrll }
103 1.5.2.2 skrll sc->sc_clk_reg = fdtbus_clock_get(phandle, "reg");
104 1.5.2.2 skrll if (sc->sc_clk_reg == NULL) {
105 1.5.2.2 skrll aprint_error(": couldn't get clock reg\n");
106 1.5.2.2 skrll return;
107 1.5.2.2 skrll }
108 1.5.2.2 skrll sc->sc_clk_pll = fdtbus_clock_get(phandle, "pll_u");
109 1.5.2.2 skrll if (sc->sc_clk_pll == NULL) {
110 1.5.2.2 skrll aprint_error(": couldn't get clock pll_u\n");
111 1.5.2.2 skrll return;
112 1.5.2.2 skrll }
113 1.5.2.2 skrll sc->sc_clk_utmip = fdtbus_clock_get(phandle, "utmi-pads");
114 1.5.2.2 skrll if (sc->sc_clk_utmip == NULL) {
115 1.5.2.2 skrll aprint_error(": couldn't get clock utmi-pads\n");
116 1.5.2.2 skrll return;
117 1.5.2.2 skrll }
118 1.5.2.2 skrll sc->sc_rst_usb = fdtbus_reset_get(phandle, "usb");
119 1.5.2.2 skrll if (sc->sc_rst_usb == NULL) {
120 1.5.2.2 skrll aprint_error(": couldn't get reset usb\n");
121 1.5.2.2 skrll return;
122 1.5.2.2 skrll }
123 1.5.2.2 skrll sc->sc_rst_utmip = fdtbus_reset_get(phandle, "utmi-pads");
124 1.5.2.2 skrll if (sc->sc_rst_utmip == NULL) {
125 1.5.2.2 skrll aprint_error(": couldn't get reset utmi-pads\n");
126 1.5.2.2 skrll return;
127 1.5.2.2 skrll }
128 1.5.2.2 skrll
129 1.5.2.2 skrll sc->sc_dev = self;
130 1.5.2.2 skrll sc->sc_phandle = phandle;
131 1.5.2.2 skrll sc->sc_bst = faa->faa_bst;
132 1.5.2.2 skrll error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
133 1.5.2.2 skrll if (error) {
134 1.5.2.2 skrll aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error);
135 1.5.2.2 skrll return;
136 1.5.2.2 skrll }
137 1.5.2.2 skrll
138 1.5.2.2 skrll aprint_naive("\n");
139 1.5.2.2 skrll aprint_normal(": USB PHY\n");
140 1.5.2.2 skrll
141 1.5.2.2 skrll if (tegra_usbphy_parse_properties(sc) != 0)
142 1.5.2.2 skrll return;
143 1.5.2.2 skrll
144 1.5.2.2 skrll fdtbus_reset_assert(sc->sc_rst_usb);
145 1.5.2.2 skrll error = clk_enable(sc->sc_clk_reg);
146 1.5.2.2 skrll if (error) {
147 1.5.2.2 skrll aprint_error_dev(self, "couldn't enable clock reg: %d\n",
148 1.5.2.2 skrll error);
149 1.5.2.2 skrll return;
150 1.5.2.2 skrll }
151 1.5.2.2 skrll fdtbus_reset_deassert(sc->sc_rst_usb);
152 1.5.2.2 skrll
153 1.5.2.2 skrll tegra_usbphy_utmip_init(sc);
154 1.5.2.2 skrll
155 1.5.2.2 skrll reg = fdtbus_regulator_acquire(phandle, "vbus-supply");
156 1.5.2.2 skrll if (reg) {
157 1.5.2.2 skrll const uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
158 1.5.2.2 skrll TEGRA_EHCI_PHY_VBUS_SENSORS_REG);
159 1.5.2.2 skrll if ((v & TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS) == 0) {
160 1.5.2.2 skrll fdtbus_regulator_enable(reg);
161 1.5.2.2 skrll } else {
162 1.5.2.2 skrll aprint_normal_dev(self, "VBUS input active\n");
163 1.5.2.2 skrll }
164 1.5.2.2 skrll }
165 1.5.2.2 skrll }
166 1.5.2.2 skrll
167 1.5.2.2 skrll static int
168 1.5.2.2 skrll tegra_usbphy_parse_properties(struct tegra_usbphy_softc *sc)
169 1.5.2.2 skrll {
170 1.5.2.2 skrll #define PROPGET(k, v) \
171 1.5.2.2 skrll if (of_getprop_uint32(sc->sc_phandle, (k), (v))) { \
172 1.5.2.2 skrll aprint_error_dev(sc->sc_dev, \
173 1.5.2.2 skrll "missing property '%s'\n", (k)); \
174 1.5.2.2 skrll return EIO; \
175 1.5.2.2 skrll }
176 1.5.2.2 skrll
177 1.5.2.2 skrll PROPGET("nvidia,hssync-start-delay", &sc->sc_hssync_start_delay);
178 1.5.2.2 skrll PROPGET("nvidia,idle-wait-delay", &sc->sc_idle_wait_delay);
179 1.5.2.2 skrll PROPGET("nvidia,elastic-limit", &sc->sc_elastic_limit);
180 1.5.2.2 skrll PROPGET("nvidia,term-range-adj", &sc->sc_term_range_adj);
181 1.5.2.2 skrll PROPGET("nvidia,xcvr-setup", &sc->sc_xcvr_setup);
182 1.5.2.2 skrll PROPGET("nvidia,xcvr-lsfslew", &sc->sc_xcvr_lsfslew);
183 1.5.2.2 skrll PROPGET("nvidia,xcvr-lsrslew", &sc->sc_xcvr_lsrslew);
184 1.5.2.2 skrll PROPGET("nvidia,hssquelch-level", &sc->sc_hssquelch_level);
185 1.5.2.2 skrll PROPGET("nvidia,hsdiscon-level", &sc->sc_hsdiscon_level);
186 1.5.2.2 skrll PROPGET("nvidia,xcvr-hsslew", &sc->sc_xcvr_hsslew);
187 1.5.2.2 skrll
188 1.5.2.2 skrll return 0;
189 1.5.2.2 skrll #undef PROPGET
190 1.5.2.2 skrll }
191 1.5.2.2 skrll
192 1.5.2.2 skrll static void
193 1.5.2.2 skrll tegra_usbphy_utmip_init(struct tegra_usbphy_softc *sc)
194 1.5.2.2 skrll {
195 1.5.2.2 skrll static u_int init_count = 0;
196 1.5.2.2 skrll bus_space_tag_t bst = sc->sc_bst;
197 1.5.2.2 skrll bus_space_handle_t bsh = sc->sc_bsh;
198 1.5.2.2 skrll int retry;
199 1.5.2.2 skrll
200 1.5.2.2 skrll /* Put UTMIP PHY into reset before programming UTMIP config registers */
201 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
202 1.5.2.2 skrll TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET, 0);
203 1.5.2.2 skrll
204 1.5.2.2 skrll /* Enable UTMIP PHY mode */
205 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
206 1.5.2.2 skrll TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB, 0);
207 1.5.2.2 skrll
208 1.5.2.2 skrll /* Stop crystal clock */
209 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
210 1.5.2.2 skrll 0, TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN);
211 1.5.2.2 skrll delay(1);
212 1.5.2.2 skrll
213 1.5.2.2 skrll /* Clear session status */
214 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_PHY_VBUS_SENSORS_REG,
215 1.5.2.2 skrll 0,
216 1.5.2.2 skrll TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE |
217 1.5.2.2 skrll TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN);
218 1.5.2.2 skrll
219 1.5.2.2 skrll /* Transceiver configuration */
220 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
221 1.5.2.2 skrll __SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) |
222 1.5.2.2 skrll __SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) |
223 1.5.2.2 skrll __SHIFTIN(sc->sc_xcvr_hsslew,
224 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB),
225 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP |
226 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB |
227 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB);
228 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
229 1.5.2.2 skrll __SHIFTIN(sc->sc_term_range_adj,
230 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ),
231 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ);
232 1.5.2.2 skrll
233 1.5.2.2 skrll if (atomic_inc_uint_nv(&init_count) == 1) {
234 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG,
235 1.5.2.2 skrll TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB |
236 1.5.2.2 skrll __SHIFTIN(sc->sc_hsdiscon_level,
237 1.5.2.2 skrll TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL),
238 1.5.2.2 skrll TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD |
239 1.5.2.2 skrll TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL);
240 1.5.2.2 skrll delay(25);
241 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
242 1.5.2.2 skrll 0, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN);
243 1.5.2.2 skrll }
244 1.5.2.2 skrll
245 1.5.2.2 skrll /* Misc config */
246 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG0_REG,
247 1.5.2.2 skrll 0,
248 1.5.2.2 skrll TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE);
249 1.5.2.2 skrll
250 1.5.2.2 skrll /* BIAS cell power down lag */
251 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG,
252 1.5.2.2 skrll __SHIFTIN(5, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT),
253 1.5.2.2 skrll TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT);
254 1.5.2.2 skrll
255 1.5.2.2 skrll /* Debounce config */
256 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG,
257 1.5.2.2 skrll __SHIFTIN(0x7530, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A),
258 1.5.2.2 skrll TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A);
259 1.5.2.2 skrll
260 1.5.2.2 skrll /* Transmit signal preamble config */
261 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_TX_CFG0_REG,
262 1.5.2.2 skrll TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J, 0);
263 1.5.2.2 skrll
264 1.5.2.2 skrll /* Power-down battery charger circuit */
265 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG,
266 1.5.2.2 skrll TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG, 0);
267 1.5.2.2 skrll
268 1.5.2.2 skrll /* Select low speed bias method */
269 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
270 1.5.2.2 skrll 0, TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL);
271 1.5.2.2 skrll
272 1.5.2.2 skrll /* High speed receive config */
273 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG0_REG,
274 1.5.2.2 skrll __SHIFTIN(sc->sc_idle_wait_delay,
275 1.5.2.2 skrll TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) |
276 1.5.2.2 skrll __SHIFTIN(sc->sc_elastic_limit,
277 1.5.2.2 skrll TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT),
278 1.5.2.2 skrll TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT |
279 1.5.2.2 skrll TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT);
280 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG,
281 1.5.2.2 skrll __SHIFTIN(sc->sc_hssync_start_delay,
282 1.5.2.2 skrll TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY),
283 1.5.2.2 skrll TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY);
284 1.5.2.2 skrll
285 1.5.2.2 skrll /* Start crystal clock */
286 1.5.2.2 skrll delay(1);
287 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG,
288 1.5.2.2 skrll TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN, 0);
289 1.5.2.2 skrll
290 1.5.2.2 skrll /* Bring UTMIP PHY out of reset */
291 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG,
292 1.5.2.2 skrll 0, TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET);
293 1.5.2.2 skrll for (retry = 100000; retry > 0; retry--) {
294 1.5.2.2 skrll const uint32_t susp = bus_space_read_4(bst, bsh,
295 1.5.2.2 skrll TEGRA_EHCI_SUSP_CTRL_REG);
296 1.5.2.2 skrll if (susp & TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID)
297 1.5.2.2 skrll break;
298 1.5.2.2 skrll delay(1);
299 1.5.2.2 skrll }
300 1.5.2.2 skrll if (retry == 0) {
301 1.5.2.2 skrll aprint_error_dev(sc->sc_dev, "PHY clock is not valid\n");
302 1.5.2.2 skrll return;
303 1.5.2.2 skrll }
304 1.5.2.2 skrll
305 1.5.2.2 skrll /* Disable ICUSB transceiver */
306 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_ICUSB_CTRL_REG,
307 1.5.2.2 skrll 0,
308 1.5.2.2 skrll TEGRA_EHCI_ICUSB_CTRL_ENB1);
309 1.5.2.2 skrll
310 1.5.2.2 skrll /* Power up UTMPI transceiver */
311 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG,
312 1.5.2.2 skrll 0,
313 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN |
314 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN |
315 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN);
316 1.5.2.2 skrll tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG,
317 1.5.2.2 skrll 0,
318 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN |
319 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN |
320 1.5.2.2 skrll TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN);
321 1.5.2.2 skrll }
322