tegra_usbphy.c revision 1.5
1 /* $NetBSD: tegra_usbphy.c,v 1.5 2015/12/22 22:10:36 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: tegra_usbphy.c,v 1.5 2015/12/22 22:10:36 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/atomic.h> 39 40 #include <arm/nvidia/tegra_reg.h> 41 #include <arm/nvidia/tegra_var.h> 42 #include <arm/nvidia/tegra_usbreg.h> 43 44 #include <dev/fdt/fdtvar.h> 45 46 static int tegra_usbphy_match(device_t, cfdata_t, void *); 47 static void tegra_usbphy_attach(device_t, device_t, void *); 48 49 struct tegra_usbphy_softc { 50 device_t sc_dev; 51 bus_space_tag_t sc_bst; 52 bus_space_handle_t sc_bsh; 53 int sc_phandle; 54 struct clk *sc_clk_reg; 55 struct clk *sc_clk_pll; 56 struct clk *sc_clk_utmip; 57 struct fdtbus_reset *sc_rst_usb; 58 struct fdtbus_reset *sc_rst_utmip; 59 60 struct tegra_gpio_pin *sc_pin_vbus; 61 uint32_t sc_hssync_start_delay; 62 uint32_t sc_idle_wait_delay; 63 uint32_t sc_elastic_limit; 64 uint32_t sc_term_range_adj; 65 uint32_t sc_xcvr_setup; 66 uint32_t sc_xcvr_lsfslew; 67 uint32_t sc_xcvr_lsrslew; 68 uint32_t sc_hssquelch_level; 69 uint32_t sc_hsdiscon_level; 70 uint32_t sc_xcvr_hsslew; 71 }; 72 73 static int tegra_usbphy_parse_properties(struct tegra_usbphy_softc *); 74 static void tegra_usbphy_utmip_init(struct tegra_usbphy_softc *); 75 76 CFATTACH_DECL_NEW(tegra_usbphy, sizeof(struct tegra_usbphy_softc), 77 tegra_usbphy_match, tegra_usbphy_attach, NULL, NULL); 78 79 static int 80 tegra_usbphy_match(device_t parent, cfdata_t cf, void *aux) 81 { 82 const char * const compatible[] = { "nvidia,tegra124-usb-phy", NULL }; 83 struct fdt_attach_args * const faa = aux; 84 85 return of_match_compatible(faa->faa_phandle, compatible); 86 } 87 88 static void 89 tegra_usbphy_attach(device_t parent, device_t self, void *aux) 90 { 91 struct tegra_usbphy_softc * const sc = device_private(self); 92 struct fdt_attach_args * const faa = aux; 93 struct fdtbus_regulator *reg; 94 const int phandle = faa->faa_phandle; 95 bus_addr_t addr; 96 bus_size_t size; 97 int error; 98 99 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 100 aprint_error(": couldn't get registers\n"); 101 return; 102 } 103 sc->sc_clk_reg = fdtbus_clock_get(phandle, "reg"); 104 if (sc->sc_clk_reg == NULL) { 105 aprint_error(": couldn't get clock reg\n"); 106 return; 107 } 108 sc->sc_clk_pll = fdtbus_clock_get(phandle, "pll_u"); 109 if (sc->sc_clk_pll == NULL) { 110 aprint_error(": couldn't get clock pll_u\n"); 111 return; 112 } 113 sc->sc_clk_utmip = fdtbus_clock_get(phandle, "utmi-pads"); 114 if (sc->sc_clk_utmip == NULL) { 115 aprint_error(": couldn't get clock utmi-pads\n"); 116 return; 117 } 118 sc->sc_rst_usb = fdtbus_reset_get(phandle, "usb"); 119 if (sc->sc_rst_usb == NULL) { 120 aprint_error(": couldn't get reset usb\n"); 121 return; 122 } 123 sc->sc_rst_utmip = fdtbus_reset_get(phandle, "utmi-pads"); 124 if (sc->sc_rst_utmip == NULL) { 125 aprint_error(": couldn't get reset utmi-pads\n"); 126 return; 127 } 128 129 sc->sc_dev = self; 130 sc->sc_phandle = phandle; 131 sc->sc_bst = faa->faa_bst; 132 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 133 if (error) { 134 aprint_error(": couldn't map %#llx: %d", (uint64_t)addr, error); 135 return; 136 } 137 138 aprint_naive("\n"); 139 aprint_normal(": USB PHY\n"); 140 141 if (tegra_usbphy_parse_properties(sc) != 0) 142 return; 143 144 fdtbus_reset_assert(sc->sc_rst_usb); 145 error = clk_enable(sc->sc_clk_reg); 146 if (error) { 147 aprint_error_dev(self, "couldn't enable clock reg: %d\n", 148 error); 149 return; 150 } 151 fdtbus_reset_deassert(sc->sc_rst_usb); 152 153 tegra_usbphy_utmip_init(sc); 154 155 reg = fdtbus_regulator_acquire(phandle, "vbus-supply"); 156 if (reg) { 157 const uint32_t v = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 158 TEGRA_EHCI_PHY_VBUS_SENSORS_REG); 159 if ((v & TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS) == 0) { 160 fdtbus_regulator_enable(reg); 161 } else { 162 aprint_normal_dev(self, "VBUS input active\n"); 163 } 164 } 165 } 166 167 static int 168 tegra_usbphy_parse_properties(struct tegra_usbphy_softc *sc) 169 { 170 #define PROPGET(k, v) \ 171 if (of_getprop_uint32(sc->sc_phandle, (k), (v))) { \ 172 aprint_error_dev(sc->sc_dev, \ 173 "missing property '%s'\n", (k)); \ 174 return EIO; \ 175 } 176 177 PROPGET("nvidia,hssync-start-delay", &sc->sc_hssync_start_delay); 178 PROPGET("nvidia,idle-wait-delay", &sc->sc_idle_wait_delay); 179 PROPGET("nvidia,elastic-limit", &sc->sc_elastic_limit); 180 PROPGET("nvidia,term-range-adj", &sc->sc_term_range_adj); 181 PROPGET("nvidia,xcvr-setup", &sc->sc_xcvr_setup); 182 PROPGET("nvidia,xcvr-lsfslew", &sc->sc_xcvr_lsfslew); 183 PROPGET("nvidia,xcvr-lsrslew", &sc->sc_xcvr_lsrslew); 184 PROPGET("nvidia,hssquelch-level", &sc->sc_hssquelch_level); 185 PROPGET("nvidia,hsdiscon-level", &sc->sc_hsdiscon_level); 186 PROPGET("nvidia,xcvr-hsslew", &sc->sc_xcvr_hsslew); 187 188 return 0; 189 #undef PROPGET 190 } 191 192 static void 193 tegra_usbphy_utmip_init(struct tegra_usbphy_softc *sc) 194 { 195 static u_int init_count = 0; 196 bus_space_tag_t bst = sc->sc_bst; 197 bus_space_handle_t bsh = sc->sc_bsh; 198 int retry; 199 200 /* Put UTMIP PHY into reset before programming UTMIP config registers */ 201 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 202 TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET, 0); 203 204 /* Enable UTMIP PHY mode */ 205 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 206 TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB, 0); 207 208 /* Stop crystal clock */ 209 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG, 210 0, TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN); 211 delay(1); 212 213 /* Clear session status */ 214 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_PHY_VBUS_SENSORS_REG, 215 0, 216 TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE | 217 TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN); 218 219 /* Transceiver configuration */ 220 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 221 __SHIFTIN(4, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP) | 222 __SHIFTIN(3, TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB) | 223 __SHIFTIN(sc->sc_xcvr_hsslew, 224 TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB), 225 TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP | 226 TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB | 227 TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB); 228 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG, 229 __SHIFTIN(sc->sc_term_range_adj, 230 TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ), 231 TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ); 232 233 if (atomic_inc_uint_nv(&init_count) == 1) { 234 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG0_REG, 235 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB | 236 __SHIFTIN(sc->sc_hsdiscon_level, 237 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL), 238 TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD | 239 TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL); 240 delay(25); 241 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG, 242 0, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN); 243 } 244 245 /* Misc config */ 246 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG0_REG, 247 0, 248 TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE); 249 250 /* BIAS cell power down lag */ 251 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BIAS_CFG1_REG, 252 __SHIFTIN(5, TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT), 253 TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT); 254 255 /* Debounce config */ 256 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG, 257 __SHIFTIN(0x7530, TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A), 258 TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A); 259 260 /* Transmit signal preamble config */ 261 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_TX_CFG0_REG, 262 TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J, 0); 263 264 /* Power-down battery charger circuit */ 265 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG, 266 TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG, 0); 267 268 /* Select low speed bias method */ 269 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 270 0, TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL); 271 272 /* High speed receive config */ 273 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG0_REG, 274 __SHIFTIN(sc->sc_idle_wait_delay, 275 TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT) | 276 __SHIFTIN(sc->sc_elastic_limit, 277 TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT), 278 TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT | 279 TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT); 280 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_HSRX_CFG1_REG, 281 __SHIFTIN(sc->sc_hssync_start_delay, 282 TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY), 283 TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY); 284 285 /* Start crystal clock */ 286 delay(1); 287 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_MISC_CFG1_REG, 288 TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN, 0); 289 290 /* Bring UTMIP PHY out of reset */ 291 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_SUSP_CTRL_REG, 292 0, TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET); 293 for (retry = 100000; retry > 0; retry--) { 294 const uint32_t susp = bus_space_read_4(bst, bsh, 295 TEGRA_EHCI_SUSP_CTRL_REG); 296 if (susp & TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID) 297 break; 298 delay(1); 299 } 300 if (retry == 0) { 301 aprint_error_dev(sc->sc_dev, "PHY clock is not valid\n"); 302 return; 303 } 304 305 /* Disable ICUSB transceiver */ 306 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_ICUSB_CTRL_REG, 307 0, 308 TEGRA_EHCI_ICUSB_CTRL_ENB1); 309 310 /* Power up UTMPI transceiver */ 311 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG0_REG, 312 0, 313 TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN | 314 TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN | 315 TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN); 316 tegra_reg_set_clear(bst, bsh, TEGRA_EHCI_UTMIP_XCVR_CFG1_REG, 317 0, 318 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN | 319 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN | 320 TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN); 321 } 322
Indexes created Tue Sep 23 07:09:52 GMT 2025