Home | History | Annotate | Line # | Download | only in nvidia 
      1 /* $NetBSD: tegra_xusbreg.h,v 1.1 2016/09/26 20:05:03 jakllsch Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2016 Jonathan A. Kollasch
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
     17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     18  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     19  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
     20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
     26  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _TEGRA_XUSBREG_H_
     30 #define _TEGRA_XUSBREG_H_
     31 
     32 /* in FPCI space */
     33 #define T_XUSB_CFG_ARU_MAILBOX_CMD_REG		0x0e4
     34 #define T_XUSB_CFG_ARU_MAILBOX_CMD_INT_EN		__BIT(31)
     35 #define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_XHCI		__BIT(30)
     36 #define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_SMI		__BIT(29)
     37 #define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_PME		__BIT(28)
     38 #define T_XUSB_CFG_ARU_MAILBOX_CMD_DEST_FALCON		__BIT(27)
     39 #define T_XUSB_CFG_ARU_MAILBOX_DATA_IN_REG	0x0e8
     40 #define MAILBOX_DATA_DATA				__BITS(23,0)
     41 #define MAILBOX_DATA_TYPE				__BITS(31,24)
     42 #define T_XUSB_CFG_ARU_MAILBOX_DATA_OUT_REG	0x0ec
     43 #define T_XUSB_CFG_ARU_MAILBOX_OWNER_REG	0x0f0
     44 #define T_XUSB_CFG_ARU_MAILBOX_OWNER_ID			__BITS(7,0)
     45 #define MAILBOX_OWNER_NONE					0
     46 #define MAILBOX_OWNER_FW					1
     47 #define MAILBOX_OWNER_SW					2
     48 #define T_XUSB_CFG_ARU_C11_CSBRANGE_REG		0x41c
     49 #define T_XUSB_CFG_ARU_C11_CSBRANGE_RANGE		__BITS(31-9,9-9)
     50 #define T_XUSB_CFG_ARU_SMI_INTR_REG		0x428
     51 #define T_XUSB_CFG_ARU_SMI_INTR_EN			__BIT(3)
     52 #define T_XUSB_CFG_ARU_SMI_INTR_FW_HANG			__BIT(1)
     53 #define T_XUSB_CFG_CSB_BASE_ADDR		0x800
     54 
     55 #define XUSB_CSB_RANGE __BITS(31,9)
     56 #define XUSB_CSB_OFFSET __BITS(8,0)
     57 
     58 /* in CSB space via FPCI space*/
     59 #define XUSB_CSB_FALCON_CPUCTL_REG		0x100
     60 #define XUSB_CSB_FALCON_CPUCTL_STOPPED			__BIT(5)
     61 #define XUSB_CSB_FALCON_CPUCTL_HALTED			__BIT(4)
     62 #define XUSB_CSB_FALCON_CPUCTL_STARTCPU			__BIT(1)
     63 #define XUSB_CSB_FALCON_BOOTVEC_REG		0x104
     64 #define XUSB_CSB_FALCON_DMACTL_REG		0x10c
     65 #define XUSB_CSB_FALCON_IMFILLRNG1_REG		0x154
     66 #define XUSB_CSB_FALCON_IMFILLRNG1_TAG_HI		__BITS(31,16)
     67 #define XUSB_CSB_FALCON_IMFILLRNG1_TAG_LO		__BITS(15,0)
     68 #define XUSB_CSB_FALCON_IMFILLCTL_REG		0x158
     69 #define XUSB_CSB_FALCON_IMFILLCTL_NBLOCKS		__BITS(7,0)
     70 
     71 #define XUSB_CSB_MEMPOOL_APMAP_REG		0x10181c
     72 #define XUSB_CSB_MEMPOOL_APMAP_BOOTPATH			__BIT(31)
     73 
     74 #define XUSB_CSB_MEMPOOL_ILOAD_ATTR_REG		0x101a00
     75 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_REG	0x101a04
     76 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_LO_SRC_ADDR		__BITS(7,0)
     77 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_REG	0x101a08
     78 #define XUSB_CSB_MEMPOOL_ILOAD_BASE_HI_SRC_ADDR		__BITS(7,0)
     79 #define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_REG	0x101a10
     80 #define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_COUNT	__BITS(31,24)
     81 #define XUSB_CSB_MEMPOOL_L2IMEMOP_SIZE_SRC_OFFSET	__BITS(19,8)
     82 #define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_REG	0x101a14
     83 #define XUSB_CSB_MEMPOOL_L2IMEMOP_TRIG_ACTION		__BITS(31,24)
     84 #define ACTION_L2IMEM_LOAD_LOCKED_RESULT			0x11
     85 #define ACTION_L2IMEM_INVALIDATE_ALL				0x40
     86 
     87 #define IMEM_BLOCK_SIZE 256
     88 
     89 #endif /* _TEGRA_XUSBREG_H_ */
     90