rk3328_cru.c revision 1.1
1 /* $NetBSD: rk3328_cru.c,v 1.1 2018/06/16 00:19:04 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.1 2018/06/16 00:19:04 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/rockchip/rk_cru.h> 41 #include <arm/rockchip/rk3328_cru.h> 42 43 static int rk3328_cru_match(device_t, cfdata_t, void *); 44 static void rk3328_cru_attach(device_t, device_t, void *); 45 46 static const char * const compatible[] = { 47 "rockchip,rk3328-cru", 48 NULL 49 }; 50 51 CFATTACH_DECL_NEW(rk3328_cru, sizeof(struct rk_cru_softc), 52 rk3328_cru_match, rk3328_cru_attach, NULL, NULL); 53 54 static const struct rk_cru_pll_rate pll_rates[] = { 55 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 56 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 57 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 58 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 59 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 60 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 61 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 62 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 63 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 64 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 65 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 66 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 67 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 68 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 69 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 70 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 71 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 72 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 73 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 74 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 75 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 76 RK_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 77 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 78 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 79 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 80 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 81 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 82 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 83 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 84 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 85 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 86 RK_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 87 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 88 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 89 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 90 RK_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), 91 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 92 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 93 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 94 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 95 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 96 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 97 }; 98 99 static const struct rk_cru_pll_rate pll_frac_rates[] = { 100 RK_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217), 101 RK_PLL_RATE( 983040000, 24, 983, 1, 1, 0, 671088), 102 RK_PLL_RATE( 491520000, 24, 983, 2, 1, 0, 671088), 103 RK_PLL_RATE( 61440000, 6, 215, 7, 2, 0, 671088), 104 RK_PLL_RATE( 56448000, 12, 451, 4, 4, 0, 9797894), 105 RK_PLL_RATE( 40960000, 12, 409, 4, 5, 0, 10066329), 106 }; 107 108 static const struct rk_cru_pll_rate pll_norates[] = { 109 }; 110 111 static const struct rk_cru_arm_rate armclk_rates[] = { 112 RK_ARM_RATE(1296000000, 1), 113 RK_ARM_RATE(1200000000, 1), 114 RK_ARM_RATE(1104000000, 1), 115 RK_ARM_RATE(1008000000, 1), 116 RK_ARM_RATE( 912000000, 1), 117 RK_ARM_RATE( 816000000, 1), 118 RK_ARM_RATE( 696000000, 1), 119 RK_ARM_RATE( 600000000, 1), 120 RK_ARM_RATE( 408000000, 1), 121 RK_ARM_RATE( 312000000, 1), 122 RK_ARM_RATE( 216000000, 1), 123 RK_ARM_RATE( 96000000, 1), 124 }; 125 126 static const char * armclk_parents[] = { "apll", "gpll", "dpll", "npll" }; 127 static const char * aclk_bus_pre_parents[] = { "cpll", "gpll", "hdmiphy" }; 128 static const char * hclk_bus_pre_parents[] = { "aclk_bus_pre" }; 129 static const char * aclk_peri_pre_parents[] = { "cpll", "gpll", "hdmiphy" }; 130 static const char * mmc_parents[] = { "cpll", "gpll", "xin24m", "usb480m" }; 131 static const char * phclk_peri_parents[] = { "aclk_peri_pre" }; 132 static const char * mux_usb480m_parents[] = { "usb480m_phy", "xin24m" }; 133 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 134 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 135 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 136 static const char * mux_mac2io_src_parents[] = { "clk_mac2io_src", "gmac_clkin" }; 137 static const char * mux_mac2io_ext_parents[] = { "clk_mac2io", "gmac_clkin" }; 138 static const char * mux_2plls_parents[] = { "cpll", "gpll" }; 139 static const char * mux_2plls_hdmiphy_parents[] = { "cpll", "gpll", "dummy_hdmiphy" }; 140 static const char * comp_uart_parents[] = { "cpll", "gpll", "usb480m" }; 141 static const char * pclk_gmac_parents[] = { "aclk_gmac" }; 142 143 static struct rk_cru_clk rk3328_cru_clks[] = { 144 RK_PLL(RK3328_PLL_APLL, "apll", "xin24m", 145 0x0000, /* con_base */ 146 0x80, /* mode_reg */ 147 __BIT(0), /* mode_mask */ 148 __BIT(4), /* lock_mask */ 149 pll_frac_rates), 150 RK_PLL(RK3328_PLL_DPLL, "dpll", "xin24m", 151 0x0020, /* con_base */ 152 0x80, /* mode_reg */ 153 __BIT(4), /* mode_mask */ 154 __BIT(3), /* lock_mask */ 155 pll_norates), 156 RK_PLL(RK3328_PLL_CPLL, "cpll", "xin24m", 157 0x0040, /* con_base */ 158 0x80, /* mode_reg */ 159 __BIT(8), /* mode_mask */ 160 __BIT(2), /* lock_mask */ 161 pll_rates), 162 RK_PLL(RK3328_PLL_GPLL, "gpll", "xin24m", 163 0x0060, /* con_base */ 164 0x80, /* mode_reg */ 165 __BIT(12), /* mode_mask */ 166 __BIT(1), /* lock_mask */ 167 pll_frac_rates), 168 RK_PLL(RK3328_PLL_NPLL, "npll", "xin24m", 169 0x00a0, /* con_base */ 170 0x80, /* mode_reg */ 171 __BIT(1), /* mode_mask */ 172 __BIT(0), /* lock_mask */ 173 pll_rates), 174 175 RK_ARM(RK3328_ARMCLK, "armclk", armclk_parents, 176 0x0100, /* reg */ 177 __BITS(7,6), 3, 0, /* mux_mask, mux_main, mux_alt */ 178 __BITS(4,0), /* div_mask */ 179 armclk_rates), 180 181 RK_COMPOSITE(RK3328_ACLK_BUS_PRE, "aclk_bus_pre", aclk_bus_pre_parents, 182 0x0100, /* muxdiv_reg */ 183 __BITS(14,13), /* mux_mask */ 184 __BITS(12,8), /* div_mask */ 185 0x0220, /* gate_reg */ 186 __BIT(0), /* gate_mask */ 187 0), 188 RK_COMPOSITE(RK3328_HCLK_BUS_PRE, "hclk_bus_pre", hclk_bus_pre_parents, 189 0x0104, /* muxdiv_reg */ 190 0, /* mux_mask */ 191 __BITS(9,8), /* div_mask */ 192 0x0220, /* gate_reg */ 193 __BIT(1), /* gate_mask */ 194 0), 195 RK_COMPOSITE(RK3328_PCLK_BUS_PRE, "pclk_bus_pre", hclk_bus_pre_parents, 196 0x0104, /* muxdiv_reg */ 197 0, /* mux_mask */ 198 __BITS(14,12), /* div_mask */ 199 0x0220, /* gate_reg */ 200 __BIT(2), /* gate_mask */ 201 0), 202 RK_COMPOSITE(RK3328_ACLK_PERI_PRE, "aclk_peri_pre", aclk_peri_pre_parents, 203 0x0170, /* muxdiv_reg */ 204 __BITS(7,6), /* mux_mask */ 205 __BITS(4,0), /* div_mask */ 206 0, 0, /* gate_reg, gate_mask */ 207 0), 208 RK_COMPOSITE(RK3328_PCLK_PERI, "pclk_peri", phclk_peri_parents, 209 0x0174, /* muxdiv_reg */ 210 0, /* mux_mask */ 211 __BITS(6,4), /* div_mask */ 212 0x0228, /* gate_reg */ 213 __BIT(2), /* gate_mask */ 214 0), 215 RK_COMPOSITE(RK3328_HCLK_PERI, "hclk_peri", phclk_peri_parents, 216 0x0174, /* muxdiv_reg */ 217 0, /* mux_mask */ 218 __BITS(1,0), /* div_mask */ 219 0x0228, /* gate_reg */ 220 __BIT(1), /* gate_mask */ 221 0), 222 RK_COMPOSITE(RK3328_SCLK_SDMMC, "clk_sdmmc", mmc_parents, 223 0x0178, /* muxdiv_reg */ 224 __BITS(9,8), /* mux_mask */ 225 __BITS(7,0), /* div_mask */ 226 0x0210, /* gate_reg */ 227 __BIT(3), /* gate_mask */ 228 RK_COMPOSITE_ROUND_DOWN), 229 RK_COMPOSITE(RK3328_SCLK_SDIO, "clk_sdio", mmc_parents, 230 0x0180, /* muxdiv_reg */ 231 __BITS(9,8), /* mux_mask */ 232 __BITS(7,0), /* div_mask */ 233 0x0210, /* gate_reg */ 234 __BIT(5), /* gate_mask */ 235 RK_COMPOSITE_ROUND_DOWN), 236 RK_COMPOSITE(RK3328_SCLK_EMMC, "clk_emmc", mmc_parents, 237 0x017c, /* muxdiv_reg */ 238 __BITS(9,8), /* mux_mask */ 239 __BITS(7,0), /* div_mask */ 240 0x0210, /* gate_reg */ 241 __BIT(4), /* gate_mask */ 242 RK_COMPOSITE_ROUND_DOWN), 243 RK_COMPOSITE(0, "clk_uart0_div", comp_uart_parents, 244 0x0138, /* muxdiv_reg */ 245 __BITS(13,12), /* mux_mask */ 246 __BITS(6,0), /* div_mask */ 247 0x0204, /* gate_reg */ 248 __BIT(14), /* gate_mask */ 249 0), 250 RK_COMPOSITE(0, "clk_uart1_div", comp_uart_parents, 251 0x0140, /* muxdiv_reg */ 252 __BITS(13,12), /* mux_mask */ 253 __BITS(6,0), /* div_mask */ 254 0x0208, /* gate_reg */ 255 __BIT(0), /* gate_mask */ 256 0), 257 RK_COMPOSITE(0, "clk_uart2_div", comp_uart_parents, 258 0x0148, /* muxdiv_reg */ 259 __BITS(13,12), /* mux_mask */ 260 __BITS(6,0), /* div_mask */ 261 0x0208, /* gate_reg */ 262 __BIT(2), /* gate_mask */ 263 0), 264 RK_COMPOSITE(RK3328_ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_parents, 265 0x018c, /* muxdiv_reg */ 266 __BITS(7,6), /* mux_mask */ 267 __BITS(4,0), /* div_mask */ 268 0x020c, /* gate_reg */ 269 __BIT(2), /* gate_mask */ 270 0), 271 RK_COMPOSITE(RK3328_PCLK_GMAC, "pclk_gmac", pclk_gmac_parents, 272 0x0164, /* muxdiv_reg */ 273 0, /* mux_mask */ 274 __BITS(10,8), /* div_mask */ 275 0x0224, /* gate_reg */ 276 __BIT(0), /* gate_mask */ 277 0), 278 RK_COMPOSITE(RK3328_SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_parents, 279 0x016c, /* muxdiv_reg */ 280 __BIT(7), /* mux_mask */ 281 __BITS(4,0), /* div_mask */ 282 0x020c, /* gate_reg */ 283 __BIT(1), /* gate_mask */ 284 0), 285 RK_COMPOSITE(RK3328_SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_parents, 286 0x016c, /* muxdiv_reg */ 287 __BIT(15), /* mux_mask */ 288 __BITS(12,8), /* div_mask */ 289 0x020c, /* gate_reg */ 290 __BIT(5), /* gate_mask */ 291 0), 292 293 RK_GATE(0, "apll_core", "apll", 0x200, 0), 294 RK_GATE(0, "dpll_core", "dpll", 0x200, 1), 295 RK_GATE(0, "gpll_core", "gpll", 0x200, 2), 296 RK_GATE(0, "npll_core", "npll", 0x200, 12), 297 RK_GATE(0, "gpll_peri", "gpll", 0x210, 0), 298 RK_GATE(0, "cpll_peri", "cpll", 0x210, 1), 299 RK_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3), 300 RK_GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0x220, 4), 301 RK_GATE(RK3328_ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0), 302 RK_GATE(RK3328_PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0x240, 7), 303 RK_GATE(RK3328_PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0x240, 8), 304 RK_GATE(RK3328_PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0x240, 9), 305 RK_GATE(RK3328_PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0x240, 10), 306 RK_GATE(RK3328_PCLK_UART0, "pclk_uart0", "pclk_bus", 0x240, 11), 307 RK_GATE(RK3328_PCLK_UART1, "pclk_uart1", "pclk_bus", 0x240, 12), 308 RK_GATE(RK3328_PCLK_UART2, "pclk_uart2", "pclk_bus", 0x240, 13), 309 RK_GATE(RK3328_SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", 0x224, 7), 310 RK_GATE(RK3328_SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", 0x224, 4), 311 RK_GATE(RK3328_SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", 0x224, 5), 312 RK_GATE(RK3328_SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", 0x224, 6), 313 RK_GATE(RK3328_ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0x24c, 4), 314 RK_GATE(RK3328_HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24c, 0), 315 RK_GATE(RK3328_HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24c, 1), 316 RK_GATE(RK3328_HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24c, 2), 317 RK_GATE(RK3328_HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24c, 15), 318 RK_GATE(RK3328_HCLK_HOST0, "hclk_host0", "hclk_peri", 0x24c, 6), 319 RK_GATE(RK3328_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", 0x24c, 7), 320 RK_GATE(RK3328_HCLK_OTG, "hclk_otg", "hclk_peri", 0x24c, 8), 321 RK_GATE(RK3328_HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", 0x24c, 9), 322 RK_GATE(RK3328_ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", 0x268, 2), 323 RK_GATE(RK3328_PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", 0x268, 3), 324 325 RK_MUX(RK3328_USB480M, "usb480m", mux_usb480m_parents, 0x0084, __BIT(13)), 326 RK_MUX(RK3328_SCLK_UART0, "sclk_uart0", mux_uart0_parents, 0x0138, __BITS(9,8)), 327 RK_MUX(RK3328_SCLK_UART1, "sclk_uart1", mux_uart1_parents, 0x0140, __BITS(9,8)), 328 RK_MUX(RK3328_SCLK_UART2, "sclk_uart2", mux_uart2_parents, 0x0148, __BITS(9,8)), 329 RK_MUXGRF(RK3328_SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_parents, 0x0904, __BIT(10)), 330 RK_MUXGRF(RK3328_SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_parents, 0x0410, __BIT(14)), 331 }; 332 333 static int 334 rk3328_cru_match(device_t parent, cfdata_t cf, void *aux) 335 { 336 struct fdt_attach_args * const faa = aux; 337 338 return of_match_compatible(faa->faa_phandle, compatible); 339 } 340 341 static void 342 rk3328_cru_attach(device_t parent, device_t self, void *aux) 343 { 344 struct rk_cru_softc * const sc = device_private(self); 345 struct fdt_attach_args * const faa = aux; 346 347 sc->sc_dev = self; 348 sc->sc_phandle = faa->faa_phandle; 349 sc->sc_bst = faa->faa_bst; 350 351 sc->sc_clks = rk3328_cru_clks; 352 sc->sc_nclks = __arraycount(rk3328_cru_clks); 353 354 if (rk_cru_attach(sc) != 0) 355 return; 356 357 aprint_naive("\n"); 358 aprint_normal(": RK3328 CRU\n"); 359 360 rk_cru_print(sc); 361 } 362
Indexes created Mon Sep 29 21:09:56 GMT 2025