rk3328_cru.c revision 1.2
1 /* $NetBSD: rk3328_cru.c,v 1.2 2018/06/16 23:14:47 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk3328_cru.c,v 1.2 2018/06/16 23:14:47 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/rockchip/rk_cru.h> 41 #include <arm/rockchip/rk3328_cru.h> 42 43 #define PLL_CON(n) (0x0000 + (n) * 4) 44 #define MISC_CON 0x0084 45 #define CLKSEL_CON(n) (0x0100 + (n) * 4) 46 #define CLKGATE_CON(n) (0x0200 + (n) * 4) 47 48 #define GRF_SOC_CON4 0x0410 49 #define GRF_MAC_CON1 0x0904 50 51 static int rk3328_cru_match(device_t, cfdata_t, void *); 52 static void rk3328_cru_attach(device_t, device_t, void *); 53 54 static const char * const compatible[] = { 55 "rockchip,rk3328-cru", 56 NULL 57 }; 58 59 CFATTACH_DECL_NEW(rk3328_cru, sizeof(struct rk_cru_softc), 60 rk3328_cru_match, rk3328_cru_attach, NULL, NULL); 61 62 static const struct rk_cru_pll_rate pll_rates[] = { 63 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 64 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 65 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 66 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 67 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 68 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 69 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 70 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 71 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 72 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 73 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 74 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 75 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 76 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 77 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 78 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 79 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 80 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 81 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 82 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 83 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 84 RK_PLL_RATE(1000000000, 6, 500, 2, 1, 1, 0), 85 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 86 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 87 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 88 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 89 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 90 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 91 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 92 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 93 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 94 RK_PLL_RATE( 800000000, 6, 400, 2, 1, 1, 0), 95 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 96 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 97 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 98 RK_PLL_RATE( 594000000, 2, 99, 2, 1, 1, 0), 99 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 100 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 101 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 102 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 103 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 104 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 105 }; 106 107 static const struct rk_cru_pll_rate pll_frac_rates[] = { 108 RK_PLL_RATE(1016064000, 3, 127, 1, 1, 0, 134217), 109 RK_PLL_RATE( 983040000, 24, 983, 1, 1, 0, 671088), 110 RK_PLL_RATE( 491520000, 24, 983, 2, 1, 0, 671088), 111 RK_PLL_RATE( 61440000, 6, 215, 7, 2, 0, 671088), 112 RK_PLL_RATE( 56448000, 12, 451, 4, 4, 0, 9797894), 113 RK_PLL_RATE( 40960000, 12, 409, 4, 5, 0, 10066329), 114 }; 115 116 static const struct rk_cru_pll_rate pll_norates[] = { 117 }; 118 119 static const struct rk_cru_arm_rate armclk_rates[] = { 120 RK_ARM_RATE(1296000000, 1), 121 RK_ARM_RATE(1200000000, 1), 122 RK_ARM_RATE(1104000000, 1), 123 RK_ARM_RATE(1008000000, 1), 124 RK_ARM_RATE( 912000000, 1), 125 RK_ARM_RATE( 816000000, 1), 126 RK_ARM_RATE( 696000000, 1), 127 RK_ARM_RATE( 600000000, 1), 128 RK_ARM_RATE( 408000000, 1), 129 RK_ARM_RATE( 312000000, 1), 130 RK_ARM_RATE( 216000000, 1), 131 RK_ARM_RATE( 96000000, 1), 132 }; 133 134 static const char * armclk_parents[] = { "apll", "gpll", "dpll", "npll" }; 135 static const char * aclk_bus_pre_parents[] = { "cpll", "gpll", "hdmiphy" }; 136 static const char * hclk_bus_pre_parents[] = { "aclk_bus_pre" }; 137 static const char * pclk_bus_pre_parents[] = { "aclk_bus_pre" }; 138 static const char * aclk_peri_pre_parents[] = { "cpll", "gpll", "hdmiphy_peri" }; 139 static const char * mmc_parents[] = { "cpll", "gpll", "xin24m", "usb480m" }; 140 static const char * phclk_peri_parents[] = { "aclk_peri_pre" }; 141 static const char * mux_hdmiphy_parents[] = { "hdmi_phy", "xin24m" }; 142 static const char * mux_usb480m_parents[] = { "usb480m_phy", "xin24m" }; 143 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 144 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 145 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 146 static const char * mux_mac2io_src_parents[] = { "clk_mac2io_src", "gmac_clkin" }; 147 static const char * mux_mac2io_ext_parents[] = { "clk_mac2io", "gmac_clkin" }; 148 static const char * mux_2plls_parents[] = { "cpll", "gpll" }; 149 static const char * mux_2plls_hdmiphy_parents[] = { "cpll", "gpll", "dummy_hdmiphy" }; 150 static const char * comp_uart_parents[] = { "cpll", "gpll", "usb480m" }; 151 static const char * pclk_gmac_parents[] = { "aclk_gmac" }; 152 153 static struct rk_cru_clk rk3328_cru_clks[] = { 154 RK_PLL(RK3328_PLL_APLL, "apll", "xin24m", 155 PLL_CON(0), /* con_base */ 156 0x80, /* mode_reg */ 157 __BIT(0), /* mode_mask */ 158 __BIT(4), /* lock_mask */ 159 pll_frac_rates), 160 RK_PLL(RK3328_PLL_DPLL, "dpll", "xin24m", 161 PLL_CON(8), /* con_base */ 162 0x80, /* mode_reg */ 163 __BIT(4), /* mode_mask */ 164 __BIT(3), /* lock_mask */ 165 pll_norates), 166 RK_PLL(RK3328_PLL_CPLL, "cpll", "xin24m", 167 PLL_CON(16), /* con_base */ 168 0x80, /* mode_reg */ 169 __BIT(8), /* mode_mask */ 170 __BIT(2), /* lock_mask */ 171 pll_rates), 172 RK_PLL(RK3328_PLL_GPLL, "gpll", "xin24m", 173 PLL_CON(24), /* con_base */ 174 0x80, /* mode_reg */ 175 __BIT(12), /* mode_mask */ 176 __BIT(1), /* lock_mask */ 177 pll_frac_rates), 178 RK_PLL(RK3328_PLL_NPLL, "npll", "xin24m", 179 PLL_CON(40), /* con_base */ 180 0x80, /* mode_reg */ 181 __BIT(1), /* mode_mask */ 182 __BIT(0), /* lock_mask */ 183 pll_rates), 184 185 RK_ARM(RK3328_ARMCLK, "armclk", armclk_parents, 186 CLKSEL_CON(0), /* reg */ 187 __BITS(7,6), 3, 1, /* mux_mask, mux_main, mux_alt */ 188 __BITS(4,0), /* div_mask */ 189 armclk_rates), 190 191 RK_COMPOSITE(RK3328_ACLK_BUS_PRE, "aclk_bus_pre", aclk_bus_pre_parents, 192 CLKSEL_CON(0), /* muxdiv_reg */ 193 __BITS(14,13), /* mux_mask */ 194 __BITS(12,8), /* div_mask */ 195 CLKGATE_CON(8), /* gate_reg */ 196 __BIT(0), /* gate_mask */ 197 0), 198 RK_COMPOSITE(RK3328_HCLK_BUS_PRE, "hclk_bus_pre", hclk_bus_pre_parents, 199 CLKSEL_CON(1), /* muxdiv_reg */ 200 0, /* mux_mask */ 201 __BITS(9,8), /* div_mask */ 202 CLKGATE_CON(8), /* gate_reg */ 203 __BIT(1), /* gate_mask */ 204 0), 205 RK_COMPOSITE(RK3328_PCLK_BUS_PRE, "pclk_bus_pre", pclk_bus_pre_parents, 206 CLKSEL_CON(1), /* muxdiv_reg */ 207 0, /* mux_mask */ 208 __BITS(14,12), /* div_mask */ 209 CLKGATE_CON(8), /* gate_reg */ 210 __BIT(2), /* gate_mask */ 211 0), 212 RK_COMPOSITE(RK3328_ACLK_PERI_PRE, "aclk_peri_pre", aclk_peri_pre_parents, 213 CLKSEL_CON(28), /* muxdiv_reg */ 214 __BITS(7,6), /* mux_mask */ 215 __BITS(4,0), /* div_mask */ 216 0, 0, /* gate_reg, gate_mask */ 217 0), 218 RK_COMPOSITE(RK3328_PCLK_PERI, "pclk_peri", phclk_peri_parents, 219 CLKSEL_CON(29), /* muxdiv_reg */ 220 0, /* mux_mask */ 221 __BITS(1,0), /* div_mask */ 222 CLKGATE_CON(10), /* gate_reg */ 223 __BIT(2), /* gate_mask */ 224 0), 225 RK_COMPOSITE(RK3328_HCLK_PERI, "hclk_peri", phclk_peri_parents, 226 CLKSEL_CON(29), /* muxdiv_reg */ 227 0, /* mux_mask */ 228 __BITS(6,4), /* div_mask */ 229 CLKGATE_CON(10), /* gate_reg */ 230 __BIT(1), /* gate_mask */ 231 0), 232 RK_COMPOSITE(RK3328_SCLK_SDMMC, "clk_sdmmc", mmc_parents, 233 CLKSEL_CON(30), /* muxdiv_reg */ 234 __BITS(9,8), /* mux_mask */ 235 __BITS(7,0), /* div_mask */ 236 CLKGATE_CON(4), /* gate_reg */ 237 __BIT(3), /* gate_mask */ 238 RK_COMPOSITE_ROUND_DOWN), 239 RK_COMPOSITE(RK3328_SCLK_SDIO, "clk_sdio", mmc_parents, 240 CLKSEL_CON(31), /* muxdiv_reg */ 241 __BITS(9,8), /* mux_mask */ 242 __BITS(7,0), /* div_mask */ 243 CLKGATE_CON(4), /* gate_reg */ 244 __BIT(4), /* gate_mask */ 245 RK_COMPOSITE_ROUND_DOWN), 246 RK_COMPOSITE(RK3328_SCLK_EMMC, "clk_emmc", mmc_parents, 247 CLKSEL_CON(32), /* muxdiv_reg */ 248 __BITS(9,8), /* mux_mask */ 249 __BITS(7,0), /* div_mask */ 250 CLKGATE_CON(4), /* gate_reg */ 251 __BIT(5), /* gate_mask */ 252 RK_COMPOSITE_ROUND_DOWN), 253 RK_COMPOSITE(0, "clk_uart0_div", comp_uart_parents, 254 CLKSEL_CON(14), /* muxdiv_reg */ 255 __BITS(13,12), /* mux_mask */ 256 __BITS(6,0), /* div_mask */ 257 CLKGATE_CON(1), /* gate_reg */ 258 __BIT(14), /* gate_mask */ 259 0), 260 RK_COMPOSITE(0, "clk_uart1_div", comp_uart_parents, 261 CLKSEL_CON(16), /* muxdiv_reg */ 262 __BITS(13,12), /* mux_mask */ 263 __BITS(6,0), /* div_mask */ 264 CLKGATE_CON(2), /* gate_reg */ 265 __BIT(0), /* gate_mask */ 266 0), 267 RK_COMPOSITE(0, "clk_uart2_div", comp_uart_parents, 268 CLKSEL_CON(18), /* muxdiv_reg */ 269 __BITS(13,12), /* mux_mask */ 270 __BITS(6,0), /* div_mask */ 271 CLKGATE_CON(2), /* gate_reg */ 272 __BIT(2), /* gate_mask */ 273 0), 274 RK_COMPOSITE(RK3328_ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_parents, 275 CLKSEL_CON(35), /* muxdiv_reg */ 276 __BITS(7,6), /* mux_mask */ 277 __BITS(4,0), /* div_mask */ 278 CLKGATE_CON(3), /* gate_reg */ 279 __BIT(2), /* gate_mask */ 280 0), 281 RK_COMPOSITE(RK3328_PCLK_GMAC, "pclk_gmac", pclk_gmac_parents, 282 CLKSEL_CON(25), /* muxdiv_reg */ 283 0, /* mux_mask */ 284 __BITS(10,8), /* div_mask */ 285 CLKGATE_CON(9), /* gate_reg */ 286 __BIT(0), /* gate_mask */ 287 0), 288 RK_COMPOSITE(RK3328_SCLK_MAC2IO_SRC, "clk_mac2io_src", mux_2plls_parents, 289 CLKSEL_CON(27), /* muxdiv_reg */ 290 __BIT(7), /* mux_mask */ 291 __BITS(4,0), /* div_mask */ 292 CLKGATE_CON(3), /* gate_reg */ 293 __BIT(1), /* gate_mask */ 294 0), 295 RK_COMPOSITE(RK3328_SCLK_MAC2IO_OUT, "clk_mac2io_out", mux_2plls_parents, 296 CLKSEL_CON(27), /* muxdiv_reg */ 297 __BIT(15), /* mux_mask */ 298 __BITS(12,8), /* div_mask */ 299 CLKGATE_CON(3), /* gate_reg */ 300 __BIT(5), /* gate_mask */ 301 0), 302 303 RK_GATE(0, "apll_core", "apll", CLKGATE_CON(0), 0), 304 RK_GATE(0, "dpll_core", "dpll", CLKGATE_CON(0), 1), 305 RK_GATE(0, "gpll_core", "gpll", CLKGATE_CON(0), 2), 306 RK_GATE(0, "npll_core", "npll", CLKGATE_CON(0), 12), 307 RK_GATE(0, "gpll_peri", "gpll", CLKGATE_CON(4), 0), 308 RK_GATE(0, "cpll_peri", "cpll", CLKGATE_CON(4), 1), 309 RK_GATE(0, "hdmiphy_peri", "hdmiphy", CLKGATE_CON(4), 2), 310 RK_GATE(0, "pclk_bus", "pclk_bus_pre", CLKGATE_CON(8), 3), 311 RK_GATE(0, "pclk_phy_pre", "pclk_bus_pre", CLKGATE_CON(8), 4), 312 RK_GATE(RK3328_ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLKGATE_CON(10), 0), 313 RK_GATE(RK3328_PCLK_GPIO0, "pclk_gpio0", "pclk_bus", CLKGATE_CON(16), 7), 314 RK_GATE(RK3328_PCLK_GPIO1, "pclk_gpio1", "pclk_bus", CLKGATE_CON(16), 8), 315 RK_GATE(RK3328_PCLK_GPIO2, "pclk_gpio2", "pclk_bus", CLKGATE_CON(16), 9), 316 RK_GATE(RK3328_PCLK_GPIO3, "pclk_gpio3", "pclk_bus", CLKGATE_CON(16), 10), 317 RK_GATE(RK3328_PCLK_UART0, "pclk_uart0", "pclk_bus", CLKGATE_CON(16), 11), 318 RK_GATE(RK3328_PCLK_UART1, "pclk_uart1", "pclk_bus", CLKGATE_CON(16), 12), 319 RK_GATE(RK3328_PCLK_UART2, "pclk_uart2", "pclk_bus", CLKGATE_CON(16), 13), 320 RK_GATE(RK3328_SCLK_MAC2IO_REF, "clk_mac2io_ref", "clk_mac2io", CLKGATE_CON(9), 7), 321 RK_GATE(RK3328_SCLK_MAC2IO_RX, "clk_mac2io_rx", "clk_mac2io", CLKGATE_CON(9), 4), 322 RK_GATE(RK3328_SCLK_MAC2IO_TX, "clk_mac2io_tx", "clk_mac2io", CLKGATE_CON(9), 5), 323 RK_GATE(RK3328_SCLK_MAC2IO_REFOUT, "clk_mac2io_refout", "clk_mac2io", CLKGATE_CON(9), 6), 324 RK_GATE(0, "pclk_phy_niu", "pclk_phy_pre", CLKGATE_CON(15), 15), 325 RK_GATE(RK3328_ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", CLKGATE_CON(19), 4), 326 RK_GATE(RK3328_HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", CLKGATE_CON(19), 0), 327 RK_GATE(RK3328_HCLK_SDIO, "hclk_sdio", "hclk_peri", CLKGATE_CON(19), 1), 328 RK_GATE(RK3328_HCLK_EMMC, "hclk_emmc", "hclk_peri", CLKGATE_CON(19), 2), 329 RK_GATE(RK3328_HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", CLKGATE_CON(19), 15), 330 RK_GATE(RK3328_HCLK_HOST0, "hclk_host0", "hclk_peri", CLKGATE_CON(19), 6), 331 RK_GATE(RK3328_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_peri", CLKGATE_CON(19), 7), 332 RK_GATE(RK3328_HCLK_OTG, "hclk_otg", "hclk_peri", CLKGATE_CON(19), 8), 333 RK_GATE(RK3328_HCLK_OTG_PMU, "hclk_otg_pmu", "hclk_peri", CLKGATE_CON(19), 9), 334 RK_GATE(RK3328_ACLK_MAC2IO, "aclk_mac2io", "aclk_gmac", CLKGATE_CON(26), 2), 335 RK_GATE(RK3328_PCLK_MAC2IO, "pclk_mac2io", "pclk_gmac", CLKGATE_CON(26), 3), 336 RK_GATE(0, "aclk_gmac_niu", "aclk_gmac", CLKGATE_CON(26), 4), 337 RK_GATE(0, "pclk_gmac_niu", "pclk_gmac", CLKGATE_CON(26), 5), 338 339 RK_MUX(RK3328_HDMIPHY, "hdmiphy", mux_hdmiphy_parents, MISC_CON, __BIT(13)), 340 RK_MUX(RK3328_USB480M, "usb480m", mux_usb480m_parents, MISC_CON, __BIT(15)), 341 RK_MUX(RK3328_SCLK_UART0, "sclk_uart0", mux_uart0_parents, CLKSEL_CON(14), __BITS(9,8)), 342 RK_MUX(RK3328_SCLK_UART1, "sclk_uart1", mux_uart1_parents, CLKSEL_CON(16), __BITS(9,8)), 343 RK_MUX(RK3328_SCLK_UART2, "sclk_uart2", mux_uart2_parents, CLKSEL_CON(18), __BITS(9,8)), 344 RK_MUXGRF(RK3328_SCLK_MAC2IO, "clk_mac2io", mux_mac2io_src_parents, GRF_MAC_CON1, __BIT(10)), 345 RK_MUXGRF(RK3328_SCLK_MAC2IO_EXT, "clk_mac2io_ext", mux_mac2io_ext_parents, GRF_SOC_CON4, __BIT(14)), 346 }; 347 348 static int 349 rk3328_cru_match(device_t parent, cfdata_t cf, void *aux) 350 { 351 struct fdt_attach_args * const faa = aux; 352 353 return of_match_compatible(faa->faa_phandle, compatible); 354 } 355 356 static void 357 rk3328_cru_attach(device_t parent, device_t self, void *aux) 358 { 359 struct rk_cru_softc * const sc = device_private(self); 360 struct fdt_attach_args * const faa = aux; 361 362 sc->sc_dev = self; 363 sc->sc_phandle = faa->faa_phandle; 364 sc->sc_bst = faa->faa_bst; 365 366 sc->sc_clks = rk3328_cru_clks; 367 sc->sc_nclks = __arraycount(rk3328_cru_clks); 368 369 if (rk_cru_attach(sc) != 0) 370 return; 371 372 aprint_naive("\n"); 373 aprint_normal(": RK3328 CRU\n"); 374 375 rk_cru_print(sc); 376 } 377
Indexes created Mon Sep 29 21:09:56 GMT 2025