rk3399_cru.c revision 1.1
1 /* $NetBSD: rk3399_cru.c,v 1.1 2018/08/12 16:48:05 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.1 2018/08/12 16:48:05 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/rockchip/rk_cru.h> 41 #include <arm/rockchip/rk3399_cru.h> 42 43 #define PLL_CON(n) (0x0000 + (n) * 4) 44 #define CLKSEL_CON(n) (0x0100 + (n) * 4) 45 #define CLKGATE_CON(n) (0x0300 + (n) * 4) 46 #define SOFTRST_CON(n) (0x0400 + (n) * 4) 47 48 static int rk3399_cru_match(device_t, cfdata_t, void *); 49 static void rk3399_cru_attach(device_t, device_t, void *); 50 51 static const char * const compatible[] = { 52 "rockchip,rk3399-cru", 53 NULL 54 }; 55 56 CFATTACH_DECL_NEW(rk3399_cru, sizeof(struct rk_cru_softc), 57 rk3399_cru_match, rk3399_cru_attach, NULL, NULL); 58 59 static const struct rk_cru_pll_rate pll_rates[] = { 60 RK_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 61 RK_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 62 RK_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 63 RK_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), 64 RK_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), 65 RK_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 66 RK_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 67 RK_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 68 RK_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 69 RK_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 70 RK_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), 71 RK_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), 72 RK_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 73 RK_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 74 RK_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), 75 RK_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), 76 RK_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), 77 RK_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 78 RK_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), 79 RK_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), 80 RK_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), 81 RK_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 82 RK_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), 83 RK_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), 84 RK_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), 85 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 86 RK_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 87 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 88 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 89 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 90 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 91 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 92 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 93 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 94 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 95 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 96 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 97 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 98 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 99 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 100 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 101 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 102 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 103 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 104 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 105 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 106 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 107 RK_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), 108 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 109 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 110 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 111 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 112 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 113 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 114 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 115 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 116 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 117 RK_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), 118 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 119 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 120 RK_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 121 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 122 RK_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), 123 RK_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), 124 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 125 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 126 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 127 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 128 RK_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), 129 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 130 RK_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), 131 RK_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), 132 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 133 RK_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), 134 RK_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), 135 RK_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), 136 RK_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), 137 }; 138 139 static const struct rk_cru_pll_rate pll_norates[] = { 140 }; 141 142 #define PLL_CON0 0x00 143 #define PLL_FBDIV __BITS(11,0) 144 145 #define PLL_CON1 0x04 146 #define PLL_POSTDIV2 __BITS(14,12) 147 #define PLL_POSTDIV1 __BITS(10,8) 148 #define PLL_REFDIV __BITS(5,0) 149 150 #define PLL_CON2 0x08 151 #define PLL_LOCK __BIT(31) 152 #define PLL_FRACDIV __BITS(23,0) 153 154 #define PLL_CON3 0x0c 155 #define PLL_WORK_MODE __BITS(9,8) 156 #define PLL_WORK_MODE_SLOW 0 157 #define PLL_WORK_MODE_NORMAL 1 158 #define PLL_WORK_MODE_DEEP_SLOW 2 159 #define PLL_DSMPD __BIT(3) 160 161 #define PLL_WRITE_MASK 0xffff0000 162 163 static u_int 164 rk3399_cru_pll_get_rate(struct rk_cru_softc *sc, 165 struct rk_cru_clk *clk) 166 { 167 struct rk_cru_pll *pll = &clk->u.pll; 168 struct clk *clkp, *clkp_parent; 169 u_int foutvco, foutpostdiv; 170 171 KASSERT(clk->type == RK_CRU_PLL); 172 173 clkp = &clk->base; 174 clkp_parent = clk_get_parent(clkp); 175 if (clkp_parent == NULL) 176 return 0; 177 178 const u_int fref = clk_get_rate(clkp_parent); 179 if (fref == 0) 180 return 0; 181 182 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); 183 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1); 184 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2); 185 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3); 186 187 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); 188 const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2); 189 const u_int postdiv1 = __SHIFTOUT(con1, PLL_POSTDIV1); 190 const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV); 191 const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV); 192 const u_int dsmpd = __SHIFTOUT(con3, PLL_DSMPD); 193 194 if (dsmpd == 1) { 195 /* integer mode */ 196 foutvco = fref / refdiv * fbdiv; 197 } else { 198 /* fractional mode */ 199 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24); 200 } 201 foutpostdiv = foutvco / postdiv1 / postdiv2; 202 203 return foutpostdiv; 204 } 205 206 static int 207 rk3399_cru_pll_set_rate(struct rk_cru_softc *sc, 208 struct rk_cru_clk *clk, u_int rate) 209 { 210 struct rk_cru_pll *pll = &clk->u.pll; 211 const struct rk_cru_pll_rate *pll_rate = NULL; 212 uint32_t val; 213 int retry; 214 215 KASSERT(clk->type == RK_CRU_PLL); 216 217 if (pll->rates == NULL || rate == 0) 218 return EIO; 219 220 for (int i = 0; i < pll->nrates; i++) 221 if (pll->rates[i].rate == rate) { 222 pll_rate = &pll->rates[i]; 223 break; 224 } 225 if (pll_rate == NULL) 226 return EINVAL; 227 228 val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 229 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 230 231 CRU_WRITE(sc, pll->con_base + PLL_CON0, 232 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | 233 PLL_WRITE_MASK); 234 235 CRU_WRITE(sc, pll->con_base + PLL_CON1, 236 __SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) | 237 __SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) | 238 __SHIFTIN(pll_rate->refdiv, PLL_REFDIV) | 239 PLL_WRITE_MASK); 240 241 val = CRU_READ(sc, pll->con_base + PLL_CON2); 242 val &= ~PLL_FRACDIV; 243 val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV); 244 CRU_WRITE(sc, pll->con_base + PLL_CON2, val); 245 246 val = __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) | (PLL_DSMPD << 16); 247 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 248 249 /* Set PLL work mode to normal */ 250 const uint32_t write_mask = pll->mode_mask << 16; 251 const uint32_t write_val = pll->mode_mask; 252 CRU_WRITE(sc, pll->mode_reg, write_mask | write_val); 253 254 for (retry = 1000; retry > 0; retry--) { 255 if (CRU_READ(sc, pll->con_base + PLL_CON2) & pll->lock_mask) 256 break; 257 delay(1); 258 } 259 260 if (retry == 0) 261 device_printf(sc->sc_dev, "WARNING: %s failed to lock\n", 262 clk->base.name); 263 264 val = __SHIFTIN(PLL_WORK_MODE_NORMAL, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 265 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 266 267 return 0; 268 } 269 270 #define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \ 271 { \ 272 .id = (_id), \ 273 .type = RK_CRU_PLL, \ 274 .base.name = (_name), \ 275 .base.flags = 0, \ 276 .u.pll.parents = (_parents), \ 277 .u.pll.nparents = __arraycount(_parents), \ 278 .u.pll.con_base = (_con_base), \ 279 .u.pll.mode_reg = (_mode_reg), \ 280 .u.pll.mode_mask = (_mode_mask), \ 281 .u.pll.lock_mask = (_lock_mask), \ 282 .u.pll.rates = (_rates), \ 283 .u.pll.nrates = __arraycount(_rates), \ 284 .get_rate = rk3399_cru_pll_get_rate, \ 285 .set_rate = rk3399_cru_pll_set_rate, \ 286 .get_parent = rk_cru_pll_get_parent, \ 287 } 288 289 static const char * pll_parents[] = { "xin24m", "xin32k" }; 290 static const char * mux_pll_src_cpll_gpll_parents[] = { "cpll", "gpll" }; 291 static const char * mux_pll_src_cpll_gpll_npll_parents[] = { "cpll", "gpll", "npll" }; 292 static const char * mux_pll_src_cpll_gpll_upll_parents[] = { "cpll", "gpll", "upll" }; 293 static const char * mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents[] = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; 294 static const char * mux_aclk_perilp0_parents[] = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" }; 295 static const char * mux_hclk_perilp1_parents[] = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" }; 296 static const char * mux_aclk_perihp_parents[] = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" }; 297 static const char * mux_aclk_cci_parents[] = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "vpll_aclk_cci_src" }; 298 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 299 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 300 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 301 static const char * mux_uart3_parents[] = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 302 static const char * mux_rmii_parents[] = { "clk_gmac", "clkin_gmac" }; 303 static const char * mux_aclk_gmac_parents[] = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" }; 304 305 static struct rk_cru_clk rk3399_cru_clks[] = { 306 RK3399_PLL(RK3399_PLL_APLLL, "lpll", pll_parents, 307 PLL_CON(0), /* con_base */ 308 PLL_CON(3), /* mode_reg */ 309 __BIT(8), /* mode_mask */ 310 __BIT(31), /* lock_mask */ 311 pll_rates), 312 RK3399_PLL(RK3399_PLL_APLLB, "bpll", pll_parents, 313 PLL_CON(8), /* con_base */ 314 PLL_CON(11), /* mode_reg */ 315 __BIT(8), /* mode_mask */ 316 __BIT(31), /* lock_mask */ 317 pll_rates), 318 RK3399_PLL(RK3399_PLL_DPLL, "dpll", pll_parents, 319 PLL_CON(16), /* con_base */ 320 PLL_CON(19), /* mode_reg */ 321 __BIT(8), /* mode_mask */ 322 __BIT(31), /* lock_mask */ 323 pll_norates), 324 RK3399_PLL(RK3399_PLL_CPLL, "cpll", pll_parents, 325 PLL_CON(24), /* con_base */ 326 PLL_CON(27), /* mode_reg */ 327 __BIT(8), /* mode_mask */ 328 __BIT(31), /* lock_mask */ 329 pll_rates), 330 RK3399_PLL(RK3399_PLL_GPLL, "gpll", pll_parents, 331 PLL_CON(32), /* con_base */ 332 PLL_CON(35), /* mode_reg */ 333 __BIT(8), /* mode_mask */ 334 __BIT(31), /* lock_mask */ 335 pll_rates), 336 RK3399_PLL(RK3399_PLL_NPLL, "npll", pll_parents, 337 PLL_CON(40), /* con_base */ 338 PLL_CON(43), /* mode_reg */ 339 __BIT(8), /* mode_mask */ 340 __BIT(31), /* lock_mask */ 341 pll_rates), 342 RK3399_PLL(RK3399_PLL_VPLL, "vpll", pll_parents, 343 PLL_CON(43), /* con_base */ 344 PLL_CON(51), /* mode_reg */ 345 __BIT(8), /* mode_mask */ 346 __BIT(31), /* lock_mask */ 347 pll_rates), 348 349 /* 350 * perilp0 351 */ 352 RK_GATE(0, "gpll_aclk_perilp0_src", "gpll", CLKGATE_CON(7), 0), 353 RK_GATE(0, "cpll_aclk_perilp0_src", "cpll", CLKGATE_CON(7), 1), 354 RK_COMPOSITE(RK3399_ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_parents, 355 CLKSEL_CON(23), /* muxdiv_reg */ 356 __BIT(7), /* mux_mask */ 357 __BITS(4,0), /* div_mask */ 358 CLKGATE_CON(7), /* gate_reg */ 359 __BIT(2), /* gate_mask */ 360 0), 361 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", 362 CLKSEL_CON(23), /* div_reg */ 363 __BITS(10,8), /* div_mask */ 364 CLKGATE_CON(7), /* gate_reg */ 365 __BIT(3), /* gate_mask */ 366 0), 367 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 368 CLKSEL_CON(23), /* div_reg */ 369 __BITS(14,12), /* div_mask */ 370 CLKGATE_CON(7), /* gate_reg */ 371 __BIT(4), /* gate_mask */ 372 0), 373 374 /* 375 * perilp1 376 */ 377 RK_GATE(0, "gpll_hclk_perilp1_src", "gpll", CLKGATE_CON(8), 0), 378 RK_GATE(0, "cpll_hclk_perilp1_src", "cpll", CLKGATE_CON(8), 1), 379 RK_COMPOSITE_NOGATE(RK3399_HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_parents, 380 CLKSEL_CON(25), /* muxdiv_reg */ 381 __BITS(10,8), /* mux_mask */ 382 __BITS(4,0), /* div_mask */ 383 0), 384 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", 385 CLKSEL_CON(25), /* div_reg */ 386 __BITS(10,8), /* div_mask */ 387 CLKGATE_CON(8), /* gate_reg */ 388 __BIT(2), /* gate_mask */ 389 0), 390 391 /* 392 * perihp 393 */ 394 RK_GATE(0, "gpll_aclk_perihp_src", "gpll", CLKGATE_CON(5), 0), 395 RK_GATE(0, "cpll_aclk_perihp_src", "cpll", CLKGATE_CON(5), 1), 396 RK_COMPOSITE(RK3399_ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_parents, 397 CLKSEL_CON(14), /* muxdiv_reg */ 398 __BIT(7), /* mux_mask */ 399 __BITS(4,0), /* div_mask */ 400 CLKGATE_CON(5), /* gate_reg */ 401 __BIT(2), /* gate_mask */ 402 0), 403 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERIHP, "hclk_perihp", "aclk_perihp", 404 CLKSEL_CON(14), /* div_reg */ 405 __BITS(10,8), /* div_mask */ 406 CLKGATE_CON(5), /* gate_reg */ 407 __BIT(3), /* gate_mask */ 408 0), 409 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERIHP, "pclk_perihp", "aclk_perihp", 410 CLKSEL_CON(14), /* div_reg */ 411 __BITS(14,12), /* div_mask */ 412 CLKGATE_CON(5), /* gate_reg */ 413 __BIT(4), /* gate_mask */ 414 0), 415 416 /* 417 * CCI 418 */ 419 RK_GATE(0, "cpll_aclk_cci_src", "cpll", CLKGATE_CON(2), 0), 420 RK_GATE(0, "gpll_aclk_cci_src", "gpll", CLKGATE_CON(2), 1), 421 RK_GATE(0, "npll_aclk_cci_src", "npll", CLKGATE_CON(2), 2), 422 RK_GATE(0, "vpll_aclk_cci_src", "vpll", CLKGATE_CON(2), 3), 423 RK_COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_parents, 424 CLKSEL_CON(5), /* muxdiv_reg */ 425 __BITS(7,6), /* mux_mask */ 426 __BITS(4,0), /* div_mask */ 427 CLKGATE_CON(2), /* gate_reg */ 428 __BIT(4), /* gate_mask */ 429 0), 430 RK_GATE(RK3399_ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLKGATE_CON(15), 2), 431 432 /* 433 * GIC 434 */ 435 RK_COMPOSITE(RK3399_ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_parents, 436 CLKSEL_CON(56), /* muxdiv_reg */ 437 __BIT(15), /* mux_mask */ 438 __BITS(12,8), /* div_mask */ 439 CLKGATE_CON(12), /* gate_reg */ 440 __BIT(12), /* gate_mask */ 441 0), 442 443 /* 444 * DDR 445 */ 446 RK_COMPOSITE(RK3399_PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_parents, 447 CLKSEL_CON(6), /* muxdiv_reg */ 448 __BIT(15), /* mux_mask */ 449 __BITS(12,8), /* div_mask */ 450 CLKGATE_CON(3), /* gate_reg */ 451 __BIT(4), /* gate_mask */ 452 0), 453 454 /* 455 * alive 456 */ 457 RK_DIV(RK3399_PCLK_ALIVE, "pclk_alive", "gpll", CLKSEL_CON(57), __BITS(4,0), 0), 458 459 /* 460 * GPIO 461 */ 462 RK_GATE(RK3399_PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLKGATE_CON(31), 3), 463 RK_GATE(RK3399_PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLKGATE_CON(31), 4), 464 RK_GATE(RK3399_PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLKGATE_CON(31), 5), 465 466 /* 467 * UART 468 */ 469 RK_MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_parents, CLKSEL_CON(33), __BITS(13,12)), 470 RK_MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_parents, CLKSEL_CON(33), __BIT(15)), 471 RK_COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 472 CLKSEL_CON(33), /* div_reg */ 473 __BITS(6,0), /* div_mask */ 474 CLKGATE_CON(9), /* gate_reg */ 475 __BIT(0), /* gate_mask */ 476 0), 477 RK_COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 478 CLKSEL_CON(34), /* div_reg */ 479 __BITS(6,0), /* div_mask */ 480 CLKGATE_CON(9), /* gate_reg */ 481 __BIT(2), /* gate_mask */ 482 0), 483 RK_COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 484 CLKSEL_CON(35), /* div_reg */ 485 __BITS(6,0), /* div_mask */ 486 CLKGATE_CON(9), /* gate_reg */ 487 __BIT(4), /* gate_mask */ 488 0), 489 RK_COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 490 CLKSEL_CON(36), /* div_reg */ 491 __BITS(6,0), /* div_mask */ 492 CLKGATE_CON(9), /* gate_reg */ 493 __BIT(6), /* gate_mask */ 494 0), 495 RK_MUX(RK3399_SCLK_UART0, "clk_uart0", mux_uart0_parents, CLKSEL_CON(33), __BITS(9,8)), 496 RK_MUX(RK3399_SCLK_UART1, "clk_uart1", mux_uart1_parents, CLKSEL_CON(34), __BITS(9,8)), 497 RK_MUX(RK3399_SCLK_UART2, "clk_uart2", mux_uart2_parents, CLKSEL_CON(35), __BITS(9,8)), 498 RK_MUX(RK3399_SCLK_UART3, "clk_uart3", mux_uart3_parents, CLKSEL_CON(36), __BITS(9,8)), 499 RK_GATE(RK3399_PCLK_UART0, "pclk_uart0", "pclk_perilp1", CLKGATE_CON(22), 0), 500 RK_GATE(RK3399_PCLK_UART1, "pclk_uart1", "pclk_perilp1", CLKGATE_CON(22), 1), 501 RK_GATE(RK3399_PCLK_UART2, "pclk_uart2", "pclk_perilp1", CLKGATE_CON(22), 2), 502 RK_GATE(RK3399_PCLK_UART3, "pclk_uart3", "pclk_perilp1", CLKGATE_CON(22), 3), 503 504 /* 505 * SDMMC/SDIO 506 */ 507 RK_COMPOSITE(RK3399_HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_parents, 508 CLKSEL_CON(13), /* muxdiv_reg */ 509 __BIT(15), /* mux_mask */ 510 __BITS(12,8), /* div_mask */ 511 CLKGATE_CON(12), /* gate_reg */ 512 __BIT(13), /* gate_mask */ 513 0), 514 RK_COMPOSITE(RK3399_SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 515 CLKSEL_CON(15), /* muxdiv_reg */ 516 __BITS(10,8), /* mux_mask */ 517 __BITS(6,0), /* div_mask */ 518 CLKGATE_CON(6), /* gate_reg */ 519 __BIT(0), /* gate_mask */ 520 0), 521 RK_COMPOSITE(RK3399_SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 522 CLKSEL_CON(16), /* muxdiv_reg */ 523 __BITS(10,8), /* mux_mask */ 524 __BITS(6,0), /* div_mask */ 525 CLKGATE_CON(6), /* gate_reg */ 526 __BIT(1), /* gate_mask */ 527 0), 528 RK_GATE(RK3399_HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLKGATE_CON(33), 8), 529 RK_GATE(RK3399_HCLK_SDIO, "hclk_sdio", "pclk_perilp1", CLKGATE_CON(34), 4), 530 531 /* 532 * GMAC 533 */ 534 RK_COMPOSITE(RK3399_SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_parents, 535 CLKSEL_CON(20), /* muxdiv_reg */ 536 __BITS(15,14), /* mux_mask */ 537 __BITS(12,8), /* div_mask */ 538 CLKGATE_CON(5), /* gate_reg */ 539 __BIT(5), /* gate_mask */ 540 0), 541 RK_MUX(RK3399_SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_parents, CLKSEL_CON(19), __BIT(4)), 542 RK_GATE(RK3399_SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLKGATE_CON(5), 6), 543 RK_GATE(RK3399_SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLKGATE_CON(5), 7), 544 RK_GATE(RK3399_SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLKGATE_CON(5), 8), 545 RK_GATE(RK3399_SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLKGATE_CON(5), 9), 546 RK_GATE(0, "gpll_aclk_gmac_src", "gpll", CLKGATE_CON(6), 8), 547 RK_GATE(0, "cpll_aclk_gmac_src", "cpll", CLKGATE_CON(6), 9), 548 RK_COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_parents, 549 CLKSEL_CON(20), /* muxdiv_reg */ 550 __BIT(17), /* mux_mask */ 551 __BITS(4,0), /* div_mask */ 552 CLKGATE_CON(6), /* gate_reg */ 553 __BIT(10), /* gate_mask */ 554 0), 555 RK_GATE(RK3399_ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLKGATE_CON(32), 0), 556 RK_COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 557 CLKSEL_CON(19), /* div_reg */ 558 __BITS(10,8), /* div_mask */ 559 CLKGATE_CON(6), /* gate_reg */ 560 __BIT(11), /* gate_mask */ 561 0), 562 RK_GATE(RK3399_PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLKGATE_CON(32), 2), 563 564 /* 565 * USB2 566 */ 567 RK_GATE(RK3399_HCLK_HOST0, "hclk_host0", "hclk_perihp", CLKGATE_CON(20), 5), 568 RK_GATE(RK3399_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLKGATE_CON(20), 6), 569 RK_GATE(RK3399_HCLK_HOST1, "hclk_host1", "hclk_perihp", CLKGATE_CON(20), 7), 570 RK_GATE(RK3399_HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLKGATE_CON(20), 8), 571 RK_GATE(RK3399_SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLKGATE_CON(6), 5), 572 RK_GATE(RK3399_SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLKGATE_CON(6), 6), 573 574 /* 575 * USB3 576 */ 577 RK_GATE(RK3399_SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLKGATE_CON(12), 1), 578 RK_GATE(RK3399_SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLKGATE_CON(12), 2), 579 RK_COMPOSITE(RK3399_SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", pll_parents, 580 CLKSEL_CON(40), /* muxdiv_reg */ 581 __BIT(15), /* mux_mask */ 582 __BITS(9,0), /* div_mask */ 583 CLKGATE_CON(12), /* gate_reg */ 584 __BIT(3), /* gate_mask */ 585 0), 586 RK_COMPOSITE(RK3399_SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", pll_parents, 587 CLKSEL_CON(41), /* muxdiv_reg */ 588 __BIT(15), /* mux_mask */ 589 __BITS(9,0), /* div_mask */ 590 CLKGATE_CON(12), /* gate_reg */ 591 __BIT(4), /* gate_mask */ 592 0), 593 RK_COMPOSITE(RK3399_ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_parents, 594 CLKSEL_CON(39), /* muxdiv_reg */ 595 __BITS(7,6), /* mux_mask */ 596 __BITS(4,0), /* div_mask */ 597 CLKGATE_CON(12), /* gate_reg */ 598 __BIT(0), /* gate_mask */ 599 0), 600 RK_GATE(RK3399_ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLKGATE_CON(30), 1), 601 RK_GATE(RK3399_ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLKGATE_CON(30), 2), 602 RK_GATE(RK3399_ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLKGATE_CON(30), 3), 603 RK_GATE(RK3399_ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLKGATE_CON(30), 4), 604 }; 605 606 static int 607 rk3399_cru_match(device_t parent, cfdata_t cf, void *aux) 608 { 609 struct fdt_attach_args * const faa = aux; 610 611 return of_match_compatible(faa->faa_phandle, compatible); 612 } 613 614 static void 615 rk3399_cru_attach(device_t parent, device_t self, void *aux) 616 { 617 struct rk_cru_softc * const sc = device_private(self); 618 struct fdt_attach_args * const faa = aux; 619 620 sc->sc_dev = self; 621 sc->sc_phandle = faa->faa_phandle; 622 sc->sc_bst = faa->faa_bst; 623 624 sc->sc_clks = rk3399_cru_clks; 625 sc->sc_nclks = __arraycount(rk3399_cru_clks); 626 627 sc->sc_softrst_base = SOFTRST_CON(0); 628 629 if (rk_cru_attach(sc) != 0) 630 return; 631 632 aprint_naive("\n"); 633 aprint_normal(": RK3399 CRU\n"); 634 635 rk_cru_print(sc); 636 } 637
Indexes created Fri Oct 03 15:10:06 GMT 2025