rk3399_cru.c revision 1.19
1 /* $NetBSD: rk3399_cru.c,v 1.19 2020/01/04 13:32:32 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.19 2020/01/04 13:32:32 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/rockchip/rk_cru.h> 41 #include <arm/rockchip/rk3399_cru.h> 42 43 #define PLL_CON(n) (0x0000 + (n) * 4) 44 #define CLKSEL_CON(n) (0x0100 + (n) * 4) 45 #define CLKGATE_CON(n) (0x0300 + (n) * 4) 46 #define SOFTRST_CON(n) (0x0400 + (n) * 4) 47 48 static int rk3399_cru_match(device_t, cfdata_t, void *); 49 static void rk3399_cru_attach(device_t, device_t, void *); 50 51 static const char * const compatible[] = { 52 "rockchip,rk3399-cru", 53 NULL 54 }; 55 56 CFATTACH_DECL_NEW(rk3399_cru, sizeof(struct rk_cru_softc), 57 rk3399_cru_match, rk3399_cru_attach, NULL, NULL); 58 59 static const struct rk_cru_pll_rate pll_rates[] = { 60 RK_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 61 RK_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 62 RK_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 63 RK_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), 64 RK_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), 65 RK_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 66 RK_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 67 RK_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 68 RK_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 69 RK_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 70 RK_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), 71 RK_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), 72 RK_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 73 RK_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 74 RK_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), 75 RK_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), 76 RK_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), 77 RK_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 78 RK_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), 79 RK_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), 80 RK_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), 81 RK_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 82 RK_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), 83 RK_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), 84 RK_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), 85 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 86 RK_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 87 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 88 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 89 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 90 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 91 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 92 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 93 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 94 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 95 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 96 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 97 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 98 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 99 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 100 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 101 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 102 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 103 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 104 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 105 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 106 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 107 RK_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), 108 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 109 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 110 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 111 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 112 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 113 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 114 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 115 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 116 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 117 RK_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), 118 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 119 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 120 RK_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 121 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 122 RK_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), 123 RK_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), 124 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 125 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 126 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 127 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 128 RK_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), 129 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 130 RK_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), 131 RK_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), 132 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 133 RK_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), 134 RK_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), 135 RK_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), 136 RK_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), 137 }; 138 139 static const struct rk_cru_pll_rate pll_norates[] = { 140 }; 141 142 #define RK3399_ACLKM_MASK __BITS(12,8) 143 #define RK3399_ATCLK_MASK __BITS(4,0) 144 #define RK3399_PDBG_MASK __BITS(12,8) 145 146 #define RK3399_CPUL_RATE(_rate, _aclkm, _atclk, _pdbg) \ 147 RK_CPU_RATE(_rate, \ 148 CLKSEL_CON(0), RK3399_ACLKM_MASK, \ 149 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \ 150 CLKSEL_CON(1), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \ 151 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK)) 152 153 #define RK3399_CPUB_RATE(_rate, _aclkm, _atclk, _pdbg) \ 154 RK_CPU_RATE(_rate, \ 155 CLKSEL_CON(2), RK3399_ACLKM_MASK, \ 156 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \ 157 CLKSEL_CON(3), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \ 158 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK)) 159 160 static const struct rk_cru_cpu_rate armclkl_rates[] = { 161 RK3399_CPUL_RATE(1800000000, 1, 8, 8), 162 RK3399_CPUL_RATE(1704000000, 1, 8, 8), 163 RK3399_CPUL_RATE(1608000000, 1, 7, 7), 164 RK3399_CPUL_RATE(1512000000, 1, 7, 7), 165 RK3399_CPUL_RATE(1488000000, 1, 6, 6), 166 RK3399_CPUL_RATE(1416000000, 1, 6, 6), 167 RK3399_CPUL_RATE(1200000000, 1, 5, 5), 168 RK3399_CPUL_RATE(1008000000, 1, 5, 5), 169 RK3399_CPUL_RATE( 816000000, 1, 4, 4), 170 RK3399_CPUL_RATE( 696000000, 1, 3, 3), 171 RK3399_CPUL_RATE( 600000000, 1, 3, 3), 172 RK3399_CPUL_RATE( 408000000, 1, 2, 2), 173 RK3399_CPUL_RATE( 312000000, 1, 1, 1), 174 RK3399_CPUL_RATE( 216000000, 1, 1, 1), 175 RK3399_CPUL_RATE( 96000000, 1, 1, 1), 176 }; 177 178 static const struct rk_cru_cpu_rate armclkb_rates[] = { 179 RK3399_CPUB_RATE(2208000000, 1, 11, 11), 180 RK3399_CPUB_RATE(2184000000, 1, 11, 11), 181 RK3399_CPUB_RATE(2088000000, 1, 10, 10), 182 RK3399_CPUB_RATE(2040000000, 1, 10, 10), 183 RK3399_CPUB_RATE(2016000000, 1, 9, 9), 184 RK3399_CPUB_RATE(2000000000, 1, 9, 9), 185 RK3399_CPUB_RATE(1992000000, 1, 9, 9), 186 RK3399_CPUB_RATE(1896000000, 1, 9, 9), 187 RK3399_CPUB_RATE(1800000000, 1, 8, 8), 188 RK3399_CPUB_RATE(1704000000, 1, 8, 8), 189 RK3399_CPUB_RATE(1608000000, 1, 7, 7), 190 RK3399_CPUB_RATE(1512000000, 1, 7, 7), 191 RK3399_CPUB_RATE(1488000000, 1, 6, 6), 192 RK3399_CPUB_RATE(1416000000, 1, 6, 6), 193 RK3399_CPUB_RATE(1200000000, 1, 5, 5), 194 RK3399_CPUB_RATE(1008000000, 1, 5, 5), 195 RK3399_CPUB_RATE( 816000000, 1, 4, 4), 196 RK3399_CPUB_RATE( 696000000, 1, 3, 3), 197 RK3399_CPUB_RATE( 600000000, 1, 3, 3), 198 RK3399_CPUB_RATE( 408000000, 1, 2, 2), 199 RK3399_CPUB_RATE( 312000000, 1, 1, 1), 200 RK3399_CPUB_RATE( 216000000, 1, 1, 1), 201 RK3399_CPUB_RATE( 96000000, 1, 1, 1), 202 }; 203 204 #define PLL_CON0 0x00 205 #define PLL_FBDIV __BITS(11,0) 206 207 #define PLL_CON1 0x04 208 #define PLL_POSTDIV2 __BITS(14,12) 209 #define PLL_POSTDIV1 __BITS(10,8) 210 #define PLL_REFDIV __BITS(5,0) 211 212 #define PLL_CON2 0x08 213 #define PLL_LOCK __BIT(31) 214 #define PLL_FRACDIV __BITS(23,0) 215 216 #define PLL_CON3 0x0c 217 #define PLL_WORK_MODE __BITS(9,8) 218 #define PLL_WORK_MODE_SLOW 0 219 #define PLL_WORK_MODE_NORMAL 1 220 #define PLL_WORK_MODE_DEEP_SLOW 2 221 #define PLL_DSMPD __BIT(3) 222 223 #define PLL_WRITE_MASK 0xffff0000 224 225 static u_int 226 rk3399_cru_pll_get_rate(struct rk_cru_softc *sc, 227 struct rk_cru_clk *clk) 228 { 229 struct rk_cru_pll *pll = &clk->u.pll; 230 struct clk *clkp, *clkp_parent; 231 u_int foutvco, foutpostdiv; 232 233 KASSERT(clk->type == RK_CRU_PLL); 234 235 clkp = &clk->base; 236 clkp_parent = clk_get_parent(clkp); 237 if (clkp_parent == NULL) 238 return 0; 239 240 const u_int fref = clk_get_rate(clkp_parent); 241 if (fref == 0) 242 return 0; 243 244 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); 245 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1); 246 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2); 247 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3); 248 249 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); 250 const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2); 251 const u_int postdiv1 = __SHIFTOUT(con1, PLL_POSTDIV1); 252 const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV); 253 const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV); 254 const u_int dsmpd = __SHIFTOUT(con3, PLL_DSMPD); 255 256 if (dsmpd == 1) { 257 /* integer mode */ 258 foutvco = fref / refdiv * fbdiv; 259 } else { 260 /* fractional mode */ 261 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24); 262 } 263 foutpostdiv = foutvco / postdiv1 / postdiv2; 264 265 return foutpostdiv; 266 } 267 268 static int 269 rk3399_cru_pll_set_rate(struct rk_cru_softc *sc, 270 struct rk_cru_clk *clk, u_int rate) 271 { 272 struct rk_cru_pll *pll = &clk->u.pll; 273 const struct rk_cru_pll_rate *pll_rate = NULL; 274 uint32_t val; 275 int retry, best_diff; 276 277 KASSERT(clk->type == RK_CRU_PLL); 278 279 if (pll->rates == NULL || rate == 0) 280 return EIO; 281 282 best_diff = INT_MAX; 283 for (int i = 0; i < pll->nrates; i++) { 284 const int diff = (int)rate - (int)pll->rates[i].rate; 285 if (abs(diff) < best_diff) { 286 pll_rate = &pll->rates[i]; 287 best_diff = abs(diff); 288 } 289 } 290 291 val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 292 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 293 294 CRU_WRITE(sc, pll->con_base + PLL_CON0, 295 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | (PLL_FBDIV << 16)); 296 297 CRU_WRITE(sc, pll->con_base + PLL_CON1, 298 __SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) | 299 __SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) | 300 __SHIFTIN(pll_rate->refdiv, PLL_REFDIV) | 301 ((PLL_POSTDIV2 | PLL_POSTDIV1 | PLL_REFDIV) << 16)); 302 303 val = CRU_READ(sc, pll->con_base + PLL_CON2); 304 val &= ~PLL_FRACDIV; 305 val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV); 306 CRU_WRITE(sc, pll->con_base + PLL_CON2, val); 307 308 val = __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) | (PLL_DSMPD << 16); 309 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 310 311 for (retry = 1000; retry > 0; retry--) { 312 if (CRU_READ(sc, pll->con_base + PLL_CON2) & pll->lock_mask) 313 break; 314 delay(1); 315 } 316 317 if (retry == 0) 318 device_printf(sc->sc_dev, "WARNING: %s failed to lock\n", 319 clk->base.name); 320 321 /* Set PLL work mode to normal */ 322 val = __SHIFTIN(PLL_WORK_MODE_NORMAL, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 323 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 324 325 return 0; 326 } 327 328 #define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \ 329 { \ 330 .id = (_id), \ 331 .type = RK_CRU_PLL, \ 332 .base.name = (_name), \ 333 .base.flags = 0, \ 334 .u.pll.parents = (_parents), \ 335 .u.pll.nparents = __arraycount(_parents), \ 336 .u.pll.con_base = (_con_base), \ 337 .u.pll.mode_reg = (_mode_reg), \ 338 .u.pll.mode_mask = (_mode_mask), \ 339 .u.pll.lock_mask = (_lock_mask), \ 340 .u.pll.rates = (_rates), \ 341 .u.pll.nrates = __arraycount(_rates), \ 342 .get_rate = rk3399_cru_pll_get_rate, \ 343 .set_rate = rk3399_cru_pll_set_rate, \ 344 .get_parent = rk_cru_pll_get_parent, \ 345 } 346 347 static const char * pll_parents[] = { "xin24m", "xin32k" }; 348 static const char * armclkl_parents[] = { "clk_core_l_lpll_src", "clk_core_l_bpll_src", "clk_core_l_dpll_src", "clk_core_l_gpll_src" }; 349 static const char * armclkb_parents[] = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" }; 350 static const char * mux_clk_tsadc_parents[] = { "xin24m", "xin32k" }; 351 static const char * mux_pll_src_cpll_gpll_parents[] = { "cpll", "gpll" }; 352 static const char * mux_pll_src_cpll_gpll_npll_parents[] = { "cpll", "gpll", "npll" }; 353 static const char * mux_pll_src_cpll_gpll_ppll_parents[] = { "cpll", "gpll", "ppll" }; 354 static const char * mux_pll_src_cpll_gpll_upll_parents[] = { "cpll", "gpll", "upll" }; 355 static const char * mux_pll_src_cpll_gpll_npll_24m_parents[] = { "cpll", "gpll", "npll", "xin24m" }; 356 static const char * mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents[] = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; 357 static const char * mux_pll_src_npll_cpll_gpll_parents[] = { "npll", "cpll", "gpll" }; 358 static const char * mux_pll_src_vpll_cpll_gpll_parents[] = { "vpll", "cpll", "gpll" }; 359 static const char * mux_pll_src_vpll_cpll_gpll_npll_parents[] = { "vpll", "cpll", "gpll", "npll" }; 360 static const char * mux_aclk_perilp0_parents[] = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" }; 361 static const char * mux_hclk_perilp1_parents[] = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" }; 362 static const char * mux_aclk_perihp_parents[] = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" }; 363 static const char * mux_aclk_cci_parents[] = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "vpll_aclk_cci_src" }; 364 static const char * mux_dclk_vop0_parents[] = { "dclk_vop0_div", "dclk_vop0_frac" }; 365 static const char * mux_dclk_vop1_parents[] = { "dclk_vop1_div", "dclk_vop1_frac" }; 366 static const char * mux_i2s0_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "clkin_i2s", "xin12m" }; 367 static const char * mux_i2s1_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s", "xin12m" }; 368 static const char * mux_i2s2_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s", "xin12m" }; 369 static const char * mux_i2sch_parents[] = { "clk_i2s0", "clk_i2s1", "clk_i2s2" }; 370 static const char * mux_i2sout_parents[] = { "clk_i2sout_src", "xin12m" }; 371 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 372 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 373 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 374 static const char * mux_uart3_parents[] = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 375 static const char * mux_rmii_parents[] = { "clk_gmac", "clkin_gmac" }; 376 static const char * mux_aclk_gmac_parents[] = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" }; 377 static const char * mux_aclk_emmc_parents[] = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" }; 378 static const char * mux_pll_src_24m_pciephy_parents[] = { "xin24m", "clk_pciephy_ref100m" }; 379 static const char * mux_pciecore_cru_phy_parents[] = { "clk_pcie_core_cru", "clk_pcie_core_phy" }; 380 381 static struct rk_cru_clk rk3399_cru_clks[] = { 382 RK3399_PLL(RK3399_PLL_APLLL, "lpll", pll_parents, 383 PLL_CON(0), /* con_base */ 384 PLL_CON(3), /* mode_reg */ 385 __BIT(8), /* mode_mask */ 386 __BIT(31), /* lock_mask */ 387 pll_rates), 388 RK3399_PLL(RK3399_PLL_APLLB, "bpll", pll_parents, 389 PLL_CON(8), /* con_base */ 390 PLL_CON(11), /* mode_reg */ 391 __BIT(8), /* mode_mask */ 392 __BIT(31), /* lock_mask */ 393 pll_rates), 394 RK3399_PLL(RK3399_PLL_DPLL, "dpll", pll_parents, 395 PLL_CON(16), /* con_base */ 396 PLL_CON(19), /* mode_reg */ 397 __BIT(8), /* mode_mask */ 398 __BIT(31), /* lock_mask */ 399 pll_norates), 400 RK3399_PLL(RK3399_PLL_CPLL, "cpll", pll_parents, 401 PLL_CON(24), /* con_base */ 402 PLL_CON(27), /* mode_reg */ 403 __BIT(8), /* mode_mask */ 404 __BIT(31), /* lock_mask */ 405 pll_rates), 406 RK3399_PLL(RK3399_PLL_GPLL, "gpll", pll_parents, 407 PLL_CON(32), /* con_base */ 408 PLL_CON(35), /* mode_reg */ 409 __BIT(8), /* mode_mask */ 410 __BIT(31), /* lock_mask */ 411 pll_rates), 412 RK3399_PLL(RK3399_PLL_NPLL, "npll", pll_parents, 413 PLL_CON(40), /* con_base */ 414 PLL_CON(43), /* mode_reg */ 415 __BIT(8), /* mode_mask */ 416 __BIT(31), /* lock_mask */ 417 pll_rates), 418 RK3399_PLL(RK3399_PLL_VPLL, "vpll", pll_parents, 419 PLL_CON(48), /* con_base */ 420 PLL_CON(51), /* mode_reg */ 421 __BIT(8), /* mode_mask */ 422 __BIT(31), /* lock_mask */ 423 pll_rates), 424 425 RK_GATE(0, "clk_core_l_lpll_src", "lpll", CLKGATE_CON(0), 0), 426 RK_GATE(0, "clk_core_l_bpll_src", "bpll", CLKGATE_CON(0), 1), 427 RK_GATE(0, "clk_core_l_dpll_src", "dpll", CLKGATE_CON(0), 2), 428 RK_GATE(0, "clk_core_l_gpll_src", "gpll", CLKGATE_CON(0), 3), 429 430 RK_CPU(RK3399_ARMCLKL, "armclkl", armclkl_parents, 431 CLKSEL_CON(0), /* reg */ 432 __BITS(7,6), 0, 3, /* mux_mask, mux_main, mux_alt */ 433 __BITS(4,0), /* div_mask */ 434 armclkl_rates), 435 436 RK_GATE(0, "clk_core_b_lpll_src", "lpll", CLKGATE_CON(1), 0), 437 RK_GATE(0, "clk_core_b_bpll_src", "bpll", CLKGATE_CON(1), 1), 438 RK_GATE(0, "clk_core_b_dpll_src", "dpll", CLKGATE_CON(1), 2), 439 RK_GATE(0, "clk_core_b_gpll_src", "gpll", CLKGATE_CON(1), 3), 440 441 RK_CPU(RK3399_ARMCLKB, "armclkb", armclkb_parents, 442 CLKSEL_CON(2), /* reg */ 443 __BITS(7,6), 1, 3, /* mux_mask, mux_main, mux_alt */ 444 __BITS(4,0), /* div_mask */ 445 armclkb_rates), 446 447 /* 448 * perilp0 449 */ 450 RK_GATE(0, "gpll_aclk_perilp0_src", "gpll", CLKGATE_CON(7), 0), 451 RK_GATE(0, "cpll_aclk_perilp0_src", "cpll", CLKGATE_CON(7), 1), 452 RK_COMPOSITE(RK3399_ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_parents, 453 CLKSEL_CON(23), /* muxdiv_reg */ 454 __BIT(7), /* mux_mask */ 455 __BITS(4,0), /* div_mask */ 456 CLKGATE_CON(7), /* gate_reg */ 457 __BIT(2), /* gate_mask */ 458 0), 459 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", 460 CLKSEL_CON(23), /* div_reg */ 461 __BITS(10,8), /* div_mask */ 462 CLKGATE_CON(7), /* gate_reg */ 463 __BIT(3), /* gate_mask */ 464 0), 465 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 466 CLKSEL_CON(23), /* div_reg */ 467 __BITS(14,12), /* div_mask */ 468 CLKGATE_CON(7), /* gate_reg */ 469 __BIT(4), /* gate_mask */ 470 0), 471 472 /* 473 * perilp1 474 */ 475 RK_GATE(0, "gpll_hclk_perilp1_src", "gpll", CLKGATE_CON(8), 0), 476 RK_GATE(0, "cpll_hclk_perilp1_src", "cpll", CLKGATE_CON(8), 1), 477 RK_COMPOSITE_NOGATE(RK3399_HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_parents, 478 CLKSEL_CON(25), /* muxdiv_reg */ 479 __BITS(10,8), /* mux_mask */ 480 __BITS(4,0), /* div_mask */ 481 0), 482 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", 483 CLKSEL_CON(25), /* div_reg */ 484 __BITS(10,8), /* div_mask */ 485 CLKGATE_CON(8), /* gate_reg */ 486 __BIT(2), /* gate_mask */ 487 0), 488 489 /* 490 * perihp 491 */ 492 RK_GATE(0, "gpll_aclk_perihp_src", "gpll", CLKGATE_CON(5), 0), 493 RK_GATE(0, "cpll_aclk_perihp_src", "cpll", CLKGATE_CON(5), 1), 494 RK_COMPOSITE(RK3399_ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_parents, 495 CLKSEL_CON(14), /* muxdiv_reg */ 496 __BIT(7), /* mux_mask */ 497 __BITS(4,0), /* div_mask */ 498 CLKGATE_CON(5), /* gate_reg */ 499 __BIT(2), /* gate_mask */ 500 0), 501 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERIHP, "hclk_perihp", "aclk_perihp", 502 CLKSEL_CON(14), /* div_reg */ 503 __BITS(10,8), /* div_mask */ 504 CLKGATE_CON(5), /* gate_reg */ 505 __BIT(3), /* gate_mask */ 506 0), 507 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERIHP, "pclk_perihp", "aclk_perihp", 508 CLKSEL_CON(14), /* div_reg */ 509 __BITS(14,12), /* div_mask */ 510 CLKGATE_CON(5), /* gate_reg */ 511 __BIT(4), /* gate_mask */ 512 0), 513 514 /* 515 * CCI 516 */ 517 RK_GATE(0, "cpll_aclk_cci_src", "cpll", CLKGATE_CON(2), 0), 518 RK_GATE(0, "gpll_aclk_cci_src", "gpll", CLKGATE_CON(2), 1), 519 RK_GATE(0, "npll_aclk_cci_src", "npll", CLKGATE_CON(2), 2), 520 RK_GATE(0, "vpll_aclk_cci_src", "vpll", CLKGATE_CON(2), 3), 521 RK_COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_parents, 522 CLKSEL_CON(5), /* muxdiv_reg */ 523 __BITS(7,6), /* mux_mask */ 524 __BITS(4,0), /* div_mask */ 525 CLKGATE_CON(2), /* gate_reg */ 526 __BIT(4), /* gate_mask */ 527 0), 528 RK_GATE(RK3399_ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLKGATE_CON(15), 2), 529 530 /* 531 * GIC 532 */ 533 RK_COMPOSITE(RK3399_ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_parents, 534 CLKSEL_CON(56), /* muxdiv_reg */ 535 __BIT(15), /* mux_mask */ 536 __BITS(12,8), /* div_mask */ 537 CLKGATE_CON(12), /* gate_reg */ 538 __BIT(12), /* gate_mask */ 539 0), 540 541 /* 542 * DDR 543 */ 544 RK_COMPOSITE(RK3399_PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_parents, 545 CLKSEL_CON(6), /* muxdiv_reg */ 546 __BIT(15), /* mux_mask */ 547 __BITS(12,8), /* div_mask */ 548 CLKGATE_CON(3), /* gate_reg */ 549 __BIT(4), /* gate_mask */ 550 0), 551 552 /* 553 * alive 554 */ 555 RK_DIV(RK3399_PCLK_ALIVE, "pclk_alive", "gpll", CLKSEL_CON(57), __BITS(4,0), 0), 556 557 /* 558 * GPIO 559 */ 560 RK_GATE(RK3399_PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLKGATE_CON(31), 3), 561 RK_GATE(RK3399_PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLKGATE_CON(31), 4), 562 RK_GATE(RK3399_PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLKGATE_CON(31), 5), 563 564 /* 565 * UART 566 */ 567 RK_MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_parents, CLKSEL_CON(33), __BITS(13,12)), 568 RK_MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_parents, CLKSEL_CON(33), __BIT(15)), 569 RK_COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 570 CLKSEL_CON(33), /* div_reg */ 571 __BITS(6,0), /* div_mask */ 572 CLKGATE_CON(9), /* gate_reg */ 573 __BIT(0), /* gate_mask */ 574 0), 575 RK_COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 576 CLKSEL_CON(34), /* div_reg */ 577 __BITS(6,0), /* div_mask */ 578 CLKGATE_CON(9), /* gate_reg */ 579 __BIT(2), /* gate_mask */ 580 0), 581 RK_COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 582 CLKSEL_CON(35), /* div_reg */ 583 __BITS(6,0), /* div_mask */ 584 CLKGATE_CON(9), /* gate_reg */ 585 __BIT(4), /* gate_mask */ 586 0), 587 RK_COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 588 CLKSEL_CON(36), /* div_reg */ 589 __BITS(6,0), /* div_mask */ 590 CLKGATE_CON(9), /* gate_reg */ 591 __BIT(6), /* gate_mask */ 592 0), 593 RK_MUX(RK3399_SCLK_UART0, "clk_uart0", mux_uart0_parents, CLKSEL_CON(33), __BITS(9,8)), 594 RK_MUX(RK3399_SCLK_UART1, "clk_uart1", mux_uart1_parents, CLKSEL_CON(34), __BITS(9,8)), 595 RK_MUX(RK3399_SCLK_UART2, "clk_uart2", mux_uart2_parents, CLKSEL_CON(35), __BITS(9,8)), 596 RK_MUX(RK3399_SCLK_UART3, "clk_uart3", mux_uart3_parents, CLKSEL_CON(36), __BITS(9,8)), 597 RK_GATE(RK3399_PCLK_UART0, "pclk_uart0", "pclk_perilp1", CLKGATE_CON(22), 0), 598 RK_GATE(RK3399_PCLK_UART1, "pclk_uart1", "pclk_perilp1", CLKGATE_CON(22), 1), 599 RK_GATE(RK3399_PCLK_UART2, "pclk_uart2", "pclk_perilp1", CLKGATE_CON(22), 2), 600 RK_GATE(RK3399_PCLK_UART3, "pclk_uart3", "pclk_perilp1", CLKGATE_CON(22), 3), 601 602 /* 603 * SDMMC/SDIO 604 */ 605 RK_COMPOSITE(RK3399_HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_parents, 606 CLKSEL_CON(13), /* muxdiv_reg */ 607 __BIT(15), /* mux_mask */ 608 __BITS(12,8), /* div_mask */ 609 CLKGATE_CON(12), /* gate_reg */ 610 __BIT(13), /* gate_mask */ 611 RK_COMPOSITE_ROUND_DOWN), 612 RK_COMPOSITE(RK3399_SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 613 CLKSEL_CON(15), /* muxdiv_reg */ 614 __BITS(10,8), /* mux_mask */ 615 __BITS(6,0), /* div_mask */ 616 CLKGATE_CON(6), /* gate_reg */ 617 __BIT(0), /* gate_mask */ 618 RK_COMPOSITE_ROUND_DOWN), 619 RK_COMPOSITE(RK3399_SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 620 CLKSEL_CON(16), /* muxdiv_reg */ 621 __BITS(10,8), /* mux_mask */ 622 __BITS(6,0), /* div_mask */ 623 CLKGATE_CON(6), /* gate_reg */ 624 __BIT(1), /* gate_mask */ 625 RK_COMPOSITE_ROUND_DOWN), 626 RK_GATE(RK3399_HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLKGATE_CON(33), 8), 627 RK_GATE(RK3399_HCLK_SDIO, "hclk_sdio", "pclk_perilp1", CLKGATE_CON(34), 4), 628 629 /* 630 * eMMC 631 */ 632 RK_COMPOSITE(RK3399_SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 633 CLKSEL_CON(22), /* muxdiv_reg */ 634 __BITS(10,8), /* mux_mask */ 635 __BITS(6,0), /* div_mask */ 636 CLKGATE_CON(6), /* gate_reg */ 637 __BIT(14), /* gate_mask */ 638 RK_COMPOSITE_ROUND_DOWN), 639 RK_GATE(0, "cpll_aclk_emmc_src", "cpll", CLKGATE_CON(6), 13), 640 RK_GATE(0, "gpll_aclk_emmc_src", "gpll", CLKGATE_CON(6), 12), 641 RK_COMPOSITE_NOGATE(RK3399_ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_parents, 642 CLKSEL_CON(21), /* muxdiv_reg */ 643 __BIT(7), /* mux_mask */ 644 __BITS(4,0), /* div_mask */ 645 0), 646 RK_GATE(RK3399_ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLKGATE_CON(32), 8), 647 RK_GATE(RK3399_ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLKGATE_CON(32), 9), 648 RK_GATE(RK3399_ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLKGATE_CON(32), 10), 649 650 /* 651 * GMAC 652 */ 653 RK_COMPOSITE(RK3399_SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_parents, 654 CLKSEL_CON(20), /* muxdiv_reg */ 655 __BITS(15,14), /* mux_mask */ 656 __BITS(12,8), /* div_mask */ 657 CLKGATE_CON(5), /* gate_reg */ 658 __BIT(5), /* gate_mask */ 659 0), 660 RK_MUX(RK3399_SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_parents, CLKSEL_CON(19), __BIT(4)), 661 RK_GATE(RK3399_SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLKGATE_CON(5), 6), 662 RK_GATE(RK3399_SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLKGATE_CON(5), 7), 663 RK_GATE(RK3399_SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLKGATE_CON(5), 8), 664 RK_GATE(RK3399_SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLKGATE_CON(5), 9), 665 RK_GATE(0, "gpll_aclk_gmac_src", "gpll", CLKGATE_CON(6), 8), 666 RK_GATE(0, "cpll_aclk_gmac_src", "cpll", CLKGATE_CON(6), 9), 667 RK_COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_parents, 668 CLKSEL_CON(20), /* muxdiv_reg */ 669 __BIT(17), /* mux_mask */ 670 __BITS(4,0), /* div_mask */ 671 CLKGATE_CON(6), /* gate_reg */ 672 __BIT(10), /* gate_mask */ 673 0), 674 RK_GATE(RK3399_ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLKGATE_CON(32), 0), 675 RK_COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 676 CLKSEL_CON(19), /* div_reg */ 677 __BITS(10,8), /* div_mask */ 678 CLKGATE_CON(6), /* gate_reg */ 679 __BIT(11), /* gate_mask */ 680 0), 681 RK_GATE(RK3399_PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLKGATE_CON(32), 2), 682 683 /* 684 * USB2 685 */ 686 RK_GATE(RK3399_HCLK_HOST0, "hclk_host0", "hclk_perihp", CLKGATE_CON(20), 5), 687 RK_GATE(RK3399_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLKGATE_CON(20), 6), 688 RK_GATE(RK3399_HCLK_HOST1, "hclk_host1", "hclk_perihp", CLKGATE_CON(20), 7), 689 RK_GATE(RK3399_HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLKGATE_CON(20), 8), 690 RK_GATE(RK3399_SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLKGATE_CON(6), 5), 691 RK_GATE(RK3399_SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLKGATE_CON(6), 6), 692 693 /* 694 * USB3 695 */ 696 RK_GATE(RK3399_SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLKGATE_CON(12), 1), 697 RK_GATE(RK3399_SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLKGATE_CON(12), 2), 698 RK_COMPOSITE(RK3399_SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", pll_parents, 699 CLKSEL_CON(40), /* muxdiv_reg */ 700 __BIT(15), /* mux_mask */ 701 __BITS(9,0), /* div_mask */ 702 CLKGATE_CON(12), /* gate_reg */ 703 __BIT(3), /* gate_mask */ 704 0), 705 RK_COMPOSITE(RK3399_SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", pll_parents, 706 CLKSEL_CON(41), /* muxdiv_reg */ 707 __BIT(15), /* mux_mask */ 708 __BITS(9,0), /* div_mask */ 709 CLKGATE_CON(12), /* gate_reg */ 710 __BIT(4), /* gate_mask */ 711 0), 712 RK_COMPOSITE(RK3399_ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_parents, 713 CLKSEL_CON(39), /* muxdiv_reg */ 714 __BITS(7,6), /* mux_mask */ 715 __BITS(4,0), /* div_mask */ 716 CLKGATE_CON(12), /* gate_reg */ 717 __BIT(0), /* gate_mask */ 718 0), 719 RK_GATE(RK3399_ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLKGATE_CON(30), 1), 720 RK_GATE(RK3399_ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLKGATE_CON(30), 2), 721 RK_GATE(RK3399_ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLKGATE_CON(30), 3), 722 RK_GATE(RK3399_ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLKGATE_CON(30), 4), 723 724 /* 725 * I2C 726 */ 727 RK_COMPOSITE(RK3399_SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_parents, 728 CLKSEL_CON(61), /* muxdiv_reg */ 729 __BIT(7), /* mux_mask */ 730 __BITS(6,0), /* div_mask */ 731 CLKGATE_CON(10), /* gate_reg */ 732 __BIT(0), /* gate_mask */ 733 0), 734 RK_COMPOSITE(RK3399_SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_parents, 735 CLKSEL_CON(62), /* muxdiv_reg */ 736 __BIT(7), /* mux_mask */ 737 __BITS(6,0), /* div_mask */ 738 CLKGATE_CON(10), /* gate_reg */ 739 __BIT(2), /* gate_mask */ 740 0), 741 RK_COMPOSITE(RK3399_SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_parents, 742 CLKSEL_CON(63), /* muxdiv_reg */ 743 __BIT(7), /* mux_mask */ 744 __BITS(6,0), /* div_mask */ 745 CLKGATE_CON(10), /* gate_reg */ 746 __BIT(4), /* gate_mask */ 747 0), 748 RK_COMPOSITE(RK3399_SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_parents, 749 CLKSEL_CON(61), /* muxdiv_reg */ 750 __BIT(15), /* mux_mask */ 751 __BITS(14,8), /* div_mask */ 752 CLKGATE_CON(10), /* gate_reg */ 753 __BIT(1), /* gate_mask */ 754 0), 755 RK_COMPOSITE(RK3399_SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_parents, 756 CLKSEL_CON(62), /* muxdiv_reg */ 757 __BIT(15), /* mux_mask */ 758 __BITS(14,8), /* div_mask */ 759 CLKGATE_CON(10), /* gate_reg */ 760 __BIT(3), /* gate_mask */ 761 0), 762 RK_COMPOSITE(RK3399_SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_parents, 763 CLKSEL_CON(63), /* muxdiv_reg */ 764 __BIT(15), /* mux_mask */ 765 __BITS(14,8), /* div_mask */ 766 CLKGATE_CON(10), /* gate_reg */ 767 __BIT(5), /* gate_mask */ 768 0), 769 RK_GATE(RK3399_PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", CLKGATE_CON(22), 5), 770 RK_GATE(RK3399_PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", CLKGATE_CON(22), 6), 771 RK_GATE(RK3399_PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", CLKGATE_CON(22), 7), 772 RK_GATE(RK3399_PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", CLKGATE_CON(22), 8), 773 RK_GATE(RK3399_PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", CLKGATE_CON(22), 9), 774 RK_GATE(RK3399_PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", CLKGATE_CON(22), 10), 775 776 /* 777 * SPI 778 */ 779 RK_COMPOSITE(RK3399_SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_parents, 780 CLKSEL_CON(59), /* muxdiv_reg */ 781 __BIT(7), /* mux_mask */ 782 __BITS(6,0), /* div_mask */ 783 CLKGATE_CON(9), /* gate_reg */ 784 __BIT(12), /* gate_mask */ 785 0), 786 RK_COMPOSITE(RK3399_SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_parents, 787 CLKSEL_CON(59), /* muxdiv_reg */ 788 __BIT(15), /* mux_mask */ 789 __BITS(14,8), /* div_mask */ 790 CLKGATE_CON(9), /* gate_reg */ 791 __BIT(13), /* gate_mask */ 792 0), 793 RK_COMPOSITE(RK3399_SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_parents, 794 CLKSEL_CON(60), /* muxdiv_reg */ 795 __BIT(7), /* mux_mask */ 796 __BITS(6,0), /* div_mask */ 797 CLKGATE_CON(9), /* gate_reg */ 798 __BIT(14), /* gate_mask */ 799 0), 800 RK_COMPOSITE(RK3399_SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_parents, 801 CLKSEL_CON(60), /* muxdiv_reg */ 802 __BIT(15), /* mux_mask */ 803 __BITS(14,8), /* div_mask */ 804 CLKGATE_CON(9), /* gate_reg */ 805 __BIT(15), /* gate_mask */ 806 0), 807 RK_COMPOSITE(RK3399_SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_parents, 808 CLKSEL_CON(58), /* muxdiv_reg */ 809 __BIT(15), /* mux_mask */ 810 __BITS(14,8), /* div_mask */ 811 CLKGATE_CON(13), /* gate_reg */ 812 __BIT(13), /* gate_mask */ 813 0), 814 RK_GATE(RK3399_PCLK_SPI0, "pclk_rkspi0", "pclk_perilp1", CLKGATE_CON(23), 10), 815 RK_GATE(RK3399_PCLK_SPI1, "pclk_rkspi1", "pclk_perilp1", CLKGATE_CON(23), 11), 816 RK_GATE(RK3399_PCLK_SPI2, "pclk_rkspi2", "pclk_perilp1", CLKGATE_CON(23), 12), 817 RK_GATE(RK3399_PCLK_SPI4, "pclk_rkspi4", "pclk_perilp1", CLKGATE_CON(23), 13), 818 RK_GATE(RK3399_PCLK_SPI5, "pclk_rkspi5", "hclk_perilp1", CLKGATE_CON(34), 5), 819 820 /* Watchdog */ 821 RK_SECURE_GATE(RK3399_PCLK_WDT, "pclk_wdt", "pclk_alive" /*, SECURE_CLKGATE_CON(3), 8 */), 822 823 /* PCIe */ 824 RK_GATE(RK3399_ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLKGATE_CON(20), 2), 825 RK_GATE(RK3399_ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLKGATE_CON(20), 10), 826 RK_GATE(RK3399_PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLKGATE_CON(20), 11), 827 RK_COMPOSITE(RK3399_SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_parents, 828 CLKSEL_CON(17), /* muxdiv_reg */ 829 __BITS(10,8), /* mux_mask */ 830 __BITS(6,0), /* div_mask */ 831 CLKGATE_CON(6), /* gate_reg */ 832 __BIT(2), /* gate_mask */ 833 0), 834 RK_COMPOSITE_NOMUX(RK3399_SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 835 CLKSEL_CON(18), /* div_reg */ 836 __BITS(15,11), /* div_mask */ 837 CLKGATE_CON(12), /* gate_reg */ 838 __BIT(6), /* gate_mask */ 839 0), 840 RK_MUX(RK3399_SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_parents, CLKSEL_CON(18), __BIT(10)), 841 RK_COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_parents, 842 CLKSEL_CON(18), /* muxdiv_reg */ 843 __BITS(9,8), /* mux_mask */ 844 __BITS(6,0), /* div_mask */ 845 CLKGATE_CON(6), /* gate_reg */ 846 __BIT(3), /* gate_mask */ 847 0), 848 RK_MUX(RK3399_SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_parents, CLKSEL_CON(18), __BIT(7)), 849 850 /* TSADC */ 851 RK_COMPOSITE(RK3399_SCLK_TSADC, "clk_tsadc", mux_clk_tsadc_parents, 852 CLKSEL_CON(27), /* muxdiv_reg */ 853 __BIT(15), /* mux_mask */ 854 __BITS(9,0), /* div_mask */ 855 CLKGATE_CON(9), /* gate_reg */ 856 __BIT(1), /* gate_mask */ 857 RK_COMPOSITE_ROUND_DOWN), 858 RK_GATE(RK3399_PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", CLKGATE_CON(22), 13), 859 860 /* VOP0 */ 861 RK_COMPOSITE(RK3399_ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_parents, 862 CLKSEL_CON(47), /* muxdiv_reg */ 863 __BITS(7,6), /* mux_mask */ 864 __BITS(4,0), /* div_mask */ 865 CLKGATE_CON(10), /* gate_reg */ 866 __BIT(8), /* gate_mask */ 867 0), 868 RK_COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 869 CLKSEL_CON(47), /* div_reg */ 870 __BITS(12,8), /* div_mask */ 871 CLKGATE_CON(10), /* gate_reg */ 872 __BIT(9), /* gate_mask */ 873 0), 874 RK_COMPOSITE(RK3399_DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_parents, 875 CLKSEL_CON(49), /* muxdiv_reg */ 876 __BITS(9,8), /* mux_mask */ 877 __BITS(7,0), /* div_mask */ 878 CLKGATE_CON(10), /* gate_reg */ 879 __BIT(12), /* gate_mask */ 880 RK_COMPOSITE_SET_RATE_PARENT), 881 RK_GATE(RK3399_ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLKGATE_CON(28), 3), 882 RK_GATE(RK3399_HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLKGATE_CON(28), 2), 883 RK_COMPOSITE_FRAC(RK3399_DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 884 CLKSEL_CON(106), /* frac_reg */ 885 0), 886 RK_MUX(RK3399_DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_parents, CLKSEL_CON(49), __BIT(11)), 887 888 /* VOP1 */ 889 RK_COMPOSITE(RK3399_ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_parents, 890 CLKSEL_CON(48), /* muxdiv_reg */ 891 __BITS(7,6), /* mux_mask */ 892 __BITS(4,0), /* div_mask */ 893 CLKGATE_CON(10), /* gate_reg */ 894 __BIT(10), /* gate_mask */ 895 0), 896 RK_COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 897 CLKSEL_CON(48), /* div_reg */ 898 __BITS(12,8), /* div_mask */ 899 CLKGATE_CON(10), /* gate_reg */ 900 __BIT(11), /* gate_mask */ 901 0), 902 RK_COMPOSITE(RK3399_DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_parents, 903 CLKSEL_CON(50), /* muxdiv_reg */ 904 __BITS(9,8), /* mux_mask */ 905 __BITS(7,0), /* div_mask */ 906 CLKGATE_CON(10), /* gate_reg */ 907 __BIT(13), /* gate_mask */ 908 RK_COMPOSITE_SET_RATE_PARENT), 909 RK_GATE(RK3399_ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLKGATE_CON(28), 7), 910 RK_GATE(RK3399_HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLKGATE_CON(28), 6), 911 RK_COMPOSITE_FRAC(RK3399_DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 912 CLKSEL_CON(107), /* frac_reg */ 913 0), 914 RK_MUX(RK3399_DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_parents, CLKSEL_CON(50), __BIT(11)), 915 916 /* VIO */ 917 RK_COMPOSITE(RK3399_ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_parents, 918 CLKSEL_CON(42), /* muxdiv_reg */ 919 __BITS(7,6), /* mux_mask */ 920 __BITS(4,0), /* div_mask */ 921 CLKGATE_CON(11), /* gate_reg */ 922 __BIT(0), /* gate_mask */ 923 0), 924 RK_COMPOSITE_NOMUX(RK3399_PCLK_VIO, "pclk_vio", "aclk_vio", 925 CLKSEL_CON(43), /* div_reg */ 926 __BITS(4,0), /* div_mask */ 927 CLKGATE_CON(11), /* gate_reg */ 928 __BIT(1), /* gate_mask */ 929 0), 930 RK_GATE(RK3399_PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLKGATE_CON(29), 12), 931 932 /* HDMI */ 933 RK_COMPOSITE(RK3399_ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_parents, 934 CLKSEL_CON(42), /* muxdiv_reg */ 935 __BITS(15,14), /* mux_mask */ 936 __BITS(12,8), /* div_mask */ 937 CLKGATE_CON(11), /* gate_reg */ 938 __BIT(12), /* gate_mask */ 939 0), 940 RK_COMPOSITE_NOMUX(RK3399_PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 941 CLKSEL_CON(43), /* div_reg */ 942 __BITS(14,10), /* div_mask */ 943 CLKGATE_CON(11), /* gate_reg */ 944 __BIT(10), /* gate_mask */ 945 0), 946 RK_COMPOSITE(RK3399_SCLK_HDMI_CEC, "clk_hdmi_cec", pll_parents, 947 CLKSEL_CON(45), /* muxdiv_reg */ 948 __BIT(15), /* mux_mask */ 949 __BITS(9,0), /* div_mask */ 950 CLKGATE_CON(11), /* gate_reg */ 951 __BIT(7), /* gate_mask */ 952 0), 953 RK_GATE(RK3399_PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLKGATE_CON(29), 6), 954 RK_GATE(RK3399_SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLKGATE_CON(11), 6), 955 956 /* I2S2 */ 957 RK_COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_parents, 958 CLKSEL_CON(28), /* muxdiv_reg */ 959 __BIT(7), /* mux_mask */ 960 __BITS(6,0), /* div_mask */ 961 CLKGATE_CON(8), /* gate_reg */ 962 __BIT(3), /* gate_mask */ 963 0), 964 RK_COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_parents, 965 CLKSEL_CON(29), /* muxdiv_reg */ 966 __BIT(7), /* mux_mask */ 967 __BITS(6,0), /* div_mask */ 968 CLKGATE_CON(8), /* gate_reg */ 969 __BIT(6), /* gate_mask */ 970 0), 971 RK_COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_parents, 972 CLKSEL_CON(30), /* muxdiv_reg */ 973 __BIT(7), /* mux_mask */ 974 __BITS(6,0), /* div_mask */ 975 CLKGATE_CON(8), /* gate_reg */ 976 __BIT(9), /* gate_mask */ 977 0), 978 RK_COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div", 979 CLKSEL_CON(96), /* frac_reg */ 980 0), 981 RK_COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div", 982 CLKSEL_CON(97), /* frac_reg */ 983 0), 984 RK_COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div", 985 CLKSEL_CON(98), /* frac_reg */ 986 0), 987 RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(28), __BITS(9,8)), 988 RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(29), __BITS(9,8)), 989 RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(30), __BITS(9,8)), 990 RK_GATE(RK3399_SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(8), 5), 991 RK_GATE(RK3399_SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(8), 8), 992 RK_GATE(RK3399_SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(8), 11), 993 RK_GATE(RK3399_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLKGATE_CON(34), 0), 994 RK_GATE(RK3399_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLKGATE_CON(34), 1), 995 RK_GATE(RK3399_HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLKGATE_CON(34), 2), 996 RK_MUX(0, "clk_i2sout_src", mux_i2sch_parents, CLKSEL_CON(31), __BITS(1,0)), 997 RK_COMPOSITE(RK3399_SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_parents, 998 CLKSEL_CON(31), /* muxdiv_reg */ 999 __BIT(2), /* mux_mask */ 1000 0, /* div_mask */ 1001 CLKGATE_CON(8), /* gate_reg */ 1002 __BIT(12), /* gate_mask */ 1003 RK_COMPOSITE_SET_RATE_PARENT), 1004 1005 /* eDP */ 1006 RK_COMPOSITE(RK3399_PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_parents, 1007 CLKSEL_CON(44), /* muxdiv_reg */ 1008 __BIT(15), /* mux_mask */ 1009 __BITS(13,8), /* div_mask */ 1010 CLKGATE_CON(11), /* gate_reg */ 1011 __BIT(11), /* gate_mask */ 1012 0), 1013 RK_GATE(RK3399_PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLKGATE_CON(32), 12), 1014 RK_GATE(RK3399_PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLKGATE_CON(32), 13), 1015 1016 RK_COMPOSITE(RK3399_SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_parents, 1017 CLKSEL_CON(46), /* muxdiv_reg */ 1018 __BITS(7,6), /* mux_mask */ 1019 __BITS(4,0), /* div_mask */ 1020 CLKGATE_CON(11), /* gate_reg */ 1021 __BIT(8), /* gate_mask */ 1022 0), 1023 RK_GATE(RK3399_PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLKGATE_CON(29), 7), 1024 1025 }; 1026 1027 static const struct rk3399_init_param { 1028 const char *clk; 1029 const char *parent; 1030 } rk3399_init_params[] = { 1031 { .clk = "clk_i2s0_mux", .parent = "clk_i2s0_frac" }, 1032 { .clk = "clk_i2s1_mux", .parent = "clk_i2s1_frac" }, 1033 { .clk = "clk_i2s2_mux", .parent = "clk_i2s2_frac" }, 1034 { .clk = "dclk_vop0_div", .parent = "gpll" }, 1035 { .clk = "dclk_vop1_div", .parent = "gpll" }, 1036 { .clk = "dclk_vop0", .parent = "dclk_vop0_frac" }, 1037 { .clk = "dclk_vop1", .parent = "dclk_vop1_frac" }, 1038 }; 1039 1040 static void 1041 rk3399_cru_init(struct rk_cru_softc *sc) 1042 { 1043 struct rk_cru_clk *clk, *pclk; 1044 uint32_t write_mask, write_val; 1045 int error; 1046 u_int n; 1047 1048 /* 1049 * Force an update of BPLL to bring it out of slow mode. 1050 */ 1051 clk = rk_cru_clock_find(sc, "armclkb"); 1052 clk_set_rate(&clk->base, clk_get_rate(&clk->base)); 1053 1054 /* 1055 * Set DCLK_VOP0 and DCLK_VOP1 dividers to 1. 1056 */ 1057 write_mask = __BITS(7,0) << 16; 1058 write_val = 0; 1059 CRU_WRITE(sc, CLKSEL_CON(49), write_mask | write_val); 1060 CRU_WRITE(sc, CLKSEL_CON(50), write_mask | write_val); 1061 1062 /* 1063 * Set defaults 1064 */ 1065 for (n = 0; n < __arraycount(rk3399_init_params); n++) { 1066 const struct rk3399_init_param *param = &rk3399_init_params[n]; 1067 clk = rk_cru_clock_find(sc, param->clk); 1068 KASSERTMSG(clk != NULL, "couldn't find clock %s", param->clk); 1069 if (param->parent != NULL) { 1070 pclk = rk_cru_clock_find(sc, param->parent); 1071 KASSERTMSG(pclk != NULL, "couldn't find clock %s", param->parent); 1072 error = clk_set_parent(&clk->base, &pclk->base); 1073 if (error != 0) { 1074 aprint_error_dev(sc->sc_dev, "couldn't set %s parent to %s: %d\n", 1075 param->clk, param->parent, error); 1076 continue; 1077 } 1078 } 1079 } 1080 } 1081 1082 static int 1083 rk3399_cru_match(device_t parent, cfdata_t cf, void *aux) 1084 { 1085 struct fdt_attach_args * const faa = aux; 1086 1087 return of_match_compatible(faa->faa_phandle, compatible); 1088 } 1089 1090 static void 1091 rk3399_cru_attach(device_t parent, device_t self, void *aux) 1092 { 1093 struct rk_cru_softc * const sc = device_private(self); 1094 struct fdt_attach_args * const faa = aux; 1095 1096 sc->sc_dev = self; 1097 sc->sc_phandle = faa->faa_phandle; 1098 sc->sc_bst = faa->faa_bst; 1099 1100 sc->sc_clks = rk3399_cru_clks; 1101 sc->sc_nclks = __arraycount(rk3399_cru_clks); 1102 1103 sc->sc_softrst_base = SOFTRST_CON(0); 1104 1105 if (rk_cru_attach(sc) != 0) 1106 return; 1107 1108 aprint_naive("\n"); 1109 aprint_normal(": RK3399 CRU\n"); 1110 1111 rk3399_cru_init(sc); 1112 1113 rk_cru_print(sc); 1114 } 1115
Indexes created Fri Oct 03 15:10:06 GMT 2025