rk3399_cru.c revision 1.22
1 /* $NetBSD: rk3399_cru.c,v 1.22 2021/05/20 01:07:24 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.22 2021/05/20 01:07:24 msaitoh Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/rockchip/rk_cru.h> 41 #include <arm/rockchip/rk3399_cru.h> 42 43 #define PLL_CON(n) (0x0000 + (n) * 4) 44 #define CLKSEL_CON(n) (0x0100 + (n) * 4) 45 #define CLKGATE_CON(n) (0x0300 + (n) * 4) 46 #define SOFTRST_CON(n) (0x0400 + (n) * 4) 47 48 static int rk3399_cru_match(device_t, cfdata_t, void *); 49 static void rk3399_cru_attach(device_t, device_t, void *); 50 51 static const struct device_compatible_entry compat_data[] = { 52 { .compat = "rockchip,rk3399-cru" }, 53 DEVICE_COMPAT_EOL 54 }; 55 56 CFATTACH_DECL_NEW(rk3399_cru, sizeof(struct rk_cru_softc), 57 rk3399_cru_match, rk3399_cru_attach, NULL, NULL); 58 59 static const struct rk_cru_pll_rate pll_rates[] = { 60 RK_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 61 RK_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 62 RK_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 63 RK_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), 64 RK_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), 65 RK_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 66 RK_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 67 RK_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 68 RK_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 69 RK_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 70 RK_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), 71 RK_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), 72 RK_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 73 RK_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 74 RK_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), 75 RK_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), 76 RK_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), 77 RK_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 78 RK_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), 79 RK_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), 80 RK_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), 81 RK_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 82 RK_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), 83 RK_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), 84 RK_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), 85 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 86 RK_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 87 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 88 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 89 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 90 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 91 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 92 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 93 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 94 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 95 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 96 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 97 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 98 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 99 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 100 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 101 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 102 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 103 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 104 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 105 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 106 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 107 RK_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), 108 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 109 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 110 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 111 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 112 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 113 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 114 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 115 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 116 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 117 RK_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), 118 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 119 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 120 RK_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 121 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 122 RK_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), 123 RK_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), 124 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 125 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 126 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 127 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 128 RK_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), 129 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 130 RK_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), 131 RK_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), 132 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 133 RK_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), 134 RK_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), 135 RK_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), 136 RK_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), 137 }; 138 139 static const struct rk_cru_pll_rate pll_norates[] = { 140 }; 141 142 #define RK3399_ACLKM_MASK __BITS(12,8) 143 #define RK3399_ATCLK_MASK __BITS(4,0) 144 #define RK3399_PDBG_MASK __BITS(12,8) 145 146 #define RK3399_CPUL_RATE(_rate, _aclkm, _atclk, _pdbg) \ 147 RK_CPU_RATE(_rate, \ 148 CLKSEL_CON(0), RK3399_ACLKM_MASK, \ 149 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \ 150 CLKSEL_CON(1), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \ 151 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK)) 152 153 #define RK3399_CPUB_RATE(_rate, _aclkm, _atclk, _pdbg) \ 154 RK_CPU_RATE(_rate, \ 155 CLKSEL_CON(2), RK3399_ACLKM_MASK, \ 156 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \ 157 CLKSEL_CON(3), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \ 158 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK)) 159 160 static const struct rk_cru_cpu_rate armclkl_rates[] = { 161 RK3399_CPUL_RATE(1800000000, 1, 8, 8), 162 RK3399_CPUL_RATE(1704000000, 1, 8, 8), 163 RK3399_CPUL_RATE(1608000000, 1, 7, 7), 164 RK3399_CPUL_RATE(1512000000, 1, 7, 7), 165 RK3399_CPUL_RATE(1488000000, 1, 6, 6), 166 RK3399_CPUL_RATE(1416000000, 1, 6, 6), 167 RK3399_CPUL_RATE(1200000000, 1, 5, 5), 168 RK3399_CPUL_RATE(1008000000, 1, 5, 5), 169 RK3399_CPUL_RATE( 816000000, 1, 4, 4), 170 RK3399_CPUL_RATE( 696000000, 1, 3, 3), 171 RK3399_CPUL_RATE( 600000000, 1, 3, 3), 172 RK3399_CPUL_RATE( 408000000, 1, 2, 2), 173 RK3399_CPUL_RATE( 312000000, 1, 1, 1), 174 RK3399_CPUL_RATE( 216000000, 1, 1, 1), 175 RK3399_CPUL_RATE( 96000000, 1, 1, 1), 176 }; 177 178 static const struct rk_cru_cpu_rate armclkb_rates[] = { 179 RK3399_CPUB_RATE(2208000000, 1, 11, 11), 180 RK3399_CPUB_RATE(2184000000, 1, 11, 11), 181 RK3399_CPUB_RATE(2088000000, 1, 10, 10), 182 RK3399_CPUB_RATE(2040000000, 1, 10, 10), 183 RK3399_CPUB_RATE(2016000000, 1, 9, 9), 184 RK3399_CPUB_RATE(2000000000, 1, 9, 9), 185 RK3399_CPUB_RATE(1992000000, 1, 9, 9), 186 RK3399_CPUB_RATE(1896000000, 1, 9, 9), 187 RK3399_CPUB_RATE(1800000000, 1, 8, 8), 188 RK3399_CPUB_RATE(1704000000, 1, 8, 8), 189 RK3399_CPUB_RATE(1608000000, 1, 7, 7), 190 RK3399_CPUB_RATE(1512000000, 1, 7, 7), 191 RK3399_CPUB_RATE(1488000000, 1, 6, 6), 192 RK3399_CPUB_RATE(1416000000, 1, 6, 6), 193 RK3399_CPUB_RATE(1200000000, 1, 5, 5), 194 RK3399_CPUB_RATE(1008000000, 1, 5, 5), 195 RK3399_CPUB_RATE( 816000000, 1, 4, 4), 196 RK3399_CPUB_RATE( 696000000, 1, 3, 3), 197 RK3399_CPUB_RATE( 600000000, 1, 3, 3), 198 RK3399_CPUB_RATE( 408000000, 1, 2, 2), 199 RK3399_CPUB_RATE( 312000000, 1, 1, 1), 200 RK3399_CPUB_RATE( 216000000, 1, 1, 1), 201 RK3399_CPUB_RATE( 96000000, 1, 1, 1), 202 }; 203 204 #define PLL_CON0 0x00 205 #define PLL_FBDIV __BITS(11,0) 206 207 #define PLL_CON1 0x04 208 #define PLL_POSTDIV2 __BITS(14,12) 209 #define PLL_POSTDIV1 __BITS(10,8) 210 #define PLL_REFDIV __BITS(5,0) 211 212 #define PLL_CON2 0x08 213 #define PLL_LOCK __BIT(31) 214 #define PLL_FRACDIV __BITS(23,0) 215 216 #define PLL_CON3 0x0c 217 #define PLL_WORK_MODE __BITS(9,8) 218 #define PLL_WORK_MODE_SLOW 0 219 #define PLL_WORK_MODE_NORMAL 1 220 #define PLL_WORK_MODE_DEEP_SLOW 2 221 #define PLL_DSMPD __BIT(3) 222 223 #define PLL_WRITE_MASK 0xffff0000 224 225 static u_int 226 rk3399_cru_pll_get_rate(struct rk_cru_softc *sc, 227 struct rk_cru_clk *clk) 228 { 229 struct rk_cru_pll *pll = &clk->u.pll; 230 struct clk *clkp, *clkp_parent; 231 u_int foutvco, foutpostdiv; 232 233 KASSERT(clk->type == RK_CRU_PLL); 234 235 clkp = &clk->base; 236 clkp_parent = clk_get_parent(clkp); 237 if (clkp_parent == NULL) 238 return 0; 239 240 const u_int fref = clk_get_rate(clkp_parent); 241 if (fref == 0) 242 return 0; 243 244 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); 245 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1); 246 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2); 247 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3); 248 249 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); 250 const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2); 251 const u_int postdiv1 = __SHIFTOUT(con1, PLL_POSTDIV1); 252 const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV); 253 const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV); 254 const u_int dsmpd = __SHIFTOUT(con3, PLL_DSMPD); 255 256 if (dsmpd == 1) { 257 /* integer mode */ 258 foutvco = fref / refdiv * fbdiv; 259 } else { 260 /* fractional mode */ 261 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24); 262 } 263 foutpostdiv = foutvco / postdiv1 / postdiv2; 264 265 return foutpostdiv; 266 } 267 268 static int 269 rk3399_cru_pll_set_rate(struct rk_cru_softc *sc, 270 struct rk_cru_clk *clk, u_int rate) 271 { 272 struct rk_cru_pll *pll = &clk->u.pll; 273 const struct rk_cru_pll_rate *pll_rate = NULL; 274 uint32_t val; 275 int retry, best_diff; 276 277 KASSERT(clk->type == RK_CRU_PLL); 278 279 if (pll->rates == NULL || rate == 0) 280 return EIO; 281 282 best_diff = INT_MAX; 283 for (int i = 0; i < pll->nrates; i++) { 284 int diff; 285 286 if (rate > pll->rates[i].rate) 287 diff = rate - pll->rates[i].rate; 288 else 289 diff = pll->rates[i].rate - rate; 290 if (diff < best_diff) { 291 pll_rate = &pll->rates[i]; 292 best_diff = diff; 293 } 294 } 295 296 val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 297 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 298 299 CRU_WRITE(sc, pll->con_base + PLL_CON0, 300 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | (PLL_FBDIV << 16)); 301 302 CRU_WRITE(sc, pll->con_base + PLL_CON1, 303 __SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) | 304 __SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) | 305 __SHIFTIN(pll_rate->refdiv, PLL_REFDIV) | 306 ((PLL_POSTDIV2 | PLL_POSTDIV1 | PLL_REFDIV) << 16)); 307 308 val = CRU_READ(sc, pll->con_base + PLL_CON2); 309 val &= ~PLL_FRACDIV; 310 val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV); 311 CRU_WRITE(sc, pll->con_base + PLL_CON2, val); 312 313 val = __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) | (PLL_DSMPD << 16); 314 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 315 316 for (retry = 1000; retry > 0; retry--) { 317 if (CRU_READ(sc, pll->con_base + PLL_CON2) & pll->lock_mask) 318 break; 319 delay(1); 320 } 321 322 if (retry == 0) 323 device_printf(sc->sc_dev, "WARNING: %s failed to lock\n", 324 clk->base.name); 325 326 /* Set PLL work mode to normal */ 327 val = __SHIFTIN(PLL_WORK_MODE_NORMAL, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 328 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 329 330 return 0; 331 } 332 333 #define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \ 334 { \ 335 .id = (_id), \ 336 .type = RK_CRU_PLL, \ 337 .base.name = (_name), \ 338 .base.flags = 0, \ 339 .u.pll.parents = (_parents), \ 340 .u.pll.nparents = __arraycount(_parents), \ 341 .u.pll.con_base = (_con_base), \ 342 .u.pll.mode_reg = (_mode_reg), \ 343 .u.pll.mode_mask = (_mode_mask), \ 344 .u.pll.lock_mask = (_lock_mask), \ 345 .u.pll.rates = (_rates), \ 346 .u.pll.nrates = __arraycount(_rates), \ 347 .get_rate = rk3399_cru_pll_get_rate, \ 348 .set_rate = rk3399_cru_pll_set_rate, \ 349 .get_parent = rk_cru_pll_get_parent, \ 350 } 351 352 static const char * pll_parents[] = { "xin24m", "xin32k" }; 353 static const char * armclkl_parents[] = { "clk_core_l_lpll_src", "clk_core_l_bpll_src", "clk_core_l_dpll_src", "clk_core_l_gpll_src" }; 354 static const char * armclkb_parents[] = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" }; 355 static const char * mux_clk_tsadc_parents[] = { "xin24m", "xin32k" }; 356 static const char * mux_pll_src_cpll_gpll_parents[] = { "cpll", "gpll" }; 357 static const char * mux_pll_src_cpll_gpll_npll_parents[] = { "cpll", "gpll", "npll" }; 358 static const char * mux_pll_src_cpll_gpll_ppll_parents[] = { "cpll", "gpll", "ppll" }; 359 static const char * mux_pll_src_cpll_gpll_upll_parents[] = { "cpll", "gpll", "upll" }; 360 static const char * mux_pll_src_cpll_gpll_npll_24m_parents[] = { "cpll", "gpll", "npll", "xin24m" }; 361 static const char * mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents[] = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; 362 static const char * mux_pll_src_npll_cpll_gpll_parents[] = { "npll", "cpll", "gpll" }; 363 static const char * mux_pll_src_vpll_cpll_gpll_parents[] = { "vpll", "cpll", "gpll" }; 364 static const char * mux_pll_src_vpll_cpll_gpll_npll_parents[] = { "vpll", "cpll", "gpll", "npll" }; 365 static const char * mux_aclk_perilp0_parents[] = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" }; 366 static const char * mux_hclk_perilp1_parents[] = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" }; 367 static const char * mux_aclk_perihp_parents[] = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" }; 368 static const char * mux_aclk_cci_parents[] = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "vpll_aclk_cci_src" }; 369 static const char * mux_dclk_vop0_parents[] = { "dclk_vop0_div", "dclk_vop0_frac" }; 370 static const char * mux_dclk_vop1_parents[] = { "dclk_vop1_div", "dclk_vop1_frac" }; 371 static const char * mux_i2s0_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "clkin_i2s", "xin12m" }; 372 static const char * mux_i2s1_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s", "xin12m" }; 373 static const char * mux_i2s2_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s", "xin12m" }; 374 static const char * mux_i2sch_parents[] = { "clk_i2s0", "clk_i2s1", "clk_i2s2" }; 375 static const char * mux_i2sout_parents[] = { "clk_i2sout_src", "xin12m" }; 376 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 377 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 378 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 379 static const char * mux_uart3_parents[] = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 380 static const char * mux_rmii_parents[] = { "clk_gmac", "clkin_gmac" }; 381 static const char * mux_aclk_gmac_parents[] = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" }; 382 static const char * mux_aclk_emmc_parents[] = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" }; 383 static const char * mux_pll_src_24m_pciephy_parents[] = { "xin24m", "clk_pciephy_ref100m" }; 384 static const char * mux_pciecore_cru_phy_parents[] = { "clk_pcie_core_cru", "clk_pcie_core_phy" }; 385 386 static struct rk_cru_clk rk3399_cru_clks[] = { 387 RK3399_PLL(RK3399_PLL_APLLL, "lpll", pll_parents, 388 PLL_CON(0), /* con_base */ 389 PLL_CON(3), /* mode_reg */ 390 __BIT(8), /* mode_mask */ 391 __BIT(31), /* lock_mask */ 392 pll_rates), 393 RK3399_PLL(RK3399_PLL_APLLB, "bpll", pll_parents, 394 PLL_CON(8), /* con_base */ 395 PLL_CON(11), /* mode_reg */ 396 __BIT(8), /* mode_mask */ 397 __BIT(31), /* lock_mask */ 398 pll_rates), 399 RK3399_PLL(RK3399_PLL_DPLL, "dpll", pll_parents, 400 PLL_CON(16), /* con_base */ 401 PLL_CON(19), /* mode_reg */ 402 __BIT(8), /* mode_mask */ 403 __BIT(31), /* lock_mask */ 404 pll_norates), 405 RK3399_PLL(RK3399_PLL_CPLL, "cpll", pll_parents, 406 PLL_CON(24), /* con_base */ 407 PLL_CON(27), /* mode_reg */ 408 __BIT(8), /* mode_mask */ 409 __BIT(31), /* lock_mask */ 410 pll_rates), 411 RK3399_PLL(RK3399_PLL_GPLL, "gpll", pll_parents, 412 PLL_CON(32), /* con_base */ 413 PLL_CON(35), /* mode_reg */ 414 __BIT(8), /* mode_mask */ 415 __BIT(31), /* lock_mask */ 416 pll_rates), 417 RK3399_PLL(RK3399_PLL_NPLL, "npll", pll_parents, 418 PLL_CON(40), /* con_base */ 419 PLL_CON(43), /* mode_reg */ 420 __BIT(8), /* mode_mask */ 421 __BIT(31), /* lock_mask */ 422 pll_rates), 423 RK3399_PLL(RK3399_PLL_VPLL, "vpll", pll_parents, 424 PLL_CON(48), /* con_base */ 425 PLL_CON(51), /* mode_reg */ 426 __BIT(8), /* mode_mask */ 427 __BIT(31), /* lock_mask */ 428 pll_rates), 429 430 RK_GATE(0, "clk_core_l_lpll_src", "lpll", CLKGATE_CON(0), 0), 431 RK_GATE(0, "clk_core_l_bpll_src", "bpll", CLKGATE_CON(0), 1), 432 RK_GATE(0, "clk_core_l_dpll_src", "dpll", CLKGATE_CON(0), 2), 433 RK_GATE(0, "clk_core_l_gpll_src", "gpll", CLKGATE_CON(0), 3), 434 435 RK_CPU(RK3399_ARMCLKL, "armclkl", armclkl_parents, 436 CLKSEL_CON(0), /* reg */ 437 __BITS(7,6), 0, 3, /* mux_mask, mux_main, mux_alt */ 438 __BITS(4,0), /* div_mask */ 439 armclkl_rates), 440 441 RK_GATE(0, "clk_core_b_lpll_src", "lpll", CLKGATE_CON(1), 0), 442 RK_GATE(0, "clk_core_b_bpll_src", "bpll", CLKGATE_CON(1), 1), 443 RK_GATE(0, "clk_core_b_dpll_src", "dpll", CLKGATE_CON(1), 2), 444 RK_GATE(0, "clk_core_b_gpll_src", "gpll", CLKGATE_CON(1), 3), 445 446 RK_CPU(RK3399_ARMCLKB, "armclkb", armclkb_parents, 447 CLKSEL_CON(2), /* reg */ 448 __BITS(7,6), 1, 3, /* mux_mask, mux_main, mux_alt */ 449 __BITS(4,0), /* div_mask */ 450 armclkb_rates), 451 452 /* 453 * perilp0 454 */ 455 RK_GATE(0, "gpll_aclk_perilp0_src", "gpll", CLKGATE_CON(7), 0), 456 RK_GATE(0, "cpll_aclk_perilp0_src", "cpll", CLKGATE_CON(7), 1), 457 RK_COMPOSITE(RK3399_ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_parents, 458 CLKSEL_CON(23), /* muxdiv_reg */ 459 __BIT(7), /* mux_mask */ 460 __BITS(4,0), /* div_mask */ 461 CLKGATE_CON(7), /* gate_reg */ 462 __BIT(2), /* gate_mask */ 463 0), 464 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", 465 CLKSEL_CON(23), /* div_reg */ 466 __BITS(10,8), /* div_mask */ 467 CLKGATE_CON(7), /* gate_reg */ 468 __BIT(3), /* gate_mask */ 469 0), 470 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 471 CLKSEL_CON(23), /* div_reg */ 472 __BITS(14,12), /* div_mask */ 473 CLKGATE_CON(7), /* gate_reg */ 474 __BIT(4), /* gate_mask */ 475 0), 476 477 /* 478 * perilp1 479 */ 480 RK_GATE(0, "gpll_hclk_perilp1_src", "gpll", CLKGATE_CON(8), 0), 481 RK_GATE(0, "cpll_hclk_perilp1_src", "cpll", CLKGATE_CON(8), 1), 482 RK_COMPOSITE_NOGATE(RK3399_HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_parents, 483 CLKSEL_CON(25), /* muxdiv_reg */ 484 __BITS(10,8), /* mux_mask */ 485 __BITS(4,0), /* div_mask */ 486 0), 487 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", 488 CLKSEL_CON(25), /* div_reg */ 489 __BITS(10,8), /* div_mask */ 490 CLKGATE_CON(8), /* gate_reg */ 491 __BIT(2), /* gate_mask */ 492 0), 493 494 /* 495 * perihp 496 */ 497 RK_GATE(0, "gpll_aclk_perihp_src", "gpll", CLKGATE_CON(5), 0), 498 RK_GATE(0, "cpll_aclk_perihp_src", "cpll", CLKGATE_CON(5), 1), 499 RK_COMPOSITE(RK3399_ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_parents, 500 CLKSEL_CON(14), /* muxdiv_reg */ 501 __BIT(7), /* mux_mask */ 502 __BITS(4,0), /* div_mask */ 503 CLKGATE_CON(5), /* gate_reg */ 504 __BIT(2), /* gate_mask */ 505 0), 506 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERIHP, "hclk_perihp", "aclk_perihp", 507 CLKSEL_CON(14), /* div_reg */ 508 __BITS(10,8), /* div_mask */ 509 CLKGATE_CON(5), /* gate_reg */ 510 __BIT(3), /* gate_mask */ 511 0), 512 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERIHP, "pclk_perihp", "aclk_perihp", 513 CLKSEL_CON(14), /* div_reg */ 514 __BITS(14,12), /* div_mask */ 515 CLKGATE_CON(5), /* gate_reg */ 516 __BIT(4), /* gate_mask */ 517 0), 518 519 /* 520 * CCI 521 */ 522 RK_GATE(0, "cpll_aclk_cci_src", "cpll", CLKGATE_CON(2), 0), 523 RK_GATE(0, "gpll_aclk_cci_src", "gpll", CLKGATE_CON(2), 1), 524 RK_GATE(0, "npll_aclk_cci_src", "npll", CLKGATE_CON(2), 2), 525 RK_GATE(0, "vpll_aclk_cci_src", "vpll", CLKGATE_CON(2), 3), 526 RK_COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_parents, 527 CLKSEL_CON(5), /* muxdiv_reg */ 528 __BITS(7,6), /* mux_mask */ 529 __BITS(4,0), /* div_mask */ 530 CLKGATE_CON(2), /* gate_reg */ 531 __BIT(4), /* gate_mask */ 532 0), 533 RK_GATE(RK3399_ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLKGATE_CON(15), 2), 534 535 /* 536 * GIC 537 */ 538 RK_COMPOSITE(RK3399_ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_parents, 539 CLKSEL_CON(56), /* muxdiv_reg */ 540 __BIT(15), /* mux_mask */ 541 __BITS(12,8), /* div_mask */ 542 CLKGATE_CON(12), /* gate_reg */ 543 __BIT(12), /* gate_mask */ 544 0), 545 546 /* 547 * DDR 548 */ 549 RK_COMPOSITE(RK3399_PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_parents, 550 CLKSEL_CON(6), /* muxdiv_reg */ 551 __BIT(15), /* mux_mask */ 552 __BITS(12,8), /* div_mask */ 553 CLKGATE_CON(3), /* gate_reg */ 554 __BIT(4), /* gate_mask */ 555 0), 556 557 /* 558 * alive 559 */ 560 RK_DIV(RK3399_PCLK_ALIVE, "pclk_alive", "gpll", CLKSEL_CON(57), __BITS(4,0), 0), 561 562 /* 563 * GPIO 564 */ 565 RK_GATE(RK3399_PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLKGATE_CON(31), 3), 566 RK_GATE(RK3399_PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLKGATE_CON(31), 4), 567 RK_GATE(RK3399_PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLKGATE_CON(31), 5), 568 569 /* 570 * UART 571 */ 572 RK_MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_parents, CLKSEL_CON(33), __BITS(13,12)), 573 RK_MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_parents, CLKSEL_CON(33), __BIT(15)), 574 RK_COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 575 CLKSEL_CON(33), /* div_reg */ 576 __BITS(6,0), /* div_mask */ 577 CLKGATE_CON(9), /* gate_reg */ 578 __BIT(0), /* gate_mask */ 579 0), 580 RK_COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 581 CLKSEL_CON(34), /* div_reg */ 582 __BITS(6,0), /* div_mask */ 583 CLKGATE_CON(9), /* gate_reg */ 584 __BIT(2), /* gate_mask */ 585 0), 586 RK_COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 587 CLKSEL_CON(35), /* div_reg */ 588 __BITS(6,0), /* div_mask */ 589 CLKGATE_CON(9), /* gate_reg */ 590 __BIT(4), /* gate_mask */ 591 0), 592 RK_COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 593 CLKSEL_CON(36), /* div_reg */ 594 __BITS(6,0), /* div_mask */ 595 CLKGATE_CON(9), /* gate_reg */ 596 __BIT(6), /* gate_mask */ 597 0), 598 RK_MUX(RK3399_SCLK_UART0, "clk_uart0", mux_uart0_parents, CLKSEL_CON(33), __BITS(9,8)), 599 RK_MUX(RK3399_SCLK_UART1, "clk_uart1", mux_uart1_parents, CLKSEL_CON(34), __BITS(9,8)), 600 RK_MUX(RK3399_SCLK_UART2, "clk_uart2", mux_uart2_parents, CLKSEL_CON(35), __BITS(9,8)), 601 RK_MUX(RK3399_SCLK_UART3, "clk_uart3", mux_uart3_parents, CLKSEL_CON(36), __BITS(9,8)), 602 RK_GATE(RK3399_PCLK_UART0, "pclk_uart0", "pclk_perilp1", CLKGATE_CON(22), 0), 603 RK_GATE(RK3399_PCLK_UART1, "pclk_uart1", "pclk_perilp1", CLKGATE_CON(22), 1), 604 RK_GATE(RK3399_PCLK_UART2, "pclk_uart2", "pclk_perilp1", CLKGATE_CON(22), 2), 605 RK_GATE(RK3399_PCLK_UART3, "pclk_uart3", "pclk_perilp1", CLKGATE_CON(22), 3), 606 607 /* 608 * SDMMC/SDIO 609 */ 610 RK_COMPOSITE(RK3399_HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_parents, 611 CLKSEL_CON(13), /* muxdiv_reg */ 612 __BIT(15), /* mux_mask */ 613 __BITS(12,8), /* div_mask */ 614 CLKGATE_CON(12), /* gate_reg */ 615 __BIT(13), /* gate_mask */ 616 RK_COMPOSITE_ROUND_DOWN), 617 RK_COMPOSITE(RK3399_SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 618 CLKSEL_CON(15), /* muxdiv_reg */ 619 __BITS(10,8), /* mux_mask */ 620 __BITS(6,0), /* div_mask */ 621 CLKGATE_CON(6), /* gate_reg */ 622 __BIT(0), /* gate_mask */ 623 RK_COMPOSITE_ROUND_DOWN), 624 RK_COMPOSITE(RK3399_SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 625 CLKSEL_CON(16), /* muxdiv_reg */ 626 __BITS(10,8), /* mux_mask */ 627 __BITS(6,0), /* div_mask */ 628 CLKGATE_CON(6), /* gate_reg */ 629 __BIT(1), /* gate_mask */ 630 RK_COMPOSITE_ROUND_DOWN), 631 RK_GATE(RK3399_HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLKGATE_CON(33), 8), 632 RK_GATE(RK3399_HCLK_SDIO, "hclk_sdio", "pclk_perilp1", CLKGATE_CON(34), 4), 633 634 /* 635 * eMMC 636 */ 637 RK_COMPOSITE(RK3399_SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 638 CLKSEL_CON(22), /* muxdiv_reg */ 639 __BITS(10,8), /* mux_mask */ 640 __BITS(6,0), /* div_mask */ 641 CLKGATE_CON(6), /* gate_reg */ 642 __BIT(14), /* gate_mask */ 643 RK_COMPOSITE_ROUND_DOWN), 644 RK_GATE(0, "cpll_aclk_emmc_src", "cpll", CLKGATE_CON(6), 13), 645 RK_GATE(0, "gpll_aclk_emmc_src", "gpll", CLKGATE_CON(6), 12), 646 RK_COMPOSITE_NOGATE(RK3399_ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_parents, 647 CLKSEL_CON(21), /* muxdiv_reg */ 648 __BIT(7), /* mux_mask */ 649 __BITS(4,0), /* div_mask */ 650 0), 651 RK_GATE(RK3399_ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLKGATE_CON(32), 8), 652 RK_GATE(RK3399_ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLKGATE_CON(32), 9), 653 RK_GATE(RK3399_ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLKGATE_CON(32), 10), 654 655 /* 656 * GMAC 657 */ 658 RK_COMPOSITE(RK3399_SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_parents, 659 CLKSEL_CON(20), /* muxdiv_reg */ 660 __BITS(15,14), /* mux_mask */ 661 __BITS(12,8), /* div_mask */ 662 CLKGATE_CON(5), /* gate_reg */ 663 __BIT(5), /* gate_mask */ 664 0), 665 RK_MUX(RK3399_SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_parents, CLKSEL_CON(19), __BIT(4)), 666 RK_GATE(RK3399_SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLKGATE_CON(5), 6), 667 RK_GATE(RK3399_SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLKGATE_CON(5), 7), 668 RK_GATE(RK3399_SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLKGATE_CON(5), 8), 669 RK_GATE(RK3399_SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLKGATE_CON(5), 9), 670 RK_GATE(0, "gpll_aclk_gmac_src", "gpll", CLKGATE_CON(6), 8), 671 RK_GATE(0, "cpll_aclk_gmac_src", "cpll", CLKGATE_CON(6), 9), 672 RK_COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_parents, 673 CLKSEL_CON(20), /* muxdiv_reg */ 674 __BIT(17), /* mux_mask */ 675 __BITS(4,0), /* div_mask */ 676 CLKGATE_CON(6), /* gate_reg */ 677 __BIT(10), /* gate_mask */ 678 0), 679 RK_GATE(RK3399_ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLKGATE_CON(32), 0), 680 RK_COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 681 CLKSEL_CON(19), /* div_reg */ 682 __BITS(10,8), /* div_mask */ 683 CLKGATE_CON(6), /* gate_reg */ 684 __BIT(11), /* gate_mask */ 685 0), 686 RK_GATE(RK3399_PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLKGATE_CON(32), 2), 687 688 /* 689 * USB2 690 */ 691 RK_GATE(RK3399_HCLK_HOST0, "hclk_host0", "hclk_perihp", CLKGATE_CON(20), 5), 692 RK_GATE(RK3399_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLKGATE_CON(20), 6), 693 RK_GATE(RK3399_HCLK_HOST1, "hclk_host1", "hclk_perihp", CLKGATE_CON(20), 7), 694 RK_GATE(RK3399_HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLKGATE_CON(20), 8), 695 RK_GATE(RK3399_SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLKGATE_CON(6), 5), 696 RK_GATE(RK3399_SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLKGATE_CON(6), 6), 697 698 /* 699 * USB3 700 */ 701 RK_GATE(RK3399_SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLKGATE_CON(12), 1), 702 RK_GATE(RK3399_SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLKGATE_CON(12), 2), 703 RK_COMPOSITE(RK3399_SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", pll_parents, 704 CLKSEL_CON(40), /* muxdiv_reg */ 705 __BIT(15), /* mux_mask */ 706 __BITS(9,0), /* div_mask */ 707 CLKGATE_CON(12), /* gate_reg */ 708 __BIT(3), /* gate_mask */ 709 0), 710 RK_COMPOSITE(RK3399_SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", pll_parents, 711 CLKSEL_CON(41), /* muxdiv_reg */ 712 __BIT(15), /* mux_mask */ 713 __BITS(9,0), /* div_mask */ 714 CLKGATE_CON(12), /* gate_reg */ 715 __BIT(4), /* gate_mask */ 716 0), 717 RK_COMPOSITE(RK3399_ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_parents, 718 CLKSEL_CON(39), /* muxdiv_reg */ 719 __BITS(7,6), /* mux_mask */ 720 __BITS(4,0), /* div_mask */ 721 CLKGATE_CON(12), /* gate_reg */ 722 __BIT(0), /* gate_mask */ 723 0), 724 RK_GATE(RK3399_ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLKGATE_CON(30), 1), 725 RK_GATE(RK3399_ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLKGATE_CON(30), 2), 726 RK_GATE(RK3399_ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLKGATE_CON(30), 3), 727 RK_GATE(RK3399_ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLKGATE_CON(30), 4), 728 729 /* 730 * I2C 731 */ 732 RK_COMPOSITE(RK3399_SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_parents, 733 CLKSEL_CON(61), /* muxdiv_reg */ 734 __BIT(7), /* mux_mask */ 735 __BITS(6,0), /* div_mask */ 736 CLKGATE_CON(10), /* gate_reg */ 737 __BIT(0), /* gate_mask */ 738 0), 739 RK_COMPOSITE(RK3399_SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_parents, 740 CLKSEL_CON(62), /* muxdiv_reg */ 741 __BIT(7), /* mux_mask */ 742 __BITS(6,0), /* div_mask */ 743 CLKGATE_CON(10), /* gate_reg */ 744 __BIT(2), /* gate_mask */ 745 0), 746 RK_COMPOSITE(RK3399_SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_parents, 747 CLKSEL_CON(63), /* muxdiv_reg */ 748 __BIT(7), /* mux_mask */ 749 __BITS(6,0), /* div_mask */ 750 CLKGATE_CON(10), /* gate_reg */ 751 __BIT(4), /* gate_mask */ 752 0), 753 RK_COMPOSITE(RK3399_SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_parents, 754 CLKSEL_CON(61), /* muxdiv_reg */ 755 __BIT(15), /* mux_mask */ 756 __BITS(14,8), /* div_mask */ 757 CLKGATE_CON(10), /* gate_reg */ 758 __BIT(1), /* gate_mask */ 759 0), 760 RK_COMPOSITE(RK3399_SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_parents, 761 CLKSEL_CON(62), /* muxdiv_reg */ 762 __BIT(15), /* mux_mask */ 763 __BITS(14,8), /* div_mask */ 764 CLKGATE_CON(10), /* gate_reg */ 765 __BIT(3), /* gate_mask */ 766 0), 767 RK_COMPOSITE(RK3399_SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_parents, 768 CLKSEL_CON(63), /* muxdiv_reg */ 769 __BIT(15), /* mux_mask */ 770 __BITS(14,8), /* div_mask */ 771 CLKGATE_CON(10), /* gate_reg */ 772 __BIT(5), /* gate_mask */ 773 0), 774 RK_GATE(RK3399_PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", CLKGATE_CON(22), 5), 775 RK_GATE(RK3399_PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", CLKGATE_CON(22), 6), 776 RK_GATE(RK3399_PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", CLKGATE_CON(22), 7), 777 RK_GATE(RK3399_PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", CLKGATE_CON(22), 8), 778 RK_GATE(RK3399_PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", CLKGATE_CON(22), 9), 779 RK_GATE(RK3399_PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", CLKGATE_CON(22), 10), 780 781 /* 782 * SPI 783 */ 784 RK_COMPOSITE(RK3399_SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_parents, 785 CLKSEL_CON(59), /* muxdiv_reg */ 786 __BIT(7), /* mux_mask */ 787 __BITS(6,0), /* div_mask */ 788 CLKGATE_CON(9), /* gate_reg */ 789 __BIT(12), /* gate_mask */ 790 0), 791 RK_COMPOSITE(RK3399_SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_parents, 792 CLKSEL_CON(59), /* muxdiv_reg */ 793 __BIT(15), /* mux_mask */ 794 __BITS(14,8), /* div_mask */ 795 CLKGATE_CON(9), /* gate_reg */ 796 __BIT(13), /* gate_mask */ 797 0), 798 RK_COMPOSITE(RK3399_SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_parents, 799 CLKSEL_CON(60), /* muxdiv_reg */ 800 __BIT(7), /* mux_mask */ 801 __BITS(6,0), /* div_mask */ 802 CLKGATE_CON(9), /* gate_reg */ 803 __BIT(14), /* gate_mask */ 804 0), 805 RK_COMPOSITE(RK3399_SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_parents, 806 CLKSEL_CON(60), /* muxdiv_reg */ 807 __BIT(15), /* mux_mask */ 808 __BITS(14,8), /* div_mask */ 809 CLKGATE_CON(9), /* gate_reg */ 810 __BIT(15), /* gate_mask */ 811 0), 812 RK_COMPOSITE(RK3399_SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_parents, 813 CLKSEL_CON(58), /* muxdiv_reg */ 814 __BIT(15), /* mux_mask */ 815 __BITS(14,8), /* div_mask */ 816 CLKGATE_CON(13), /* gate_reg */ 817 __BIT(13), /* gate_mask */ 818 0), 819 RK_GATE(RK3399_PCLK_SPI0, "pclk_rkspi0", "pclk_perilp1", CLKGATE_CON(23), 10), 820 RK_GATE(RK3399_PCLK_SPI1, "pclk_rkspi1", "pclk_perilp1", CLKGATE_CON(23), 11), 821 RK_GATE(RK3399_PCLK_SPI2, "pclk_rkspi2", "pclk_perilp1", CLKGATE_CON(23), 12), 822 RK_GATE(RK3399_PCLK_SPI4, "pclk_rkspi4", "pclk_perilp1", CLKGATE_CON(23), 13), 823 RK_GATE(RK3399_PCLK_SPI5, "pclk_rkspi5", "hclk_perilp1", CLKGATE_CON(34), 5), 824 825 /* Watchdog */ 826 RK_SECURE_GATE(RK3399_PCLK_WDT, "pclk_wdt", "pclk_alive" /*, SECURE_CLKGATE_CON(3), 8 */), 827 828 /* PCIe */ 829 RK_GATE(RK3399_ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLKGATE_CON(20), 2), 830 RK_GATE(RK3399_ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLKGATE_CON(20), 10), 831 RK_GATE(RK3399_PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLKGATE_CON(20), 11), 832 RK_COMPOSITE(RK3399_SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_parents, 833 CLKSEL_CON(17), /* muxdiv_reg */ 834 __BITS(10,8), /* mux_mask */ 835 __BITS(6,0), /* div_mask */ 836 CLKGATE_CON(6), /* gate_reg */ 837 __BIT(2), /* gate_mask */ 838 0), 839 RK_COMPOSITE_NOMUX(RK3399_SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 840 CLKSEL_CON(18), /* div_reg */ 841 __BITS(15,11), /* div_mask */ 842 CLKGATE_CON(12), /* gate_reg */ 843 __BIT(6), /* gate_mask */ 844 0), 845 RK_MUX(RK3399_SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_parents, CLKSEL_CON(18), __BIT(10)), 846 RK_COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_parents, 847 CLKSEL_CON(18), /* muxdiv_reg */ 848 __BITS(9,8), /* mux_mask */ 849 __BITS(6,0), /* div_mask */ 850 CLKGATE_CON(6), /* gate_reg */ 851 __BIT(3), /* gate_mask */ 852 0), 853 RK_MUX(RK3399_SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_parents, CLKSEL_CON(18), __BIT(7)), 854 855 /* Crypto */ 856 RK_COMPOSITE(RK3399_SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_parents, 857 CLKSEL_CON(24), /* muxdiv_reg */ 858 __BITS(7,6), /* mux_mask */ 859 __BITS(4,0), /* div_mask */ 860 CLKGATE_CON(7), /* gate_reg */ 861 __BIT(7), /* gate_mask */ 862 RK_COMPOSITE_ROUND_DOWN /*???*/), 863 RK_COMPOSITE(RK3399_SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_parents, 864 CLKSEL_CON(26), /* muxdiv_reg */ 865 __BITS(7,6), /* mux_mask */ 866 __BITS(4,0), /* div_mask */ 867 CLKGATE_CON(8), /* gate_reg */ 868 __BIT(7), /* gate_mask */ 869 RK_COMPOSITE_ROUND_DOWN /*???*/), 870 RK_GATE(RK3399_HCLK_M_CRYPTO0, "hclk_m_crypto0", "pclk_perilp0", CLKGATE_CON(24), 5), 871 RK_GATE(RK3399_HCLK_S_CRYPTO0, "hclk_s_crypto0", "pclk_perilp0", CLKGATE_CON(24), 6), 872 RK_GATE(RK3399_HCLK_M_CRYPTO1, "hclk_m_crypto1", "pclk_perilp0", CLKGATE_CON(24), 14), 873 RK_GATE(RK3399_HCLK_S_CRYPTO1, "hclk_s_crypto1", "pclk_perilp0", CLKGATE_CON(24), 15), 874 RK_GATE(RK3399_ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "pclk_perilp", CLKGATE_CON(25), 6), 875 876 /* TSADC */ 877 RK_COMPOSITE(RK3399_SCLK_TSADC, "clk_tsadc", mux_clk_tsadc_parents, 878 CLKSEL_CON(27), /* muxdiv_reg */ 879 __BIT(15), /* mux_mask */ 880 __BITS(9,0), /* div_mask */ 881 CLKGATE_CON(9), /* gate_reg */ 882 __BIT(1), /* gate_mask */ 883 RK_COMPOSITE_ROUND_DOWN), 884 RK_GATE(RK3399_PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", CLKGATE_CON(22), 13), 885 886 /* VOP0 */ 887 RK_COMPOSITE(RK3399_ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_parents, 888 CLKSEL_CON(47), /* muxdiv_reg */ 889 __BITS(7,6), /* mux_mask */ 890 __BITS(4,0), /* div_mask */ 891 CLKGATE_CON(10), /* gate_reg */ 892 __BIT(8), /* gate_mask */ 893 0), 894 RK_COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 895 CLKSEL_CON(47), /* div_reg */ 896 __BITS(12,8), /* div_mask */ 897 CLKGATE_CON(10), /* gate_reg */ 898 __BIT(9), /* gate_mask */ 899 0), 900 RK_COMPOSITE(RK3399_DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_parents, 901 CLKSEL_CON(49), /* muxdiv_reg */ 902 __BITS(9,8), /* mux_mask */ 903 __BITS(7,0), /* div_mask */ 904 CLKGATE_CON(10), /* gate_reg */ 905 __BIT(12), /* gate_mask */ 906 RK_COMPOSITE_SET_RATE_PARENT), 907 RK_GATE(RK3399_ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLKGATE_CON(28), 3), 908 RK_GATE(RK3399_HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLKGATE_CON(28), 2), 909 RK_COMPOSITE_FRAC(RK3399_DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 910 CLKSEL_CON(106), /* frac_reg */ 911 0), 912 RK_MUX(RK3399_DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_parents, CLKSEL_CON(49), __BIT(11)), 913 914 /* VOP1 */ 915 RK_COMPOSITE(RK3399_ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_parents, 916 CLKSEL_CON(48), /* muxdiv_reg */ 917 __BITS(7,6), /* mux_mask */ 918 __BITS(4,0), /* div_mask */ 919 CLKGATE_CON(10), /* gate_reg */ 920 __BIT(10), /* gate_mask */ 921 0), 922 RK_COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 923 CLKSEL_CON(48), /* div_reg */ 924 __BITS(12,8), /* div_mask */ 925 CLKGATE_CON(10), /* gate_reg */ 926 __BIT(11), /* gate_mask */ 927 0), 928 RK_COMPOSITE(RK3399_DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_parents, 929 CLKSEL_CON(50), /* muxdiv_reg */ 930 __BITS(9,8), /* mux_mask */ 931 __BITS(7,0), /* div_mask */ 932 CLKGATE_CON(10), /* gate_reg */ 933 __BIT(13), /* gate_mask */ 934 RK_COMPOSITE_SET_RATE_PARENT), 935 RK_GATE(RK3399_ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLKGATE_CON(28), 7), 936 RK_GATE(RK3399_HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLKGATE_CON(28), 6), 937 RK_COMPOSITE_FRAC(RK3399_DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 938 CLKSEL_CON(107), /* frac_reg */ 939 0), 940 RK_MUX(RK3399_DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_parents, CLKSEL_CON(50), __BIT(11)), 941 942 /* VIO */ 943 RK_COMPOSITE(RK3399_ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_parents, 944 CLKSEL_CON(42), /* muxdiv_reg */ 945 __BITS(7,6), /* mux_mask */ 946 __BITS(4,0), /* div_mask */ 947 CLKGATE_CON(11), /* gate_reg */ 948 __BIT(0), /* gate_mask */ 949 0), 950 RK_COMPOSITE_NOMUX(RK3399_PCLK_VIO, "pclk_vio", "aclk_vio", 951 CLKSEL_CON(43), /* div_reg */ 952 __BITS(4,0), /* div_mask */ 953 CLKGATE_CON(11), /* gate_reg */ 954 __BIT(1), /* gate_mask */ 955 0), 956 RK_GATE(RK3399_PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLKGATE_CON(29), 12), 957 958 /* HDMI */ 959 RK_COMPOSITE(RK3399_ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_parents, 960 CLKSEL_CON(42), /* muxdiv_reg */ 961 __BITS(15,14), /* mux_mask */ 962 __BITS(12,8), /* div_mask */ 963 CLKGATE_CON(11), /* gate_reg */ 964 __BIT(12), /* gate_mask */ 965 0), 966 RK_COMPOSITE_NOMUX(RK3399_PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 967 CLKSEL_CON(43), /* div_reg */ 968 __BITS(14,10), /* div_mask */ 969 CLKGATE_CON(11), /* gate_reg */ 970 __BIT(10), /* gate_mask */ 971 0), 972 RK_COMPOSITE(RK3399_SCLK_HDMI_CEC, "clk_hdmi_cec", pll_parents, 973 CLKSEL_CON(45), /* muxdiv_reg */ 974 __BIT(15), /* mux_mask */ 975 __BITS(9,0), /* div_mask */ 976 CLKGATE_CON(11), /* gate_reg */ 977 __BIT(7), /* gate_mask */ 978 0), 979 RK_GATE(RK3399_PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLKGATE_CON(29), 6), 980 RK_GATE(RK3399_SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLKGATE_CON(11), 6), 981 982 /* I2S2 */ 983 RK_COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_parents, 984 CLKSEL_CON(28), /* muxdiv_reg */ 985 __BIT(7), /* mux_mask */ 986 __BITS(6,0), /* div_mask */ 987 CLKGATE_CON(8), /* gate_reg */ 988 __BIT(3), /* gate_mask */ 989 0), 990 RK_COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_parents, 991 CLKSEL_CON(29), /* muxdiv_reg */ 992 __BIT(7), /* mux_mask */ 993 __BITS(6,0), /* div_mask */ 994 CLKGATE_CON(8), /* gate_reg */ 995 __BIT(6), /* gate_mask */ 996 0), 997 RK_COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_parents, 998 CLKSEL_CON(30), /* muxdiv_reg */ 999 __BIT(7), /* mux_mask */ 1000 __BITS(6,0), /* div_mask */ 1001 CLKGATE_CON(8), /* gate_reg */ 1002 __BIT(9), /* gate_mask */ 1003 0), 1004 RK_COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div", 1005 CLKSEL_CON(96), /* frac_reg */ 1006 0), 1007 RK_COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div", 1008 CLKSEL_CON(97), /* frac_reg */ 1009 0), 1010 RK_COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div", 1011 CLKSEL_CON(98), /* frac_reg */ 1012 0), 1013 RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(28), __BITS(9,8)), 1014 RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(29), __BITS(9,8)), 1015 RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(30), __BITS(9,8)), 1016 RK_GATE(RK3399_SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(8), 5), 1017 RK_GATE(RK3399_SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(8), 8), 1018 RK_GATE(RK3399_SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(8), 11), 1019 RK_GATE(RK3399_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLKGATE_CON(34), 0), 1020 RK_GATE(RK3399_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLKGATE_CON(34), 1), 1021 RK_GATE(RK3399_HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLKGATE_CON(34), 2), 1022 RK_MUX(0, "clk_i2sout_src", mux_i2sch_parents, CLKSEL_CON(31), __BITS(1,0)), 1023 RK_COMPOSITE(RK3399_SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_parents, 1024 CLKSEL_CON(31), /* muxdiv_reg */ 1025 __BIT(2), /* mux_mask */ 1026 0, /* div_mask */ 1027 CLKGATE_CON(8), /* gate_reg */ 1028 __BIT(12), /* gate_mask */ 1029 RK_COMPOSITE_SET_RATE_PARENT), 1030 1031 /* eDP */ 1032 RK_COMPOSITE(RK3399_PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_parents, 1033 CLKSEL_CON(44), /* muxdiv_reg */ 1034 __BIT(15), /* mux_mask */ 1035 __BITS(13,8), /* div_mask */ 1036 CLKGATE_CON(11), /* gate_reg */ 1037 __BIT(11), /* gate_mask */ 1038 0), 1039 RK_GATE(RK3399_PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLKGATE_CON(32), 12), 1040 RK_GATE(RK3399_PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLKGATE_CON(32), 13), 1041 1042 RK_COMPOSITE(RK3399_SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_parents, 1043 CLKSEL_CON(46), /* muxdiv_reg */ 1044 __BITS(7,6), /* mux_mask */ 1045 __BITS(4,0), /* div_mask */ 1046 CLKGATE_CON(11), /* gate_reg */ 1047 __BIT(8), /* gate_mask */ 1048 0), 1049 RK_GATE(RK3399_PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLKGATE_CON(29), 7), 1050 1051 }; 1052 1053 static const struct rk3399_init_param { 1054 const char *clk; 1055 const char *parent; 1056 } rk3399_init_params[] = { 1057 { .clk = "clk_i2s0_mux", .parent = "clk_i2s0_frac" }, 1058 { .clk = "clk_i2s1_mux", .parent = "clk_i2s1_frac" }, 1059 { .clk = "clk_i2s2_mux", .parent = "clk_i2s2_frac" }, 1060 { .clk = "dclk_vop0_div", .parent = "gpll" }, 1061 { .clk = "dclk_vop1_div", .parent = "gpll" }, 1062 { .clk = "dclk_vop0", .parent = "dclk_vop0_frac" }, 1063 { .clk = "dclk_vop1", .parent = "dclk_vop1_frac" }, 1064 }; 1065 1066 static void 1067 rk3399_cru_init(struct rk_cru_softc *sc) 1068 { 1069 struct rk_cru_clk *clk, *pclk; 1070 uint32_t write_mask, write_val; 1071 int error; 1072 u_int n; 1073 1074 /* 1075 * Force an update of BPLL to bring it out of slow mode. 1076 */ 1077 clk = rk_cru_clock_find(sc, "armclkb"); 1078 clk_set_rate(&clk->base, clk_get_rate(&clk->base)); 1079 1080 /* 1081 * Set DCLK_VOP0 and DCLK_VOP1 dividers to 1. 1082 */ 1083 write_mask = __BITS(7,0) << 16; 1084 write_val = 0; 1085 CRU_WRITE(sc, CLKSEL_CON(49), write_mask | write_val); 1086 CRU_WRITE(sc, CLKSEL_CON(50), write_mask | write_val); 1087 1088 /* 1089 * Set defaults 1090 */ 1091 for (n = 0; n < __arraycount(rk3399_init_params); n++) { 1092 const struct rk3399_init_param *param = &rk3399_init_params[n]; 1093 clk = rk_cru_clock_find(sc, param->clk); 1094 KASSERTMSG(clk != NULL, "couldn't find clock %s", param->clk); 1095 if (param->parent != NULL) { 1096 pclk = rk_cru_clock_find(sc, param->parent); 1097 KASSERTMSG(pclk != NULL, "couldn't find clock %s", param->parent); 1098 error = clk_set_parent(&clk->base, &pclk->base); 1099 if (error != 0) { 1100 aprint_error_dev(sc->sc_dev, "couldn't set %s parent to %s: %d\n", 1101 param->clk, param->parent, error); 1102 continue; 1103 } 1104 } 1105 } 1106 } 1107 1108 static int 1109 rk3399_cru_match(device_t parent, cfdata_t cf, void *aux) 1110 { 1111 struct fdt_attach_args * const faa = aux; 1112 1113 return of_compatible_match(faa->faa_phandle, compat_data); 1114 } 1115 1116 static void 1117 rk3399_cru_attach(device_t parent, device_t self, void *aux) 1118 { 1119 struct rk_cru_softc * const sc = device_private(self); 1120 struct fdt_attach_args * const faa = aux; 1121 1122 sc->sc_dev = self; 1123 sc->sc_phandle = faa->faa_phandle; 1124 sc->sc_bst = faa->faa_bst; 1125 1126 sc->sc_clks = rk3399_cru_clks; 1127 sc->sc_nclks = __arraycount(rk3399_cru_clks); 1128 1129 sc->sc_softrst_base = SOFTRST_CON(0); 1130 1131 if (rk_cru_attach(sc) != 0) 1132 return; 1133 1134 aprint_naive("\n"); 1135 aprint_normal(": RK3399 CRU\n"); 1136 1137 rk3399_cru_init(sc); 1138 1139 rk_cru_print(sc); 1140 } 1141
Indexes created Fri Oct 03 02:09:57 GMT 2025