rk3399_cru.c revision 1.26
1 /* $NetBSD: rk3399_cru.c,v 1.26 2025/06/03 19:10:26 rjs Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.26 2025/06/03 19:10:26 rjs Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/rockchip/rk_cru.h> 41 #include <arm/rockchip/rk3399_cru.h> 42 43 #define PLL_CON(n) (0x0000 + (n) * 4) 44 #define CLKSEL_CON(n) (0x0100 + (n) * 4) 45 #define CLKGATE_CON(n) (0x0300 + (n) * 4) 46 #define SOFTRST_CON(n) (0x0400 + (n) * 4) 47 48 static int rk3399_cru_match(device_t, cfdata_t, void *); 49 static void rk3399_cru_attach(device_t, device_t, void *); 50 51 static const struct device_compatible_entry compat_data[] = { 52 { .compat = "rockchip,rk3399-cru" }, 53 DEVICE_COMPAT_EOL 54 }; 55 56 CFATTACH_DECL_NEW(rk3399_cru, sizeof(struct rk_cru_softc), 57 rk3399_cru_match, rk3399_cru_attach, NULL, NULL); 58 59 static const struct rk_cru_pll_rate pll_rates[] = { 60 RK_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 61 RK_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 62 RK_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 63 RK_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), 64 RK_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), 65 RK_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 66 RK_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 67 RK_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 68 RK_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 69 RK_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 70 RK_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), 71 RK_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), 72 RK_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 73 RK_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 74 RK_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), 75 RK_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), 76 RK_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), 77 RK_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 78 RK_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), 79 RK_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), 80 RK_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), 81 RK_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 82 RK_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), 83 RK_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), 84 RK_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), 85 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 86 RK_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 87 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 88 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 89 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 90 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 91 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 92 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 93 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 94 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 95 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 96 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 97 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 98 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 99 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 100 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 101 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 102 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 103 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 104 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 105 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 106 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 107 RK_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), 108 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 109 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 110 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 111 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 112 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 113 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 114 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 115 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 116 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 117 RK_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), 118 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 119 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 120 RK_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 121 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 122 RK_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), 123 RK_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), 124 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 125 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 126 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 127 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 128 RK_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), 129 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 130 RK_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), 131 RK_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), 132 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 133 RK_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), 134 RK_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), 135 RK_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), 136 RK_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), 137 }; 138 139 static const struct rk_cru_pll_rate pll_norates[] = { 140 }; 141 142 #define RK3399_ACLKM_MASK __BITS(12,8) 143 #define RK3399_ATCLK_MASK __BITS(4,0) 144 #define RK3399_PDBG_MASK __BITS(12,8) 145 146 #define RK3399_CPU_RATE(_rate, _reg0, _reg0_mask, _reg0_val, _reg1, _reg1_mask, _reg1_val)\ 147 { \ 148 .rate = (_rate), \ 149 .divs[0] = { .reg = (_reg0), .mask = (_reg0_mask), .val = (_reg0_val) },\ 150 .divs[1] = { .reg = (_reg1), .mask = (_reg1_mask), .val = (_reg1_val) },\ 151 } 152 153 #define RK3399_CPUL_RATE(_rate, _aclkm, _atclk, _pdbg) \ 154 RK3399_CPU_RATE(_rate, \ 155 CLKSEL_CON(0), RK3399_ACLKM_MASK, \ 156 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \ 157 CLKSEL_CON(1), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \ 158 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK)) 159 160 #define RK3399_CPUB_RATE(_rate, _aclkm, _atclk, _pdbg) \ 161 RK3399_CPU_RATE(_rate, \ 162 CLKSEL_CON(2), RK3399_ACLKM_MASK, \ 163 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \ 164 CLKSEL_CON(3), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \ 165 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK)) 166 167 static const struct rk_cru_cpu_rate armclkl_rates[] = { 168 RK3399_CPUL_RATE(1800000000, 1, 8, 8), 169 RK3399_CPUL_RATE(1704000000, 1, 8, 8), 170 RK3399_CPUL_RATE(1608000000, 1, 7, 7), 171 RK3399_CPUL_RATE(1512000000, 1, 7, 7), 172 RK3399_CPUL_RATE(1488000000, 1, 6, 6), 173 RK3399_CPUL_RATE(1416000000, 1, 6, 6), 174 RK3399_CPUL_RATE(1200000000, 1, 5, 5), 175 RK3399_CPUL_RATE(1008000000, 1, 5, 5), 176 RK3399_CPUL_RATE( 816000000, 1, 4, 4), 177 RK3399_CPUL_RATE( 696000000, 1, 3, 3), 178 RK3399_CPUL_RATE( 600000000, 1, 3, 3), 179 RK3399_CPUL_RATE( 408000000, 1, 2, 2), 180 RK3399_CPUL_RATE( 312000000, 1, 1, 1), 181 RK3399_CPUL_RATE( 216000000, 1, 1, 1), 182 RK3399_CPUL_RATE( 96000000, 1, 1, 1), 183 }; 184 185 static const struct rk_cru_cpu_rate armclkb_rates[] = { 186 RK3399_CPUB_RATE(2208000000, 1, 11, 11), 187 RK3399_CPUB_RATE(2184000000, 1, 11, 11), 188 RK3399_CPUB_RATE(2088000000, 1, 10, 10), 189 RK3399_CPUB_RATE(2040000000, 1, 10, 10), 190 RK3399_CPUB_RATE(2016000000, 1, 9, 9), 191 RK3399_CPUB_RATE(2000000000, 1, 9, 9), 192 RK3399_CPUB_RATE(1992000000, 1, 9, 9), 193 RK3399_CPUB_RATE(1896000000, 1, 9, 9), 194 RK3399_CPUB_RATE(1800000000, 1, 8, 8), 195 RK3399_CPUB_RATE(1704000000, 1, 8, 8), 196 RK3399_CPUB_RATE(1608000000, 1, 7, 7), 197 RK3399_CPUB_RATE(1512000000, 1, 7, 7), 198 RK3399_CPUB_RATE(1488000000, 1, 6, 6), 199 RK3399_CPUB_RATE(1416000000, 1, 6, 6), 200 RK3399_CPUB_RATE(1200000000, 1, 5, 5), 201 RK3399_CPUB_RATE(1008000000, 1, 5, 5), 202 RK3399_CPUB_RATE( 816000000, 1, 4, 4), 203 RK3399_CPUB_RATE( 696000000, 1, 3, 3), 204 RK3399_CPUB_RATE( 600000000, 1, 3, 3), 205 RK3399_CPUB_RATE( 408000000, 1, 2, 2), 206 RK3399_CPUB_RATE( 312000000, 1, 1, 1), 207 RK3399_CPUB_RATE( 216000000, 1, 1, 1), 208 RK3399_CPUB_RATE( 96000000, 1, 1, 1), 209 }; 210 211 #define PLL_CON0 0x00 212 #define PLL_FBDIV __BITS(11,0) 213 214 #define PLL_CON1 0x04 215 #define PLL_POSTDIV2 __BITS(14,12) 216 #define PLL_POSTDIV1 __BITS(10,8) 217 #define PLL_REFDIV __BITS(5,0) 218 219 #define PLL_CON2 0x08 220 #define PLL_LOCK __BIT(31) 221 #define PLL_FRACDIV __BITS(23,0) 222 223 #define PLL_CON3 0x0c 224 #define PLL_WORK_MODE __BITS(9,8) 225 #define PLL_WORK_MODE_SLOW 0 226 #define PLL_WORK_MODE_NORMAL 1 227 #define PLL_WORK_MODE_DEEP_SLOW 2 228 #define PLL_DSMPD __BIT(3) 229 230 #define PLL_WRITE_MASK 0xffff0000 231 232 static u_int 233 rk3399_cru_pll_get_rate(struct rk_cru_softc *sc, 234 struct rk_cru_clk *clk) 235 { 236 struct rk_cru_pll *pll = &clk->u.pll; 237 struct clk *clkp, *clkp_parent; 238 u_int foutvco, foutpostdiv; 239 240 KASSERT(clk->type == RK_CRU_PLL); 241 242 clkp = &clk->base; 243 clkp_parent = clk_get_parent(clkp); 244 if (clkp_parent == NULL) 245 return 0; 246 247 const u_int fref = clk_get_rate(clkp_parent); 248 if (fref == 0) 249 return 0; 250 251 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); 252 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1); 253 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2); 254 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3); 255 256 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); 257 const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2); 258 const u_int postdiv1 = __SHIFTOUT(con1, PLL_POSTDIV1); 259 const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV); 260 const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV); 261 const u_int dsmpd = __SHIFTOUT(con3, PLL_DSMPD); 262 263 if (dsmpd == 1) { 264 /* integer mode */ 265 foutvco = fref / refdiv * fbdiv; 266 } else { 267 /* fractional mode */ 268 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24); 269 } 270 foutpostdiv = foutvco / postdiv1 / postdiv2; 271 272 return foutpostdiv; 273 } 274 275 static int 276 rk3399_cru_pll_set_rate(struct rk_cru_softc *sc, 277 struct rk_cru_clk *clk, u_int rate) 278 { 279 struct rk_cru_pll *pll = &clk->u.pll; 280 const struct rk_cru_pll_rate *pll_rate = NULL; 281 uint32_t val; 282 int retry, best_diff; 283 284 KASSERT(clk->type == RK_CRU_PLL); 285 286 if (pll->rates == NULL || rate == 0) 287 return EIO; 288 289 best_diff = INT_MAX; 290 for (int i = 0; i < pll->nrates; i++) { 291 int diff; 292 293 if (rate > pll->rates[i].rate) 294 diff = rate - pll->rates[i].rate; 295 else 296 diff = pll->rates[i].rate - rate; 297 if (diff < best_diff) { 298 pll_rate = &pll->rates[i]; 299 best_diff = diff; 300 } 301 } 302 303 val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 304 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 305 306 CRU_WRITE(sc, pll->con_base + PLL_CON0, 307 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | (PLL_FBDIV << 16)); 308 309 CRU_WRITE(sc, pll->con_base + PLL_CON1, 310 __SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) | 311 __SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) | 312 __SHIFTIN(pll_rate->refdiv, PLL_REFDIV) | 313 ((PLL_POSTDIV2 | PLL_POSTDIV1 | PLL_REFDIV) << 16)); 314 315 val = CRU_READ(sc, pll->con_base + PLL_CON2); 316 val &= ~PLL_FRACDIV; 317 val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV); 318 CRU_WRITE(sc, pll->con_base + PLL_CON2, val); 319 320 val = __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) | (PLL_DSMPD << 16); 321 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 322 323 for (retry = 1000; retry > 0; retry--) { 324 if (CRU_READ(sc, pll->con_base + PLL_CON2) & pll->lock_mask) 325 break; 326 delay(1); 327 } 328 329 if (retry == 0) 330 device_printf(sc->sc_dev, "WARNING: %s failed to lock\n", 331 clk->base.name); 332 333 /* Set PLL work mode to normal */ 334 val = __SHIFTIN(PLL_WORK_MODE_NORMAL, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 335 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 336 337 return 0; 338 } 339 340 #define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \ 341 { \ 342 .id = (_id), \ 343 .type = RK_CRU_PLL, \ 344 .base.name = (_name), \ 345 .base.flags = 0, \ 346 .u.pll.parents = (_parents), \ 347 .u.pll.nparents = __arraycount(_parents), \ 348 .u.pll.con_base = (_con_base), \ 349 .u.pll.mode_reg = (_mode_reg), \ 350 .u.pll.mode_mask = (_mode_mask), \ 351 .u.pll.lock_mask = (_lock_mask), \ 352 .u.pll.rates = (_rates), \ 353 .u.pll.nrates = __arraycount(_rates), \ 354 .get_rate = rk3399_cru_pll_get_rate, \ 355 .set_rate = rk3399_cru_pll_set_rate, \ 356 .get_parent = rk_cru_pll_get_parent, \ 357 } 358 359 static const char * pll_parents[] = { "xin24m", "xin32k" }; 360 static const char * armclkl_parents[] = { "clk_core_l_lpll_src", "clk_core_l_bpll_src", "clk_core_l_dpll_src", "clk_core_l_gpll_src" }; 361 static const char * armclkb_parents[] = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" }; 362 static const char * mux_clk_tsadc_parents[] = { "xin24m", "xin32k" }; 363 static const char * mux_pll_src_cpll_gpll_parents[] = { "cpll", "gpll" }; 364 static const char * mux_pll_src_cpll_gpll_npll_parents[] = { "cpll", "gpll", "npll" }; 365 static const char * mux_pll_src_cpll_gpll_ppll_parents[] = { "cpll", "gpll", "ppll" }; 366 static const char * mux_pll_src_cpll_gpll_upll_parents[] = { "cpll", "gpll", "upll" }; 367 static const char * mux_pll_src_cpll_gpll_npll_24m_parents[] = { "cpll", "gpll", "npll", "xin24m" }; 368 static const char * mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents[] = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; 369 static const char * mux_pll_src_npll_cpll_gpll_parents[] = { "npll", "cpll", "gpll" }; 370 static const char * mux_pll_src_vpll_cpll_gpll_parents[] = { "vpll", "cpll", "gpll" }; 371 static const char * mux_pll_src_vpll_cpll_gpll_npll_parents[] = { "vpll", "cpll", "gpll", "npll" }; 372 static const char * mux_aclk_perilp0_parents[] = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" }; 373 static const char * mux_hclk_perilp1_parents[] = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" }; 374 static const char * mux_aclk_perihp_parents[] = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" }; 375 static const char * mux_aclk_cci_parents[] = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "vpll_aclk_cci_src" }; 376 static const char * mux_dclk_vop0_parents[] = { "dclk_vop0_div", "dclk_vop0_frac" }; 377 static const char * mux_dclk_vop1_parents[] = { "dclk_vop1_div", "dclk_vop1_frac" }; 378 static const char * mux_i2s0_parents[] = { "clk_i2s0_div", "clk_i2s0_frac", "clkin_i2s", "xin12m" }; 379 static const char * mux_i2s1_parents[] = { "clk_i2s1_div", "clk_i2s1_frac", "clkin_i2s", "xin12m" }; 380 static const char * mux_i2s2_parents[] = { "clk_i2s2_div", "clk_i2s2_frac", "clkin_i2s", "xin12m" }; 381 static const char * mux_i2sch_parents[] = { "clk_i2s0", "clk_i2s1", "clk_i2s2" }; 382 static const char * mux_i2sout_parents[] = { "clk_i2sout_src", "xin12m" }; 383 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 384 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 385 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 386 static const char * mux_uart3_parents[] = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 387 static const char * mux_rmii_parents[] = { "clk_gmac", "clkin_gmac" }; 388 static const char * mux_aclk_gmac_parents[] = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" }; 389 static const char * mux_aclk_emmc_parents[] = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" }; 390 static const char * mux_pll_src_24m_pciephy_parents[] = { "xin24m", "clk_pciephy_ref100m" }; 391 static const char * mux_pciecore_cru_phy_parents[] = { "clk_pcie_core_cru", "clk_pcie_core_phy" }; 392 static const char * mux_tcpd_parents[] = { "xin24m", "xin32k", "cpll", "gpll" }; 393 394 static struct rk_cru_clk rk3399_cru_clks[] = { 395 RK3399_PLL(RK3399_PLL_APLLL, "lpll", pll_parents, 396 PLL_CON(0), /* con_base */ 397 PLL_CON(3), /* mode_reg */ 398 __BIT(8), /* mode_mask */ 399 __BIT(31), /* lock_mask */ 400 pll_rates), 401 RK3399_PLL(RK3399_PLL_APLLB, "bpll", pll_parents, 402 PLL_CON(8), /* con_base */ 403 PLL_CON(11), /* mode_reg */ 404 __BIT(8), /* mode_mask */ 405 __BIT(31), /* lock_mask */ 406 pll_rates), 407 RK3399_PLL(RK3399_PLL_DPLL, "dpll", pll_parents, 408 PLL_CON(16), /* con_base */ 409 PLL_CON(19), /* mode_reg */ 410 __BIT(8), /* mode_mask */ 411 __BIT(31), /* lock_mask */ 412 pll_norates), 413 RK3399_PLL(RK3399_PLL_CPLL, "cpll", pll_parents, 414 PLL_CON(24), /* con_base */ 415 PLL_CON(27), /* mode_reg */ 416 __BIT(8), /* mode_mask */ 417 __BIT(31), /* lock_mask */ 418 pll_rates), 419 RK3399_PLL(RK3399_PLL_GPLL, "gpll", pll_parents, 420 PLL_CON(32), /* con_base */ 421 PLL_CON(35), /* mode_reg */ 422 __BIT(8), /* mode_mask */ 423 __BIT(31), /* lock_mask */ 424 pll_rates), 425 RK3399_PLL(RK3399_PLL_NPLL, "npll", pll_parents, 426 PLL_CON(40), /* con_base */ 427 PLL_CON(43), /* mode_reg */ 428 __BIT(8), /* mode_mask */ 429 __BIT(31), /* lock_mask */ 430 pll_rates), 431 RK3399_PLL(RK3399_PLL_VPLL, "vpll", pll_parents, 432 PLL_CON(48), /* con_base */ 433 PLL_CON(51), /* mode_reg */ 434 __BIT(8), /* mode_mask */ 435 __BIT(31), /* lock_mask */ 436 pll_rates), 437 438 RK_GATE(0, "clk_core_l_lpll_src", "lpll", CLKGATE_CON(0), 0), 439 RK_GATE(0, "clk_core_l_bpll_src", "bpll", CLKGATE_CON(0), 1), 440 RK_GATE(0, "clk_core_l_dpll_src", "dpll", CLKGATE_CON(0), 2), 441 RK_GATE(0, "clk_core_l_gpll_src", "gpll", CLKGATE_CON(0), 3), 442 443 RK_CPU(RK3399_ARMCLKL, "armclkl", armclkl_parents, 444 CLKSEL_CON(0), /* mux_reg */ 445 __BITS(7,6), 0, 3, /* mux_mask, mux_main, mux_alt */ 446 CLKSEL_CON(0), /* div_reg */ 447 __BITS(4,0), /* div_mask */ 448 armclkl_rates), 449 450 RK_GATE(0, "clk_core_b_lpll_src", "lpll", CLKGATE_CON(1), 0), 451 RK_GATE(0, "clk_core_b_bpll_src", "bpll", CLKGATE_CON(1), 1), 452 RK_GATE(0, "clk_core_b_dpll_src", "dpll", CLKGATE_CON(1), 2), 453 RK_GATE(0, "clk_core_b_gpll_src", "gpll", CLKGATE_CON(1), 3), 454 455 RK_CPU(RK3399_ARMCLKB, "armclkb", armclkb_parents, 456 CLKSEL_CON(2), /* mux_reg */ 457 __BITS(7,6), 1, 3, /* mux_mask, mux_main, mux_alt */ 458 CLKSEL_CON(2), /* div_reg */ 459 __BITS(4,0), /* div_mask */ 460 armclkb_rates), 461 462 /* 463 * perilp0 464 */ 465 RK_GATE(0, "gpll_aclk_perilp0_src", "gpll", CLKGATE_CON(7), 0), 466 RK_GATE(0, "cpll_aclk_perilp0_src", "cpll", CLKGATE_CON(7), 1), 467 RK_COMPOSITE(RK3399_ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_parents, 468 CLKSEL_CON(23), /* muxdiv_reg */ 469 __BIT(7), /* mux_mask */ 470 __BITS(4,0), /* div_mask */ 471 CLKGATE_CON(7), /* gate_reg */ 472 __BIT(2), /* gate_mask */ 473 0), 474 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", 475 CLKSEL_CON(23), /* div_reg */ 476 __BITS(10,8), /* div_mask */ 477 CLKGATE_CON(7), /* gate_reg */ 478 __BIT(3), /* gate_mask */ 479 0), 480 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 481 CLKSEL_CON(23), /* div_reg */ 482 __BITS(14,12), /* div_mask */ 483 CLKGATE_CON(7), /* gate_reg */ 484 __BIT(4), /* gate_mask */ 485 0), 486 487 /* 488 * perilp1 489 */ 490 RK_GATE(0, "gpll_hclk_perilp1_src", "gpll", CLKGATE_CON(8), 0), 491 RK_GATE(0, "cpll_hclk_perilp1_src", "cpll", CLKGATE_CON(8), 1), 492 RK_COMPOSITE_NOGATE(RK3399_HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_parents, 493 CLKSEL_CON(25), /* muxdiv_reg */ 494 __BITS(10,8), /* mux_mask */ 495 __BITS(4,0), /* div_mask */ 496 0), 497 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", 498 CLKSEL_CON(25), /* div_reg */ 499 __BITS(10,8), /* div_mask */ 500 CLKGATE_CON(8), /* gate_reg */ 501 __BIT(2), /* gate_mask */ 502 0), 503 504 /* 505 * perihp 506 */ 507 RK_GATE(0, "gpll_aclk_perihp_src", "gpll", CLKGATE_CON(5), 0), 508 RK_GATE(0, "cpll_aclk_perihp_src", "cpll", CLKGATE_CON(5), 1), 509 RK_COMPOSITE(RK3399_ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_parents, 510 CLKSEL_CON(14), /* muxdiv_reg */ 511 __BIT(7), /* mux_mask */ 512 __BITS(4,0), /* div_mask */ 513 CLKGATE_CON(5), /* gate_reg */ 514 __BIT(2), /* gate_mask */ 515 0), 516 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERIHP, "hclk_perihp", "aclk_perihp", 517 CLKSEL_CON(14), /* div_reg */ 518 __BITS(10,8), /* div_mask */ 519 CLKGATE_CON(5), /* gate_reg */ 520 __BIT(3), /* gate_mask */ 521 0), 522 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERIHP, "pclk_perihp", "aclk_perihp", 523 CLKSEL_CON(14), /* div_reg */ 524 __BITS(14,12), /* div_mask */ 525 CLKGATE_CON(5), /* gate_reg */ 526 __BIT(4), /* gate_mask */ 527 0), 528 529 /* 530 * CCI 531 */ 532 RK_GATE(0, "cpll_aclk_cci_src", "cpll", CLKGATE_CON(2), 0), 533 RK_GATE(0, "gpll_aclk_cci_src", "gpll", CLKGATE_CON(2), 1), 534 RK_GATE(0, "npll_aclk_cci_src", "npll", CLKGATE_CON(2), 2), 535 RK_GATE(0, "vpll_aclk_cci_src", "vpll", CLKGATE_CON(2), 3), 536 RK_COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_parents, 537 CLKSEL_CON(5), /* muxdiv_reg */ 538 __BITS(7,6), /* mux_mask */ 539 __BITS(4,0), /* div_mask */ 540 CLKGATE_CON(2), /* gate_reg */ 541 __BIT(4), /* gate_mask */ 542 0), 543 RK_GATE(RK3399_ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLKGATE_CON(15), 2), 544 545 /* 546 * GIC 547 */ 548 RK_COMPOSITE(RK3399_ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_parents, 549 CLKSEL_CON(56), /* muxdiv_reg */ 550 __BIT(15), /* mux_mask */ 551 __BITS(12,8), /* div_mask */ 552 CLKGATE_CON(12), /* gate_reg */ 553 __BIT(12), /* gate_mask */ 554 0), 555 556 /* 557 * DDR 558 */ 559 RK_COMPOSITE(RK3399_PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_parents, 560 CLKSEL_CON(6), /* muxdiv_reg */ 561 __BIT(15), /* mux_mask */ 562 __BITS(12,8), /* div_mask */ 563 CLKGATE_CON(3), /* gate_reg */ 564 __BIT(4), /* gate_mask */ 565 0), 566 567 /* 568 * alive 569 */ 570 RK_DIV(RK3399_PCLK_ALIVE, "pclk_alive", "gpll", CLKSEL_CON(57), __BITS(4,0), 0), 571 572 /* 573 * GPIO 574 */ 575 RK_GATE(RK3399_PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLKGATE_CON(31), 3), 576 RK_GATE(RK3399_PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLKGATE_CON(31), 4), 577 RK_GATE(RK3399_PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLKGATE_CON(31), 5), 578 579 /* 580 * UART 581 */ 582 RK_MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_parents, CLKSEL_CON(33), __BITS(13,12)), 583 RK_MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_parents, CLKSEL_CON(33), __BIT(15)), 584 RK_COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 585 CLKSEL_CON(33), /* div_reg */ 586 __BITS(6,0), /* div_mask */ 587 CLKGATE_CON(9), /* gate_reg */ 588 __BIT(0), /* gate_mask */ 589 0), 590 RK_COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 591 CLKSEL_CON(34), /* div_reg */ 592 __BITS(6,0), /* div_mask */ 593 CLKGATE_CON(9), /* gate_reg */ 594 __BIT(2), /* gate_mask */ 595 0), 596 RK_COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 597 CLKSEL_CON(35), /* div_reg */ 598 __BITS(6,0), /* div_mask */ 599 CLKGATE_CON(9), /* gate_reg */ 600 __BIT(4), /* gate_mask */ 601 0), 602 RK_COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 603 CLKSEL_CON(36), /* div_reg */ 604 __BITS(6,0), /* div_mask */ 605 CLKGATE_CON(9), /* gate_reg */ 606 __BIT(6), /* gate_mask */ 607 0), 608 RK_MUX(RK3399_SCLK_UART0, "clk_uart0", mux_uart0_parents, CLKSEL_CON(33), __BITS(9,8)), 609 RK_MUX(RK3399_SCLK_UART1, "clk_uart1", mux_uart1_parents, CLKSEL_CON(34), __BITS(9,8)), 610 RK_MUX(RK3399_SCLK_UART2, "clk_uart2", mux_uart2_parents, CLKSEL_CON(35), __BITS(9,8)), 611 RK_MUX(RK3399_SCLK_UART3, "clk_uart3", mux_uart3_parents, CLKSEL_CON(36), __BITS(9,8)), 612 RK_GATE(RK3399_PCLK_UART0, "pclk_uart0", "pclk_perilp1", CLKGATE_CON(22), 0), 613 RK_GATE(RK3399_PCLK_UART1, "pclk_uart1", "pclk_perilp1", CLKGATE_CON(22), 1), 614 RK_GATE(RK3399_PCLK_UART2, "pclk_uart2", "pclk_perilp1", CLKGATE_CON(22), 2), 615 RK_GATE(RK3399_PCLK_UART3, "pclk_uart3", "pclk_perilp1", CLKGATE_CON(22), 3), 616 617 /* 618 * SDMMC/SDIO 619 */ 620 RK_COMPOSITE(RK3399_HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_parents, 621 CLKSEL_CON(13), /* muxdiv_reg */ 622 __BIT(15), /* mux_mask */ 623 __BITS(12,8), /* div_mask */ 624 CLKGATE_CON(12), /* gate_reg */ 625 __BIT(13), /* gate_mask */ 626 RK_COMPOSITE_ROUND_DOWN), 627 RK_COMPOSITE(RK3399_SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 628 CLKSEL_CON(15), /* muxdiv_reg */ 629 __BITS(10,8), /* mux_mask */ 630 __BITS(6,0), /* div_mask */ 631 CLKGATE_CON(6), /* gate_reg */ 632 __BIT(0), /* gate_mask */ 633 RK_COMPOSITE_ROUND_DOWN), 634 RK_COMPOSITE(RK3399_SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 635 CLKSEL_CON(16), /* muxdiv_reg */ 636 __BITS(10,8), /* mux_mask */ 637 __BITS(6,0), /* div_mask */ 638 CLKGATE_CON(6), /* gate_reg */ 639 __BIT(1), /* gate_mask */ 640 RK_COMPOSITE_ROUND_DOWN), 641 RK_GATE(RK3399_HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLKGATE_CON(33), 8), 642 RK_GATE(RK3399_HCLK_SDIO, "hclk_sdio", "pclk_perilp1", CLKGATE_CON(34), 4), 643 644 /* 645 * eMMC 646 */ 647 RK_COMPOSITE(RK3399_SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 648 CLKSEL_CON(22), /* muxdiv_reg */ 649 __BITS(10,8), /* mux_mask */ 650 __BITS(6,0), /* div_mask */ 651 CLKGATE_CON(6), /* gate_reg */ 652 __BIT(14), /* gate_mask */ 653 RK_COMPOSITE_ROUND_DOWN), 654 RK_GATE(0, "cpll_aclk_emmc_src", "cpll", CLKGATE_CON(6), 13), 655 RK_GATE(0, "gpll_aclk_emmc_src", "gpll", CLKGATE_CON(6), 12), 656 RK_COMPOSITE_NOGATE(RK3399_ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_parents, 657 CLKSEL_CON(21), /* muxdiv_reg */ 658 __BIT(7), /* mux_mask */ 659 __BITS(4,0), /* div_mask */ 660 0), 661 RK_GATE(RK3399_ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLKGATE_CON(32), 8), 662 RK_GATE(RK3399_ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLKGATE_CON(32), 9), 663 RK_GATE(RK3399_ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLKGATE_CON(32), 10), 664 665 /* 666 * GMAC 667 */ 668 RK_COMPOSITE(RK3399_SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_parents, 669 CLKSEL_CON(20), /* muxdiv_reg */ 670 __BITS(15,14), /* mux_mask */ 671 __BITS(12,8), /* div_mask */ 672 CLKGATE_CON(5), /* gate_reg */ 673 __BIT(5), /* gate_mask */ 674 0), 675 RK_MUX(RK3399_SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_parents, CLKSEL_CON(19), __BIT(4)), 676 RK_GATE(RK3399_SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLKGATE_CON(5), 6), 677 RK_GATE(RK3399_SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLKGATE_CON(5), 7), 678 RK_GATE(RK3399_SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLKGATE_CON(5), 8), 679 RK_GATE(RK3399_SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLKGATE_CON(5), 9), 680 RK_GATE(0, "gpll_aclk_gmac_src", "gpll", CLKGATE_CON(6), 8), 681 RK_GATE(0, "cpll_aclk_gmac_src", "cpll", CLKGATE_CON(6), 9), 682 RK_COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_parents, 683 CLKSEL_CON(20), /* muxdiv_reg */ 684 __BIT(17), /* mux_mask */ 685 __BITS(4,0), /* div_mask */ 686 CLKGATE_CON(6), /* gate_reg */ 687 __BIT(10), /* gate_mask */ 688 0), 689 RK_GATE(RK3399_ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLKGATE_CON(32), 0), 690 RK_COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 691 CLKSEL_CON(19), /* div_reg */ 692 __BITS(10,8), /* div_mask */ 693 CLKGATE_CON(6), /* gate_reg */ 694 __BIT(11), /* gate_mask */ 695 0), 696 RK_GATE(RK3399_PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLKGATE_CON(32), 2), 697 698 /* 699 * USB2 700 */ 701 RK_GATE(RK3399_HCLK_HOST0, "hclk_host0", "hclk_perihp", CLKGATE_CON(20), 5), 702 RK_GATE(RK3399_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLKGATE_CON(20), 6), 703 RK_GATE(RK3399_HCLK_HOST1, "hclk_host1", "hclk_perihp", CLKGATE_CON(20), 7), 704 RK_GATE(RK3399_HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLKGATE_CON(20), 8), 705 RK_GATE(RK3399_SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLKGATE_CON(6), 5), 706 RK_GATE(RK3399_SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLKGATE_CON(6), 6), 707 708 /* 709 * USB3 710 */ 711 RK_GATE(RK3399_SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLKGATE_CON(12), 1), 712 RK_GATE(RK3399_SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLKGATE_CON(12), 2), 713 RK_COMPOSITE(RK3399_SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", pll_parents, 714 CLKSEL_CON(40), /* muxdiv_reg */ 715 __BIT(15), /* mux_mask */ 716 __BITS(9,0), /* div_mask */ 717 CLKGATE_CON(12), /* gate_reg */ 718 __BIT(3), /* gate_mask */ 719 0), 720 RK_COMPOSITE(RK3399_SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", pll_parents, 721 CLKSEL_CON(41), /* muxdiv_reg */ 722 __BIT(15), /* mux_mask */ 723 __BITS(9,0), /* div_mask */ 724 CLKGATE_CON(12), /* gate_reg */ 725 __BIT(4), /* gate_mask */ 726 0), 727 RK_COMPOSITE(RK3399_ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_parents, 728 CLKSEL_CON(39), /* muxdiv_reg */ 729 __BITS(7,6), /* mux_mask */ 730 __BITS(4,0), /* div_mask */ 731 CLKGATE_CON(12), /* gate_reg */ 732 __BIT(0), /* gate_mask */ 733 0), 734 RK_GATE(RK3399_ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLKGATE_CON(30), 1), 735 RK_GATE(RK3399_ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLKGATE_CON(30), 2), 736 RK_GATE(RK3399_ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLKGATE_CON(30), 3), 737 RK_GATE(RK3399_ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLKGATE_CON(30), 4), 738 739 /* TYPE-C PHY */ 740 RK_COMPOSITE(RK3399_SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", pll_parents, 741 CLKSEL_CON(64), /* muxdiv_reg */ 742 __BIT(15), /* mux_mask */ 743 __BITS(12,8), /* div_mask */ 744 CLKGATE_CON(13), /* gate_reg */ 745 __BIT(4), /* gate_mask */ 746 0), 747 RK_COMPOSITE(RK3399_SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_tcpd_parents, 748 CLKSEL_CON(64), /* muxdiv_reg */ 749 __BITS(7,6), /* mux_mask */ 750 __BITS(4,0), /* div_mask */ 751 CLKGATE_CON(13), /* gate_reg */ 752 __BIT(5), /* gate_mask */ 753 0), 754 RK_COMPOSITE(RK3399_SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", pll_parents, 755 CLKSEL_CON(65), /* muxdiv_reg */ 756 __BIT(15), /* mux_mask */ 757 __BITS(12,8), /* div_mask */ 758 CLKGATE_CON(13), /* gate_reg */ 759 __BIT(6), /* gate_mask */ 760 0), 761 RK_COMPOSITE(RK3399_SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_tcpd_parents, 762 CLKSEL_CON(65), /* muxdiv_reg */ 763 __BITS(7,6), /* mux_mask */ 764 __BITS(4,0), /* div_mask */ 765 CLKGATE_CON(13), /* gate_reg */ 766 __BIT(7), /* gate_mask */ 767 0), 768 769 /* 770 * I2C 771 */ 772 RK_COMPOSITE(RK3399_SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_parents, 773 CLKSEL_CON(61), /* muxdiv_reg */ 774 __BIT(7), /* mux_mask */ 775 __BITS(6,0), /* div_mask */ 776 CLKGATE_CON(10), /* gate_reg */ 777 __BIT(0), /* gate_mask */ 778 0), 779 RK_COMPOSITE(RK3399_SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_parents, 780 CLKSEL_CON(62), /* muxdiv_reg */ 781 __BIT(7), /* mux_mask */ 782 __BITS(6,0), /* div_mask */ 783 CLKGATE_CON(10), /* gate_reg */ 784 __BIT(2), /* gate_mask */ 785 0), 786 RK_COMPOSITE(RK3399_SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_parents, 787 CLKSEL_CON(63), /* muxdiv_reg */ 788 __BIT(7), /* mux_mask */ 789 __BITS(6,0), /* div_mask */ 790 CLKGATE_CON(10), /* gate_reg */ 791 __BIT(4), /* gate_mask */ 792 0), 793 RK_COMPOSITE(RK3399_SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_parents, 794 CLKSEL_CON(61), /* muxdiv_reg */ 795 __BIT(15), /* mux_mask */ 796 __BITS(14,8), /* div_mask */ 797 CLKGATE_CON(10), /* gate_reg */ 798 __BIT(1), /* gate_mask */ 799 0), 800 RK_COMPOSITE(RK3399_SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_parents, 801 CLKSEL_CON(62), /* muxdiv_reg */ 802 __BIT(15), /* mux_mask */ 803 __BITS(14,8), /* div_mask */ 804 CLKGATE_CON(10), /* gate_reg */ 805 __BIT(3), /* gate_mask */ 806 0), 807 RK_COMPOSITE(RK3399_SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_parents, 808 CLKSEL_CON(63), /* muxdiv_reg */ 809 __BIT(15), /* mux_mask */ 810 __BITS(14,8), /* div_mask */ 811 CLKGATE_CON(10), /* gate_reg */ 812 __BIT(5), /* gate_mask */ 813 0), 814 RK_GATE(RK3399_PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", CLKGATE_CON(22), 5), 815 RK_GATE(RK3399_PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", CLKGATE_CON(22), 6), 816 RK_GATE(RK3399_PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", CLKGATE_CON(22), 7), 817 RK_GATE(RK3399_PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", CLKGATE_CON(22), 8), 818 RK_GATE(RK3399_PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", CLKGATE_CON(22), 9), 819 RK_GATE(RK3399_PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", CLKGATE_CON(22), 10), 820 821 /* 822 * SPI 823 */ 824 RK_COMPOSITE(RK3399_SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_parents, 825 CLKSEL_CON(59), /* muxdiv_reg */ 826 __BIT(7), /* mux_mask */ 827 __BITS(6,0), /* div_mask */ 828 CLKGATE_CON(9), /* gate_reg */ 829 __BIT(12), /* gate_mask */ 830 0), 831 RK_COMPOSITE(RK3399_SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_parents, 832 CLKSEL_CON(59), /* muxdiv_reg */ 833 __BIT(15), /* mux_mask */ 834 __BITS(14,8), /* div_mask */ 835 CLKGATE_CON(9), /* gate_reg */ 836 __BIT(13), /* gate_mask */ 837 0), 838 RK_COMPOSITE(RK3399_SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_parents, 839 CLKSEL_CON(60), /* muxdiv_reg */ 840 __BIT(7), /* mux_mask */ 841 __BITS(6,0), /* div_mask */ 842 CLKGATE_CON(9), /* gate_reg */ 843 __BIT(14), /* gate_mask */ 844 0), 845 RK_COMPOSITE(RK3399_SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_parents, 846 CLKSEL_CON(60), /* muxdiv_reg */ 847 __BIT(15), /* mux_mask */ 848 __BITS(14,8), /* div_mask */ 849 CLKGATE_CON(9), /* gate_reg */ 850 __BIT(15), /* gate_mask */ 851 0), 852 RK_COMPOSITE(RK3399_SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_parents, 853 CLKSEL_CON(58), /* muxdiv_reg */ 854 __BIT(15), /* mux_mask */ 855 __BITS(14,8), /* div_mask */ 856 CLKGATE_CON(13), /* gate_reg */ 857 __BIT(13), /* gate_mask */ 858 0), 859 RK_GATE(RK3399_PCLK_SPI0, "pclk_rkspi0", "pclk_perilp1", CLKGATE_CON(23), 10), 860 RK_GATE(RK3399_PCLK_SPI1, "pclk_rkspi1", "pclk_perilp1", CLKGATE_CON(23), 11), 861 RK_GATE(RK3399_PCLK_SPI2, "pclk_rkspi2", "pclk_perilp1", CLKGATE_CON(23), 12), 862 RK_GATE(RK3399_PCLK_SPI4, "pclk_rkspi4", "pclk_perilp1", CLKGATE_CON(23), 13), 863 RK_GATE(RK3399_PCLK_SPI5, "pclk_rkspi5", "hclk_perilp1", CLKGATE_CON(34), 5), 864 865 /* Watchdog */ 866 RK_SECURE_GATE(RK3399_PCLK_WDT, "pclk_wdt", "pclk_alive" /*, SECURE_CLKGATE_CON(3), 8 */), 867 868 /* PCIe */ 869 RK_GATE(RK3399_ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLKGATE_CON(20), 2), 870 RK_GATE(RK3399_ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLKGATE_CON(20), 10), 871 RK_GATE(RK3399_PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLKGATE_CON(20), 11), 872 RK_COMPOSITE(RK3399_SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_parents, 873 CLKSEL_CON(17), /* muxdiv_reg */ 874 __BITS(10,8), /* mux_mask */ 875 __BITS(6,0), /* div_mask */ 876 CLKGATE_CON(6), /* gate_reg */ 877 __BIT(2), /* gate_mask */ 878 0), 879 RK_COMPOSITE_NOMUX(RK3399_SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 880 CLKSEL_CON(18), /* div_reg */ 881 __BITS(15,11), /* div_mask */ 882 CLKGATE_CON(12), /* gate_reg */ 883 __BIT(6), /* gate_mask */ 884 0), 885 RK_MUX(RK3399_SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_parents, CLKSEL_CON(18), __BIT(10)), 886 RK_COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_parents, 887 CLKSEL_CON(18), /* muxdiv_reg */ 888 __BITS(9,8), /* mux_mask */ 889 __BITS(6,0), /* div_mask */ 890 CLKGATE_CON(6), /* gate_reg */ 891 __BIT(3), /* gate_mask */ 892 0), 893 RK_MUX(RK3399_SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_parents, CLKSEL_CON(18), __BIT(7)), 894 895 /* Crypto */ 896 RK_COMPOSITE(RK3399_SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_parents, 897 CLKSEL_CON(24), /* muxdiv_reg */ 898 __BITS(7,6), /* mux_mask */ 899 __BITS(4,0), /* div_mask */ 900 CLKGATE_CON(7), /* gate_reg */ 901 __BIT(7), /* gate_mask */ 902 RK_COMPOSITE_ROUND_DOWN /*???*/), 903 RK_COMPOSITE(RK3399_SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_parents, 904 CLKSEL_CON(26), /* muxdiv_reg */ 905 __BITS(7,6), /* mux_mask */ 906 __BITS(4,0), /* div_mask */ 907 CLKGATE_CON(8), /* gate_reg */ 908 __BIT(7), /* gate_mask */ 909 RK_COMPOSITE_ROUND_DOWN /*???*/), 910 RK_GATE(RK3399_HCLK_M_CRYPTO0, "hclk_m_crypto0", "pclk_perilp0", CLKGATE_CON(24), 5), 911 RK_GATE(RK3399_HCLK_S_CRYPTO0, "hclk_s_crypto0", "pclk_perilp0", CLKGATE_CON(24), 6), 912 RK_GATE(RK3399_HCLK_M_CRYPTO1, "hclk_m_crypto1", "pclk_perilp0", CLKGATE_CON(24), 14), 913 RK_GATE(RK3399_HCLK_S_CRYPTO1, "hclk_s_crypto1", "pclk_perilp0", CLKGATE_CON(24), 15), 914 RK_GATE(RK3399_ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "pclk_perilp", CLKGATE_CON(25), 6), 915 916 /* TSADC */ 917 RK_COMPOSITE(RK3399_SCLK_TSADC, "clk_tsadc", mux_clk_tsadc_parents, 918 CLKSEL_CON(27), /* muxdiv_reg */ 919 __BIT(15), /* mux_mask */ 920 __BITS(9,0), /* div_mask */ 921 CLKGATE_CON(9), /* gate_reg */ 922 __BIT(1), /* gate_mask */ 923 RK_COMPOSITE_ROUND_DOWN), 924 RK_GATE(RK3399_PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", CLKGATE_CON(22), 13), 925 926 /* VOP0 */ 927 RK_COMPOSITE(RK3399_ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_parents, 928 CLKSEL_CON(47), /* muxdiv_reg */ 929 __BITS(7,6), /* mux_mask */ 930 __BITS(4,0), /* div_mask */ 931 CLKGATE_CON(10), /* gate_reg */ 932 __BIT(8), /* gate_mask */ 933 0), 934 RK_COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 935 CLKSEL_CON(47), /* div_reg */ 936 __BITS(12,8), /* div_mask */ 937 CLKGATE_CON(10), /* gate_reg */ 938 __BIT(9), /* gate_mask */ 939 0), 940 RK_COMPOSITE(RK3399_DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_parents, 941 CLKSEL_CON(49), /* muxdiv_reg */ 942 __BITS(9,8), /* mux_mask */ 943 __BITS(7,0), /* div_mask */ 944 CLKGATE_CON(10), /* gate_reg */ 945 __BIT(12), /* gate_mask */ 946 RK_COMPOSITE_SET_RATE_PARENT), 947 RK_GATE(RK3399_ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", CLKGATE_CON(28), 3), 948 RK_GATE(RK3399_HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", CLKGATE_CON(28), 2), 949 RK_COMPOSITE_FRAC(RK3399_DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 950 CLKSEL_CON(106), /* frac_reg */ 951 0), 952 RK_MUX(RK3399_DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_parents, CLKSEL_CON(49), __BIT(11)), 953 954 /* VOP1 */ 955 RK_COMPOSITE(RK3399_ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_parents, 956 CLKSEL_CON(48), /* muxdiv_reg */ 957 __BITS(7,6), /* mux_mask */ 958 __BITS(4,0), /* div_mask */ 959 CLKGATE_CON(10), /* gate_reg */ 960 __BIT(10), /* gate_mask */ 961 0), 962 RK_COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 963 CLKSEL_CON(48), /* div_reg */ 964 __BITS(12,8), /* div_mask */ 965 CLKGATE_CON(10), /* gate_reg */ 966 __BIT(11), /* gate_mask */ 967 0), 968 RK_COMPOSITE(RK3399_DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_parents, 969 CLKSEL_CON(50), /* muxdiv_reg */ 970 __BITS(9,8), /* mux_mask */ 971 __BITS(7,0), /* div_mask */ 972 CLKGATE_CON(10), /* gate_reg */ 973 __BIT(13), /* gate_mask */ 974 RK_COMPOSITE_SET_RATE_PARENT), 975 RK_GATE(RK3399_ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", CLKGATE_CON(28), 7), 976 RK_GATE(RK3399_HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", CLKGATE_CON(28), 6), 977 RK_COMPOSITE_FRAC(RK3399_DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 978 CLKSEL_CON(107), /* frac_reg */ 979 0), 980 RK_MUX(RK3399_DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_parents, CLKSEL_CON(50), __BIT(11)), 981 982 /* VIO */ 983 RK_COMPOSITE(RK3399_ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_parents, 984 CLKSEL_CON(42), /* muxdiv_reg */ 985 __BITS(7,6), /* mux_mask */ 986 __BITS(4,0), /* div_mask */ 987 CLKGATE_CON(11), /* gate_reg */ 988 __BIT(0), /* gate_mask */ 989 0), 990 RK_COMPOSITE_NOMUX(RK3399_PCLK_VIO, "pclk_vio", "aclk_vio", 991 CLKSEL_CON(43), /* div_reg */ 992 __BITS(4,0), /* div_mask */ 993 CLKGATE_CON(11), /* gate_reg */ 994 __BIT(1), /* gate_mask */ 995 0), 996 RK_GATE(RK3399_PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLKGATE_CON(29), 12), 997 998 /* HDMI */ 999 RK_COMPOSITE(RK3399_ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_parents, 1000 CLKSEL_CON(42), /* muxdiv_reg */ 1001 __BITS(15,14), /* mux_mask */ 1002 __BITS(12,8), /* div_mask */ 1003 CLKGATE_CON(11), /* gate_reg */ 1004 __BIT(12), /* gate_mask */ 1005 0), 1006 RK_COMPOSITE_NOMUX(RK3399_PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 1007 CLKSEL_CON(43), /* div_reg */ 1008 __BITS(14,10), /* div_mask */ 1009 CLKGATE_CON(11), /* gate_reg */ 1010 __BIT(10), /* gate_mask */ 1011 0), 1012 RK_COMPOSITE(RK3399_SCLK_HDMI_CEC, "clk_hdmi_cec", pll_parents, 1013 CLKSEL_CON(45), /* muxdiv_reg */ 1014 __BIT(15), /* mux_mask */ 1015 __BITS(9,0), /* div_mask */ 1016 CLKGATE_CON(11), /* gate_reg */ 1017 __BIT(7), /* gate_mask */ 1018 0), 1019 RK_GATE(RK3399_PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", CLKGATE_CON(29), 6), 1020 RK_GATE(RK3399_SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", CLKGATE_CON(11), 6), 1021 1022 /* I2S2 */ 1023 RK_COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_parents, 1024 CLKSEL_CON(28), /* muxdiv_reg */ 1025 __BIT(7), /* mux_mask */ 1026 __BITS(6,0), /* div_mask */ 1027 CLKGATE_CON(8), /* gate_reg */ 1028 __BIT(3), /* gate_mask */ 1029 0), 1030 RK_COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_parents, 1031 CLKSEL_CON(29), /* muxdiv_reg */ 1032 __BIT(7), /* mux_mask */ 1033 __BITS(6,0), /* div_mask */ 1034 CLKGATE_CON(8), /* gate_reg */ 1035 __BIT(6), /* gate_mask */ 1036 0), 1037 RK_COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_parents, 1038 CLKSEL_CON(30), /* muxdiv_reg */ 1039 __BIT(7), /* mux_mask */ 1040 __BITS(6,0), /* div_mask */ 1041 CLKGATE_CON(8), /* gate_reg */ 1042 __BIT(9), /* gate_mask */ 1043 0), 1044 RK_COMPOSITE_FRAC(0, "clk_i2s0_frac", "clk_i2s0_div", 1045 CLKSEL_CON(96), /* frac_reg */ 1046 0), 1047 RK_COMPOSITE_FRAC(0, "clk_i2s1_frac", "clk_i2s1_div", 1048 CLKSEL_CON(97), /* frac_reg */ 1049 0), 1050 RK_COMPOSITE_FRAC(0, "clk_i2s2_frac", "clk_i2s2_div", 1051 CLKSEL_CON(98), /* frac_reg */ 1052 0), 1053 RK_MUX(0, "clk_i2s0_mux", mux_i2s0_parents, CLKSEL_CON(28), __BITS(9,8)), 1054 RK_MUX(0, "clk_i2s1_mux", mux_i2s1_parents, CLKSEL_CON(29), __BITS(9,8)), 1055 RK_MUX(0, "clk_i2s2_mux", mux_i2s2_parents, CLKSEL_CON(30), __BITS(9,8)), 1056 RK_GATE(RK3399_SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLKGATE_CON(8), 5), 1057 RK_GATE(RK3399_SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLKGATE_CON(8), 8), 1058 RK_GATE(RK3399_SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLKGATE_CON(8), 11), 1059 RK_GATE(RK3399_HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", CLKGATE_CON(34), 0), 1060 RK_GATE(RK3399_HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", CLKGATE_CON(34), 1), 1061 RK_GATE(RK3399_HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", CLKGATE_CON(34), 2), 1062 RK_MUX(0, "clk_i2sout_src", mux_i2sch_parents, CLKSEL_CON(31), __BITS(1,0)), 1063 RK_COMPOSITE(RK3399_SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_parents, 1064 CLKSEL_CON(31), /* muxdiv_reg */ 1065 __BIT(2), /* mux_mask */ 1066 0, /* div_mask */ 1067 CLKGATE_CON(8), /* gate_reg */ 1068 __BIT(12), /* gate_mask */ 1069 RK_COMPOSITE_SET_RATE_PARENT), 1070 1071 /* eDP */ 1072 RK_COMPOSITE(RK3399_PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_parents, 1073 CLKSEL_CON(44), /* muxdiv_reg */ 1074 __BIT(15), /* mux_mask */ 1075 __BITS(13,8), /* div_mask */ 1076 CLKGATE_CON(11), /* gate_reg */ 1077 __BIT(11), /* gate_mask */ 1078 0), 1079 RK_GATE(RK3399_PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLKGATE_CON(32), 12), 1080 RK_GATE(RK3399_PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", CLKGATE_CON(32), 13), 1081 1082 RK_COMPOSITE(RK3399_SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_parents, 1083 CLKSEL_CON(46), /* muxdiv_reg */ 1084 __BITS(7,6), /* mux_mask */ 1085 __BITS(4,0), /* div_mask */ 1086 CLKGATE_CON(11), /* gate_reg */ 1087 __BIT(8), /* gate_mask */ 1088 0), 1089 RK_GATE(RK3399_PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", CLKGATE_CON(29), 7), 1090 1091 }; 1092 1093 static const struct rk3399_init_param { 1094 const char *clk; 1095 const char *parent; 1096 } rk3399_init_params[] = { 1097 { .clk = "clk_i2s0_mux", .parent = "clk_i2s0_frac" }, 1098 { .clk = "clk_i2s1_mux", .parent = "clk_i2s1_frac" }, 1099 { .clk = "clk_i2s2_mux", .parent = "clk_i2s2_frac" }, 1100 { .clk = "dclk_vop0_div", .parent = "gpll" }, 1101 { .clk = "dclk_vop1_div", .parent = "gpll" }, 1102 { .clk = "dclk_vop0", .parent = "dclk_vop0_frac" }, 1103 { .clk = "dclk_vop1", .parent = "dclk_vop1_frac" }, 1104 }; 1105 1106 static void 1107 rk3399_cru_init(struct rk_cru_softc *sc) 1108 { 1109 struct rk_cru_clk *clk, *pclk; 1110 uint32_t write_mask, write_val; 1111 int error; 1112 u_int n; 1113 1114 /* 1115 * Force an update of BPLL to bring it out of slow mode. 1116 */ 1117 clk = rk_cru_clock_find(sc, "armclkb"); 1118 clk_set_rate(&clk->base, clk_get_rate(&clk->base)); 1119 1120 /* 1121 * Set DCLK_VOP0 and DCLK_VOP1 dividers to 1. 1122 */ 1123 write_mask = __BITS(7,0) << 16; 1124 write_val = 0; 1125 CRU_WRITE(sc, CLKSEL_CON(49), write_mask | write_val); 1126 CRU_WRITE(sc, CLKSEL_CON(50), write_mask | write_val); 1127 1128 /* 1129 * Set defaults 1130 */ 1131 for (n = 0; n < __arraycount(rk3399_init_params); n++) { 1132 const struct rk3399_init_param *param = &rk3399_init_params[n]; 1133 clk = rk_cru_clock_find(sc, param->clk); 1134 KASSERTMSG(clk != NULL, "couldn't find clock %s", param->clk); 1135 if (param->parent != NULL) { 1136 pclk = rk_cru_clock_find(sc, param->parent); 1137 KASSERTMSG(pclk != NULL, "couldn't find clock %s", param->parent); 1138 error = clk_set_parent(&clk->base, &pclk->base); 1139 if (error != 0) { 1140 aprint_error_dev(sc->sc_dev, "couldn't set %s parent to %s: %d\n", 1141 param->clk, param->parent, error); 1142 continue; 1143 } 1144 } 1145 } 1146 } 1147 1148 static int 1149 rk3399_cru_match(device_t parent, cfdata_t cf, void *aux) 1150 { 1151 struct fdt_attach_args * const faa = aux; 1152 1153 return of_compatible_match(faa->faa_phandle, compat_data); 1154 } 1155 1156 static void 1157 rk3399_cru_attach(device_t parent, device_t self, void *aux) 1158 { 1159 struct rk_cru_softc * const sc = device_private(self); 1160 struct fdt_attach_args * const faa = aux; 1161 1162 sc->sc_dev = self; 1163 sc->sc_phandle = faa->faa_phandle; 1164 sc->sc_bst = faa->faa_bst; 1165 1166 sc->sc_clks = rk3399_cru_clks; 1167 sc->sc_nclks = __arraycount(rk3399_cru_clks); 1168 1169 sc->sc_grf_soc_status = 0x0480; 1170 sc->sc_softrst_base = SOFTRST_CON(0); 1171 1172 if (rk_cru_attach(sc) != 0) 1173 return; 1174 1175 aprint_naive("\n"); 1176 aprint_normal(": RK3399 CRU\n"); 1177 1178 rk3399_cru_init(sc); 1179 1180 rk_cru_print(sc); 1181 } 1182
Indexes created Fri Oct 03 02:09:57 GMT 2025