rk3399_cru.c revision 1.9
1 /* $NetBSD: rk3399_cru.c,v 1.9 2019/08/04 17:09:07 tnn Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: rk3399_cru.c,v 1.9 2019/08/04 17:09:07 tnn Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/rockchip/rk_cru.h> 41 #include <arm/rockchip/rk3399_cru.h> 42 43 #define PLL_CON(n) (0x0000 + (n) * 4) 44 #define CLKSEL_CON(n) (0x0100 + (n) * 4) 45 #define CLKGATE_CON(n) (0x0300 + (n) * 4) 46 #define SOFTRST_CON(n) (0x0400 + (n) * 4) 47 48 static int rk3399_cru_match(device_t, cfdata_t, void *); 49 static void rk3399_cru_attach(device_t, device_t, void *); 50 51 static const char * const compatible[] = { 52 "rockchip,rk3399-cru", 53 NULL 54 }; 55 56 CFATTACH_DECL_NEW(rk3399_cru, sizeof(struct rk_cru_softc), 57 rk3399_cru_match, rk3399_cru_attach, NULL, NULL); 58 59 static const struct rk_cru_pll_rate pll_rates[] = { 60 RK_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0), 61 RK_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0), 62 RK_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0), 63 RK_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0), 64 RK_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0), 65 RK_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0), 66 RK_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0), 67 RK_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0), 68 RK_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0), 69 RK_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0), 70 RK_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0), 71 RK_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0), 72 RK_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0), 73 RK_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0), 74 RK_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0), 75 RK_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0), 76 RK_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0), 77 RK_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0), 78 RK_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0), 79 RK_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0), 80 RK_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0), 81 RK_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0), 82 RK_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0), 83 RK_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0), 84 RK_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0), 85 RK_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0), 86 RK_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), 87 RK_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0), 88 RK_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0), 89 RK_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0), 90 RK_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0), 91 RK_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0), 92 RK_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0), 93 RK_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0), 94 RK_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0), 95 RK_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0), 96 RK_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0), 97 RK_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0), 98 RK_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0), 99 RK_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0), 100 RK_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0), 101 RK_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0), 102 RK_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0), 103 RK_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0), 104 RK_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0), 105 RK_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0), 106 RK_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), 107 RK_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), 108 RK_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0), 109 RK_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0), 110 RK_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0), 111 RK_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0), 112 RK_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0), 113 RK_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0), 114 RK_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0), 115 RK_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0), 116 RK_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0), 117 RK_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0), 118 RK_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0), 119 RK_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0), 120 RK_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0), 121 RK_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0), 122 RK_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0), 123 RK_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0), 124 RK_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0), 125 RK_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0), 126 RK_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0), 127 RK_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0), 128 RK_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0), 129 RK_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0), 130 RK_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0), 131 RK_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0), 132 RK_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0), 133 RK_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0), 134 RK_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0), 135 RK_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0), 136 RK_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0), 137 }; 138 139 static const struct rk_cru_pll_rate pll_norates[] = { 140 }; 141 142 #define RK3399_ACLKM_MASK __BITS(12,8) 143 #define RK3399_ATCLK_MASK __BITS(4,0) 144 #define RK3399_PDBG_MASK __BITS(12,8) 145 146 #define RK3399_CPUL_RATE(_rate, _aclkm, _atclk, _pdbg) \ 147 RK_CPU_RATE(_rate, \ 148 CLKSEL_CON(0), RK3399_ACLKM_MASK, \ 149 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \ 150 CLKSEL_CON(1), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \ 151 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK)) 152 153 #define RK3399_CPUB_RATE(_rate, _aclkm, _atclk, _pdbg) \ 154 RK_CPU_RATE(_rate, \ 155 CLKSEL_CON(2), RK3399_ACLKM_MASK, \ 156 __SHIFTIN((_aclkm), RK3399_ACLKM_MASK), \ 157 CLKSEL_CON(3), RK3399_ATCLK_MASK|RK3399_PDBG_MASK, \ 158 __SHIFTIN((_atclk), RK3399_ATCLK_MASK)|__SHIFTIN((_pdbg), RK3399_PDBG_MASK)) 159 160 static const struct rk_cru_cpu_rate armclkl_rates[] = { 161 RK3399_CPUL_RATE(1800000000, 1, 8, 8), 162 RK3399_CPUL_RATE(1704000000, 1, 8, 8), 163 RK3399_CPUL_RATE(1608000000, 1, 7, 7), 164 RK3399_CPUL_RATE(1512000000, 1, 7, 7), 165 RK3399_CPUL_RATE(1488000000, 1, 6, 6), 166 RK3399_CPUL_RATE(1416000000, 1, 6, 6), 167 RK3399_CPUL_RATE(1200000000, 1, 5, 5), 168 RK3399_CPUL_RATE(1008000000, 1, 5, 5), 169 RK3399_CPUL_RATE( 816000000, 1, 4, 4), 170 RK3399_CPUL_RATE( 696000000, 1, 3, 3), 171 RK3399_CPUL_RATE( 600000000, 1, 3, 3), 172 RK3399_CPUL_RATE( 408000000, 1, 2, 2), 173 RK3399_CPUL_RATE( 312000000, 1, 1, 1), 174 RK3399_CPUL_RATE( 216000000, 1, 1, 1), 175 RK3399_CPUL_RATE( 96000000, 1, 1, 1), 176 }; 177 178 static const struct rk_cru_cpu_rate armclkb_rates[] = { 179 RK3399_CPUB_RATE(2208000000, 1, 11, 11), 180 RK3399_CPUB_RATE(2184000000, 1, 11, 11), 181 RK3399_CPUB_RATE(2088000000, 1, 10, 10), 182 RK3399_CPUB_RATE(2040000000, 1, 10, 10), 183 RK3399_CPUB_RATE(2016000000, 1, 9, 9), 184 RK3399_CPUB_RATE(1992000000, 1, 9, 9), 185 RK3399_CPUB_RATE(1896000000, 1, 9, 9), 186 RK3399_CPUB_RATE(1800000000, 1, 8, 8), 187 RK3399_CPUB_RATE(1704000000, 1, 8, 8), 188 RK3399_CPUB_RATE(1608000000, 1, 7, 7), 189 RK3399_CPUB_RATE(1512000000, 1, 7, 7), 190 RK3399_CPUB_RATE(1488000000, 1, 6, 6), 191 RK3399_CPUB_RATE(1416000000, 1, 6, 6), 192 RK3399_CPUB_RATE(1200000000, 1, 5, 5), 193 RK3399_CPUB_RATE(1008000000, 1, 5, 5), 194 RK3399_CPUB_RATE( 816000000, 1, 4, 4), 195 RK3399_CPUB_RATE( 696000000, 1, 3, 3), 196 RK3399_CPUB_RATE( 600000000, 1, 3, 3), 197 RK3399_CPUB_RATE( 408000000, 1, 2, 2), 198 RK3399_CPUB_RATE( 312000000, 1, 1, 1), 199 RK3399_CPUB_RATE( 216000000, 1, 1, 1), 200 RK3399_CPUB_RATE( 96000000, 1, 1, 1), 201 }; 202 203 #define PLL_CON0 0x00 204 #define PLL_FBDIV __BITS(11,0) 205 206 #define PLL_CON1 0x04 207 #define PLL_POSTDIV2 __BITS(14,12) 208 #define PLL_POSTDIV1 __BITS(10,8) 209 #define PLL_REFDIV __BITS(5,0) 210 211 #define PLL_CON2 0x08 212 #define PLL_LOCK __BIT(31) 213 #define PLL_FRACDIV __BITS(23,0) 214 215 #define PLL_CON3 0x0c 216 #define PLL_WORK_MODE __BITS(9,8) 217 #define PLL_WORK_MODE_SLOW 0 218 #define PLL_WORK_MODE_NORMAL 1 219 #define PLL_WORK_MODE_DEEP_SLOW 2 220 #define PLL_DSMPD __BIT(3) 221 222 #define PLL_WRITE_MASK 0xffff0000 223 224 static u_int 225 rk3399_cru_pll_get_rate(struct rk_cru_softc *sc, 226 struct rk_cru_clk *clk) 227 { 228 struct rk_cru_pll *pll = &clk->u.pll; 229 struct clk *clkp, *clkp_parent; 230 u_int foutvco, foutpostdiv; 231 232 KASSERT(clk->type == RK_CRU_PLL); 233 234 clkp = &clk->base; 235 clkp_parent = clk_get_parent(clkp); 236 if (clkp_parent == NULL) 237 return 0; 238 239 const u_int fref = clk_get_rate(clkp_parent); 240 if (fref == 0) 241 return 0; 242 243 const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0); 244 const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1); 245 const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2); 246 const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3); 247 248 const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV); 249 const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2); 250 const u_int postdiv1 = __SHIFTOUT(con1, PLL_POSTDIV1); 251 const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV); 252 const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV); 253 const u_int dsmpd = __SHIFTOUT(con3, PLL_DSMPD); 254 255 if (dsmpd == 1) { 256 /* integer mode */ 257 foutvco = fref / refdiv * fbdiv; 258 } else { 259 /* fractional mode */ 260 foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24); 261 } 262 foutpostdiv = foutvco / postdiv1 / postdiv2; 263 264 return foutpostdiv; 265 } 266 267 static int 268 rk3399_cru_pll_set_rate(struct rk_cru_softc *sc, 269 struct rk_cru_clk *clk, u_int rate) 270 { 271 struct rk_cru_pll *pll = &clk->u.pll; 272 const struct rk_cru_pll_rate *pll_rate = NULL; 273 uint32_t val; 274 int retry; 275 276 KASSERT(clk->type == RK_CRU_PLL); 277 278 if (pll->rates == NULL || rate == 0) 279 return EIO; 280 281 for (int i = 0; i < pll->nrates; i++) 282 if (pll->rates[i].rate == rate) { 283 pll_rate = &pll->rates[i]; 284 break; 285 } 286 if (pll_rate == NULL) 287 return EINVAL; 288 289 val = __SHIFTIN(PLL_WORK_MODE_SLOW, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 290 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 291 292 CRU_WRITE(sc, pll->con_base + PLL_CON0, 293 __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) | (PLL_FBDIV << 16)); 294 295 CRU_WRITE(sc, pll->con_base + PLL_CON1, 296 __SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) | 297 __SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) | 298 __SHIFTIN(pll_rate->refdiv, PLL_REFDIV) | 299 ((PLL_POSTDIV2 | PLL_POSTDIV1 | PLL_REFDIV) << 16)); 300 301 val = CRU_READ(sc, pll->con_base + PLL_CON2); 302 val &= ~PLL_FRACDIV; 303 val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV); 304 CRU_WRITE(sc, pll->con_base + PLL_CON2, val); 305 306 val = __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) | (PLL_DSMPD << 16); 307 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 308 309 for (retry = 1000; retry > 0; retry--) { 310 if (CRU_READ(sc, pll->con_base + PLL_CON2) & pll->lock_mask) 311 break; 312 delay(1); 313 } 314 315 if (retry == 0) 316 device_printf(sc->sc_dev, "WARNING: %s failed to lock\n", 317 clk->base.name); 318 319 /* Set PLL work mode to normal */ 320 val = __SHIFTIN(PLL_WORK_MODE_NORMAL, PLL_WORK_MODE) | (PLL_WORK_MODE << 16); 321 CRU_WRITE(sc, pll->con_base + PLL_CON3, val); 322 323 return 0; 324 } 325 326 #define RK3399_PLL(_id, _name, _parents, _con_base, _mode_reg, _mode_mask, _lock_mask, _rates) \ 327 { \ 328 .id = (_id), \ 329 .type = RK_CRU_PLL, \ 330 .base.name = (_name), \ 331 .base.flags = 0, \ 332 .u.pll.parents = (_parents), \ 333 .u.pll.nparents = __arraycount(_parents), \ 334 .u.pll.con_base = (_con_base), \ 335 .u.pll.mode_reg = (_mode_reg), \ 336 .u.pll.mode_mask = (_mode_mask), \ 337 .u.pll.lock_mask = (_lock_mask), \ 338 .u.pll.rates = (_rates), \ 339 .u.pll.nrates = __arraycount(_rates), \ 340 .get_rate = rk3399_cru_pll_get_rate, \ 341 .set_rate = rk3399_cru_pll_set_rate, \ 342 .get_parent = rk_cru_pll_get_parent, \ 343 } 344 345 static const char * pll_parents[] = { "xin24m", "xin32k" }; 346 static const char * armclkl_parents[] = { "clk_core_l_lpll_src", "clk_core_l_bpll_src", "clk_core_l_dpll_src", "clk_core_l_gpll_src" }; 347 static const char * armclkb_parents[] = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" }; 348 static const char * mux_clk_tsadc_parents[] = { "xin24m", "xin32k" }; 349 static const char * mux_pll_src_cpll_gpll_parents[] = { "cpll", "gpll" }; 350 static const char * mux_pll_src_cpll_gpll_npll_parents[] = { "cpll", "gpll", "npll" }; 351 static const char * mux_pll_src_cpll_gpll_upll_parents[] = { "cpll", "gpll", "upll" }; 352 static const char * mux_pll_src_cpll_gpll_npll_24m_parents[] = { "cpll", "gpll", "npll", "xin24m" }; 353 static const char * mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents[] = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m" }; 354 static const char * mux_aclk_perilp0_parents[] = { "cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src" }; 355 static const char * mux_hclk_perilp1_parents[] = { "cpll_hclk_perilp1_src", "gpll_hclk_perilp1_src" }; 356 static const char * mux_aclk_perihp_parents[] = { "cpll_aclk_perihp_src", "gpll_aclk_perihp_src" }; 357 static const char * mux_aclk_cci_parents[] = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", "vpll_aclk_cci_src" }; 358 static const char * mux_uart0_parents[] = { "clk_uart0_div", "clk_uart0_frac", "xin24m" }; 359 static const char * mux_uart1_parents[] = { "clk_uart1_div", "clk_uart1_frac", "xin24m" }; 360 static const char * mux_uart2_parents[] = { "clk_uart2_div", "clk_uart2_frac", "xin24m" }; 361 static const char * mux_uart3_parents[] = { "clk_uart3_div", "clk_uart3_frac", "xin24m" }; 362 static const char * mux_rmii_parents[] = { "clk_gmac", "clkin_gmac" }; 363 static const char * mux_aclk_gmac_parents[] = { "cpll_aclk_gmac_src", "gpll_aclk_gmac_src" }; 364 static const char * mux_aclk_emmc_parents[] = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" }; 365 static const char * mux_pll_src_24m_pciephy_parents[] = { "xin24m", "clk_pciephy_ref100m" }; 366 static const char * mux_pciecore_cru_phy_parents[] = { "clk_pcie_core_cru", "clk_pcie_core_phy" }; 367 368 static struct rk_cru_clk rk3399_cru_clks[] = { 369 RK3399_PLL(RK3399_PLL_APLLL, "lpll", pll_parents, 370 PLL_CON(0), /* con_base */ 371 PLL_CON(3), /* mode_reg */ 372 __BIT(8), /* mode_mask */ 373 __BIT(31), /* lock_mask */ 374 pll_rates), 375 RK3399_PLL(RK3399_PLL_APLLB, "bpll", pll_parents, 376 PLL_CON(8), /* con_base */ 377 PLL_CON(11), /* mode_reg */ 378 __BIT(8), /* mode_mask */ 379 __BIT(31), /* lock_mask */ 380 pll_rates), 381 RK3399_PLL(RK3399_PLL_DPLL, "dpll", pll_parents, 382 PLL_CON(16), /* con_base */ 383 PLL_CON(19), /* mode_reg */ 384 __BIT(8), /* mode_mask */ 385 __BIT(31), /* lock_mask */ 386 pll_norates), 387 RK3399_PLL(RK3399_PLL_CPLL, "cpll", pll_parents, 388 PLL_CON(24), /* con_base */ 389 PLL_CON(27), /* mode_reg */ 390 __BIT(8), /* mode_mask */ 391 __BIT(31), /* lock_mask */ 392 pll_rates), 393 RK3399_PLL(RK3399_PLL_GPLL, "gpll", pll_parents, 394 PLL_CON(32), /* con_base */ 395 PLL_CON(35), /* mode_reg */ 396 __BIT(8), /* mode_mask */ 397 __BIT(31), /* lock_mask */ 398 pll_rates), 399 RK3399_PLL(RK3399_PLL_NPLL, "npll", pll_parents, 400 PLL_CON(40), /* con_base */ 401 PLL_CON(43), /* mode_reg */ 402 __BIT(8), /* mode_mask */ 403 __BIT(31), /* lock_mask */ 404 pll_rates), 405 RK3399_PLL(RK3399_PLL_VPLL, "vpll", pll_parents, 406 PLL_CON(43), /* con_base */ 407 PLL_CON(51), /* mode_reg */ 408 __BIT(8), /* mode_mask */ 409 __BIT(31), /* lock_mask */ 410 pll_rates), 411 412 RK_GATE(0, "clk_core_l_lpll_src", "lpll", CLKGATE_CON(0), 0), 413 RK_GATE(0, "clk_core_l_bpll_src", "bpll", CLKGATE_CON(0), 1), 414 RK_GATE(0, "clk_core_l_dpll_src", "dpll", CLKGATE_CON(0), 2), 415 RK_GATE(0, "clk_core_l_gpll_src", "gpll", CLKGATE_CON(0), 3), 416 417 RK_CPU(RK3399_ARMCLKL, "armclkl", armclkl_parents, 418 CLKSEL_CON(0), /* reg */ 419 __BITS(7,6), 0, 3, /* mux_mask, mux_main, mux_alt */ 420 __BITS(4,0), /* div_mask */ 421 armclkl_rates), 422 423 RK_GATE(0, "clk_core_b_lpll_src", "lpll", CLKGATE_CON(1), 0), 424 RK_GATE(0, "clk_core_b_bpll_src", "bpll", CLKGATE_CON(1), 1), 425 RK_GATE(0, "clk_core_b_dpll_src", "dpll", CLKGATE_CON(1), 2), 426 RK_GATE(0, "clk_core_b_gpll_src", "gpll", CLKGATE_CON(1), 3), 427 428 RK_CPU(RK3399_ARMCLKB, "armclkb", armclkb_parents, 429 CLKSEL_CON(2), /* reg */ 430 __BITS(7,6), 1, 3, /* mux_mask, mux_main, mux_alt */ 431 __BITS(4,0), /* div_mask */ 432 armclkb_rates), 433 434 /* 435 * perilp0 436 */ 437 RK_GATE(0, "gpll_aclk_perilp0_src", "gpll", CLKGATE_CON(7), 0), 438 RK_GATE(0, "cpll_aclk_perilp0_src", "cpll", CLKGATE_CON(7), 1), 439 RK_COMPOSITE(RK3399_ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_parents, 440 CLKSEL_CON(23), /* muxdiv_reg */ 441 __BIT(7), /* mux_mask */ 442 __BITS(4,0), /* div_mask */ 443 CLKGATE_CON(7), /* gate_reg */ 444 __BIT(2), /* gate_mask */ 445 0), 446 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", 447 CLKSEL_CON(23), /* div_reg */ 448 __BITS(10,8), /* div_mask */ 449 CLKGATE_CON(7), /* gate_reg */ 450 __BIT(3), /* gate_mask */ 451 0), 452 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 453 CLKSEL_CON(23), /* div_reg */ 454 __BITS(14,12), /* div_mask */ 455 CLKGATE_CON(7), /* gate_reg */ 456 __BIT(4), /* gate_mask */ 457 0), 458 459 /* 460 * perilp1 461 */ 462 RK_GATE(0, "gpll_hclk_perilp1_src", "gpll", CLKGATE_CON(8), 0), 463 RK_GATE(0, "cpll_hclk_perilp1_src", "cpll", CLKGATE_CON(8), 1), 464 RK_COMPOSITE_NOGATE(RK3399_HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_parents, 465 CLKSEL_CON(25), /* muxdiv_reg */ 466 __BITS(10,8), /* mux_mask */ 467 __BITS(4,0), /* div_mask */ 468 0), 469 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", 470 CLKSEL_CON(25), /* div_reg */ 471 __BITS(10,8), /* div_mask */ 472 CLKGATE_CON(8), /* gate_reg */ 473 __BIT(2), /* gate_mask */ 474 0), 475 476 /* 477 * perihp 478 */ 479 RK_GATE(0, "gpll_aclk_perihp_src", "gpll", CLKGATE_CON(5), 0), 480 RK_GATE(0, "cpll_aclk_perihp_src", "cpll", CLKGATE_CON(5), 1), 481 RK_COMPOSITE(RK3399_ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_parents, 482 CLKSEL_CON(14), /* muxdiv_reg */ 483 __BIT(7), /* mux_mask */ 484 __BITS(4,0), /* div_mask */ 485 CLKGATE_CON(5), /* gate_reg */ 486 __BIT(2), /* gate_mask */ 487 0), 488 RK_COMPOSITE_NOMUX(RK3399_HCLK_PERIHP, "hclk_perihp", "aclk_perihp", 489 CLKSEL_CON(14), /* div_reg */ 490 __BITS(10,8), /* div_mask */ 491 CLKGATE_CON(5), /* gate_reg */ 492 __BIT(3), /* gate_mask */ 493 0), 494 RK_COMPOSITE_NOMUX(RK3399_PCLK_PERIHP, "pclk_perihp", "aclk_perihp", 495 CLKSEL_CON(14), /* div_reg */ 496 __BITS(14,12), /* div_mask */ 497 CLKGATE_CON(5), /* gate_reg */ 498 __BIT(4), /* gate_mask */ 499 0), 500 501 /* 502 * CCI 503 */ 504 RK_GATE(0, "cpll_aclk_cci_src", "cpll", CLKGATE_CON(2), 0), 505 RK_GATE(0, "gpll_aclk_cci_src", "gpll", CLKGATE_CON(2), 1), 506 RK_GATE(0, "npll_aclk_cci_src", "npll", CLKGATE_CON(2), 2), 507 RK_GATE(0, "vpll_aclk_cci_src", "vpll", CLKGATE_CON(2), 3), 508 RK_COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_parents, 509 CLKSEL_CON(5), /* muxdiv_reg */ 510 __BITS(7,6), /* mux_mask */ 511 __BITS(4,0), /* div_mask */ 512 CLKGATE_CON(2), /* gate_reg */ 513 __BIT(4), /* gate_mask */ 514 0), 515 RK_GATE(RK3399_ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLKGATE_CON(15), 2), 516 517 /* 518 * GIC 519 */ 520 RK_COMPOSITE(RK3399_ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_parents, 521 CLKSEL_CON(56), /* muxdiv_reg */ 522 __BIT(15), /* mux_mask */ 523 __BITS(12,8), /* div_mask */ 524 CLKGATE_CON(12), /* gate_reg */ 525 __BIT(12), /* gate_mask */ 526 0), 527 528 /* 529 * DDR 530 */ 531 RK_COMPOSITE(RK3399_PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_parents, 532 CLKSEL_CON(6), /* muxdiv_reg */ 533 __BIT(15), /* mux_mask */ 534 __BITS(12,8), /* div_mask */ 535 CLKGATE_CON(3), /* gate_reg */ 536 __BIT(4), /* gate_mask */ 537 0), 538 539 /* 540 * alive 541 */ 542 RK_DIV(RK3399_PCLK_ALIVE, "pclk_alive", "gpll", CLKSEL_CON(57), __BITS(4,0), 0), 543 544 /* 545 * GPIO 546 */ 547 RK_GATE(RK3399_PCLK_GPIO2, "pclk_gpio2", "pclk_alive", CLKGATE_CON(31), 3), 548 RK_GATE(RK3399_PCLK_GPIO3, "pclk_gpio3", "pclk_alive", CLKGATE_CON(31), 4), 549 RK_GATE(RK3399_PCLK_GPIO4, "pclk_gpio4", "pclk_alive", CLKGATE_CON(31), 5), 550 551 /* 552 * UART 553 */ 554 RK_MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_parents, CLKSEL_CON(33), __BITS(13,12)), 555 RK_MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_parents, CLKSEL_CON(33), __BIT(15)), 556 RK_COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 557 CLKSEL_CON(33), /* div_reg */ 558 __BITS(6,0), /* div_mask */ 559 CLKGATE_CON(9), /* gate_reg */ 560 __BIT(0), /* gate_mask */ 561 0), 562 RK_COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 563 CLKSEL_CON(34), /* div_reg */ 564 __BITS(6,0), /* div_mask */ 565 CLKGATE_CON(9), /* gate_reg */ 566 __BIT(2), /* gate_mask */ 567 0), 568 RK_COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 569 CLKSEL_CON(35), /* div_reg */ 570 __BITS(6,0), /* div_mask */ 571 CLKGATE_CON(9), /* gate_reg */ 572 __BIT(4), /* gate_mask */ 573 0), 574 RK_COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 575 CLKSEL_CON(36), /* div_reg */ 576 __BITS(6,0), /* div_mask */ 577 CLKGATE_CON(9), /* gate_reg */ 578 __BIT(6), /* gate_mask */ 579 0), 580 RK_MUX(RK3399_SCLK_UART0, "clk_uart0", mux_uart0_parents, CLKSEL_CON(33), __BITS(9,8)), 581 RK_MUX(RK3399_SCLK_UART1, "clk_uart1", mux_uart1_parents, CLKSEL_CON(34), __BITS(9,8)), 582 RK_MUX(RK3399_SCLK_UART2, "clk_uart2", mux_uart2_parents, CLKSEL_CON(35), __BITS(9,8)), 583 RK_MUX(RK3399_SCLK_UART3, "clk_uart3", mux_uart3_parents, CLKSEL_CON(36), __BITS(9,8)), 584 RK_GATE(RK3399_PCLK_UART0, "pclk_uart0", "pclk_perilp1", CLKGATE_CON(22), 0), 585 RK_GATE(RK3399_PCLK_UART1, "pclk_uart1", "pclk_perilp1", CLKGATE_CON(22), 1), 586 RK_GATE(RK3399_PCLK_UART2, "pclk_uart2", "pclk_perilp1", CLKGATE_CON(22), 2), 587 RK_GATE(RK3399_PCLK_UART3, "pclk_uart3", "pclk_perilp1", CLKGATE_CON(22), 3), 588 589 /* 590 * SDMMC/SDIO 591 */ 592 RK_COMPOSITE(RK3399_HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_parents, 593 CLKSEL_CON(13), /* muxdiv_reg */ 594 __BIT(15), /* mux_mask */ 595 __BITS(12,8), /* div_mask */ 596 CLKGATE_CON(12), /* gate_reg */ 597 __BIT(13), /* gate_mask */ 598 RK_COMPOSITE_ROUND_DOWN), 599 RK_COMPOSITE(RK3399_SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 600 CLKSEL_CON(15), /* muxdiv_reg */ 601 __BITS(10,8), /* mux_mask */ 602 __BITS(6,0), /* div_mask */ 603 CLKGATE_CON(6), /* gate_reg */ 604 __BIT(0), /* gate_mask */ 605 RK_COMPOSITE_ROUND_DOWN), 606 RK_COMPOSITE(RK3399_SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 607 CLKSEL_CON(16), /* muxdiv_reg */ 608 __BITS(10,8), /* mux_mask */ 609 __BITS(6,0), /* div_mask */ 610 CLKGATE_CON(6), /* gate_reg */ 611 __BIT(1), /* gate_mask */ 612 RK_COMPOSITE_ROUND_DOWN), 613 RK_GATE(RK3399_HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", CLKGATE_CON(33), 8), 614 RK_GATE(RK3399_HCLK_SDIO, "hclk_sdio", "pclk_perilp1", CLKGATE_CON(34), 4), 615 616 /* 617 * eMMC 618 */ 619 RK_COMPOSITE(RK3399_SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_parents, 620 CLKSEL_CON(22), /* muxdiv_reg */ 621 __BITS(10,8), /* mux_mask */ 622 __BITS(6,0), /* div_mask */ 623 CLKGATE_CON(6), /* gate_reg */ 624 __BIT(14), /* gate_mask */ 625 RK_COMPOSITE_ROUND_DOWN), 626 RK_GATE(0, "cpll_aclk_emmc_src", "cpll", CLKGATE_CON(6), 13), 627 RK_GATE(0, "gpll_aclk_emmc_src", "gpll", CLKGATE_CON(6), 12), 628 RK_COMPOSITE_NOGATE(RK3399_ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_parents, 629 CLKSEL_CON(21), /* muxdiv_reg */ 630 __BIT(7), /* mux_mask */ 631 __BITS(4,0), /* div_mask */ 632 0), 633 RK_GATE(RK3399_ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLKGATE_CON(32), 8), 634 RK_GATE(RK3399_ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLKGATE_CON(32), 9), 635 RK_GATE(RK3399_ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLKGATE_CON(32), 10), 636 637 /* 638 * GMAC 639 */ 640 RK_COMPOSITE(RK3399_SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_parents, 641 CLKSEL_CON(20), /* muxdiv_reg */ 642 __BITS(15,14), /* mux_mask */ 643 __BITS(12,8), /* div_mask */ 644 CLKGATE_CON(5), /* gate_reg */ 645 __BIT(5), /* gate_mask */ 646 0), 647 RK_MUX(RK3399_SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_parents, CLKSEL_CON(19), __BIT(4)), 648 RK_GATE(RK3399_SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", CLKGATE_CON(5), 6), 649 RK_GATE(RK3399_SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", CLKGATE_CON(5), 7), 650 RK_GATE(RK3399_SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", CLKGATE_CON(5), 8), 651 RK_GATE(RK3399_SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", CLKGATE_CON(5), 9), 652 RK_GATE(0, "gpll_aclk_gmac_src", "gpll", CLKGATE_CON(6), 8), 653 RK_GATE(0, "cpll_aclk_gmac_src", "cpll", CLKGATE_CON(6), 9), 654 RK_COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_parents, 655 CLKSEL_CON(20), /* muxdiv_reg */ 656 __BIT(17), /* mux_mask */ 657 __BITS(4,0), /* div_mask */ 658 CLKGATE_CON(6), /* gate_reg */ 659 __BIT(10), /* gate_mask */ 660 0), 661 RK_GATE(RK3399_ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", CLKGATE_CON(32), 0), 662 RK_COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 663 CLKSEL_CON(19), /* div_reg */ 664 __BITS(10,8), /* div_mask */ 665 CLKGATE_CON(6), /* gate_reg */ 666 __BIT(11), /* gate_mask */ 667 0), 668 RK_GATE(RK3399_PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", CLKGATE_CON(32), 2), 669 670 /* 671 * USB2 672 */ 673 RK_GATE(RK3399_HCLK_HOST0, "hclk_host0", "hclk_perihp", CLKGATE_CON(20), 5), 674 RK_GATE(RK3399_HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", CLKGATE_CON(20), 6), 675 RK_GATE(RK3399_HCLK_HOST1, "hclk_host1", "hclk_perihp", CLKGATE_CON(20), 7), 676 RK_GATE(RK3399_HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", CLKGATE_CON(20), 8), 677 RK_GATE(RK3399_SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLKGATE_CON(6), 5), 678 RK_GATE(RK3399_SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLKGATE_CON(6), 6), 679 680 /* 681 * USB3 682 */ 683 RK_GATE(RK3399_SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", CLKGATE_CON(12), 1), 684 RK_GATE(RK3399_SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", CLKGATE_CON(12), 2), 685 RK_COMPOSITE(RK3399_SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", pll_parents, 686 CLKSEL_CON(40), /* muxdiv_reg */ 687 __BIT(15), /* mux_mask */ 688 __BITS(9,0), /* div_mask */ 689 CLKGATE_CON(12), /* gate_reg */ 690 __BIT(3), /* gate_mask */ 691 0), 692 RK_COMPOSITE(RK3399_SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", pll_parents, 693 CLKSEL_CON(41), /* muxdiv_reg */ 694 __BIT(15), /* mux_mask */ 695 __BITS(9,0), /* div_mask */ 696 CLKGATE_CON(12), /* gate_reg */ 697 __BIT(4), /* gate_mask */ 698 0), 699 RK_COMPOSITE(RK3399_ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_parents, 700 CLKSEL_CON(39), /* muxdiv_reg */ 701 __BITS(7,6), /* mux_mask */ 702 __BITS(4,0), /* div_mask */ 703 CLKGATE_CON(12), /* gate_reg */ 704 __BIT(0), /* gate_mask */ 705 0), 706 RK_GATE(RK3399_ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", CLKGATE_CON(30), 1), 707 RK_GATE(RK3399_ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", CLKGATE_CON(30), 2), 708 RK_GATE(RK3399_ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", CLKGATE_CON(30), 3), 709 RK_GATE(RK3399_ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", CLKGATE_CON(30), 4), 710 711 /* 712 * I2C 713 */ 714 RK_COMPOSITE(RK3399_SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_parents, 715 CLKSEL_CON(61), /* muxdiv_reg */ 716 __BIT(7), /* mux_mask */ 717 __BITS(6,0), /* div_mask */ 718 CLKGATE_CON(10), /* gate_reg */ 719 __BIT(0), /* gate_mask */ 720 0), 721 RK_COMPOSITE(RK3399_SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_parents, 722 CLKSEL_CON(62), /* muxdiv_reg */ 723 __BIT(7), /* mux_mask */ 724 __BITS(6,0), /* div_mask */ 725 CLKGATE_CON(10), /* gate_reg */ 726 __BIT(2), /* gate_mask */ 727 0), 728 RK_COMPOSITE(RK3399_SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_parents, 729 CLKSEL_CON(63), /* muxdiv_reg */ 730 __BIT(7), /* mux_mask */ 731 __BITS(6,0), /* div_mask */ 732 CLKGATE_CON(10), /* gate_reg */ 733 __BIT(4), /* gate_mask */ 734 0), 735 RK_COMPOSITE(RK3399_SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_parents, 736 CLKSEL_CON(61), /* muxdiv_reg */ 737 __BIT(15), /* mux_mask */ 738 __BITS(14,8), /* div_mask */ 739 CLKGATE_CON(10), /* gate_reg */ 740 __BIT(1), /* gate_mask */ 741 0), 742 RK_COMPOSITE(RK3399_SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_parents, 743 CLKSEL_CON(62), /* muxdiv_reg */ 744 __BIT(15), /* mux_mask */ 745 __BITS(14,8), /* div_mask */ 746 CLKGATE_CON(10), /* gate_reg */ 747 __BIT(3), /* gate_mask */ 748 0), 749 RK_COMPOSITE(RK3399_SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_parents, 750 CLKSEL_CON(63), /* muxdiv_reg */ 751 __BIT(15), /* mux_mask */ 752 __BITS(14,8), /* div_mask */ 753 CLKGATE_CON(10), /* gate_reg */ 754 __BIT(5), /* gate_mask */ 755 0), 756 RK_GATE(RK3399_PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", CLKGATE_CON(22), 5), 757 RK_GATE(RK3399_PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", CLKGATE_CON(22), 6), 758 RK_GATE(RK3399_PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", CLKGATE_CON(22), 7), 759 RK_GATE(RK3399_PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", CLKGATE_CON(22), 8), 760 RK_GATE(RK3399_PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", CLKGATE_CON(22), 9), 761 RK_GATE(RK3399_PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", CLKGATE_CON(22), 10), 762 763 /* 764 * SPI 765 */ 766 RK_COMPOSITE(RK3399_SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_parents, 767 CLKSEL_CON(59), /* muxdiv_reg */ 768 __BIT(7), /* mux_mask */ 769 __BITS(6,0), /* div_mask */ 770 CLKGATE_CON(9), /* gate_reg */ 771 __BIT(12), /* gate_mask */ 772 0), 773 RK_COMPOSITE(RK3399_SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_parents, 774 CLKSEL_CON(59), /* muxdiv_reg */ 775 __BIT(15), /* mux_mask */ 776 __BITS(14,8), /* div_mask */ 777 CLKGATE_CON(9), /* gate_reg */ 778 __BIT(13), /* gate_mask */ 779 0), 780 RK_COMPOSITE(RK3399_SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_parents, 781 CLKSEL_CON(60), /* muxdiv_reg */ 782 __BIT(7), /* mux_mask */ 783 __BITS(6,0), /* div_mask */ 784 CLKGATE_CON(9), /* gate_reg */ 785 __BIT(14), /* gate_mask */ 786 0), 787 RK_COMPOSITE(RK3399_SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_parents, 788 CLKSEL_CON(60), /* muxdiv_reg */ 789 __BIT(15), /* mux_mask */ 790 __BITS(14,8), /* div_mask */ 791 CLKGATE_CON(9), /* gate_reg */ 792 __BIT(15), /* gate_mask */ 793 0), 794 RK_COMPOSITE(RK3399_SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_parents, 795 CLKSEL_CON(58), /* muxdiv_reg */ 796 __BIT(15), /* mux_mask */ 797 __BITS(14,8), /* div_mask */ 798 CLKGATE_CON(13), /* gate_reg */ 799 __BIT(13), /* gate_mask */ 800 0), 801 RK_GATE(RK3399_PCLK_SPI0, "pclk_rkspi0", "pclk_perilp1", CLKGATE_CON(23), 10), 802 RK_GATE(RK3399_PCLK_SPI1, "pclk_rkspi1", "pclk_perilp1", CLKGATE_CON(23), 11), 803 RK_GATE(RK3399_PCLK_SPI2, "pclk_rkspi2", "pclk_perilp1", CLKGATE_CON(23), 12), 804 RK_GATE(RK3399_PCLK_SPI4, "pclk_rkspi4", "pclk_perilp1", CLKGATE_CON(23), 13), 805 RK_GATE(RK3399_PCLK_SPI5, "pclk_rkspi5", "hclk_perilp1", CLKGATE_CON(34), 5), 806 807 /* PCIe */ 808 RK_GATE(RK3399_ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLKGATE_CON(20), 2), 809 RK_GATE(RK3399_ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLKGATE_CON(20), 10), 810 RK_GATE(RK3399_PCLK_PCIE, "pclk_pcie", "pclk_perihp", CLKGATE_CON(20), 11), 811 RK_COMPOSITE(RK3399_SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_parents, 812 CLKSEL_CON(17), /* muxdiv_reg */ 813 __BITS(10,8), /* mux_mask */ 814 __BITS(6,0), /* div_mask */ 815 CLKGATE_CON(6), /* gate_reg */ 816 __BIT(2), /* gate_mask */ 817 0), 818 RK_COMPOSITE_NOMUX(RK3399_SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 819 CLKSEL_CON(18), /* div_reg */ 820 __BITS(15,11), /* div_mask */ 821 CLKGATE_CON(12), /* gate_reg */ 822 __BIT(6), /* gate_mask */ 823 0), 824 RK_MUX(RK3399_SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_parents, CLKSEL_CON(18), __BIT(10)), 825 RK_COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_parents, 826 CLKSEL_CON(18), /* muxdiv_reg */ 827 __BITS(9,8), /* mux_mask */ 828 __BITS(6,0), /* div_mask */ 829 CLKGATE_CON(6), /* gate_reg */ 830 __BIT(3), /* gate_mask */ 831 0), 832 RK_MUX(RK3399_SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_parents, CLKSEL_CON(18), __BIT(7)), 833 834 /* TSADC */ 835 RK_COMPOSITE(RK3399_SCLK_TSADC, "clk_tsadc", mux_clk_tsadc_parents, 836 CLKSEL_CON(27), /* muxdiv_reg */ 837 __BIT(15), /* mux_mask */ 838 __BITS(9,0), /* div_mask */ 839 CLKGATE_CON(9), /* gate_reg */ 840 __BIT(1), /* gate_mask */ 841 RK_COMPOSITE_ROUND_DOWN), 842 RK_GATE(RK3399_PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", CLKGATE_CON(22), 13), 843 }; 844 845 static void 846 rk3399_cru_init(struct rk_cru_softc *sc) 847 { 848 struct rk_cru_clk *clk; 849 850 /* 851 * Force an update of BPLL to bring it out of slow mode. 852 */ 853 clk = rk_cru_clock_find(sc, "armclkb"); 854 clk_set_rate(&clk->base, clk_get_rate(&clk->base)); 855 } 856 857 static int 858 rk3399_cru_match(device_t parent, cfdata_t cf, void *aux) 859 { 860 struct fdt_attach_args * const faa = aux; 861 862 return of_match_compatible(faa->faa_phandle, compatible); 863 } 864 865 static void 866 rk3399_cru_attach(device_t parent, device_t self, void *aux) 867 { 868 struct rk_cru_softc * const sc = device_private(self); 869 struct fdt_attach_args * const faa = aux; 870 871 sc->sc_dev = self; 872 sc->sc_phandle = faa->faa_phandle; 873 sc->sc_bst = faa->faa_bst; 874 875 sc->sc_clks = rk3399_cru_clks; 876 sc->sc_nclks = __arraycount(rk3399_cru_clks); 877 878 sc->sc_softrst_base = SOFTRST_CON(0); 879 880 if (rk_cru_attach(sc) != 0) 881 return; 882 883 aprint_naive("\n"); 884 aprint_normal(": RK3399 CRU\n"); 885 886 rk3399_cru_init(sc); 887 888 rk_cru_print(sc); 889 } 890
Indexes created Fri Oct 03 15:10:06 GMT 2025