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      1  1.6       ryo /* $NetBSD: rk_cru_pll.c,v 1.6 2022/08/23 05:39:06 ryo Exp $ */
      2  1.1  jmcneill 
      3  1.1  jmcneill /*-
      4  1.1  jmcneill  * Copyright (c) 2018 Jared McNeill <jmcneill (at) invisible.ca>
      5  1.1  jmcneill  * All rights reserved.
      6  1.1  jmcneill  *
      7  1.1  jmcneill  * Redistribution and use in source and binary forms, with or without
      8  1.1  jmcneill  * modification, are permitted provided that the following conditions
      9  1.1  jmcneill  * are met:
     10  1.1  jmcneill  * 1. Redistributions of source code must retain the above copyright
     11  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer.
     12  1.1  jmcneill  * 2. Redistributions in binary form must reproduce the above copyright
     13  1.1  jmcneill  *    notice, this list of conditions and the following disclaimer in the
     14  1.1  jmcneill  *    documentation and/or other materials provided with the distribution.
     15  1.1  jmcneill  *
     16  1.1  jmcneill  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  1.1  jmcneill  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  1.1  jmcneill  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  1.1  jmcneill  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  1.1  jmcneill  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  1.1  jmcneill  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  1.1  jmcneill  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  1.1  jmcneill  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  1.1  jmcneill  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  1.1  jmcneill  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  1.1  jmcneill  * SUCH DAMAGE.
     27  1.1  jmcneill  */
     28  1.1  jmcneill 
     29  1.1  jmcneill #include <sys/cdefs.h>
     30  1.6       ryo __KERNEL_RCSID(0, "$NetBSD: rk_cru_pll.c,v 1.6 2022/08/23 05:39:06 ryo Exp $");
     31  1.1  jmcneill 
     32  1.1  jmcneill #include <sys/param.h>
     33  1.1  jmcneill #include <sys/bus.h>
     34  1.1  jmcneill 
     35  1.1  jmcneill #include <dev/clk/clk_backend.h>
     36  1.1  jmcneill 
     37  1.1  jmcneill #include <arm/rockchip/rk_cru.h>
     38  1.1  jmcneill 
     39  1.1  jmcneill #define	PLL_CON0		0x00
     40  1.1  jmcneill #define	 PLL_BYPASS		__BIT(15)
     41  1.1  jmcneill #define	 PLL_POSTDIV1		__BITS(14,12)
     42  1.1  jmcneill #define	 PLL_FBDIV		__BITS(11,0)
     43  1.1  jmcneill 
     44  1.1  jmcneill #define	PLL_CON1		0x04
     45  1.1  jmcneill #define	 PLL_PDSEL		__BIT(15)
     46  1.1  jmcneill #define	 PLL_PD1		__BIT(14)
     47  1.1  jmcneill #define	 PLL_PD0		__BIT(13)
     48  1.1  jmcneill #define	 PLL_DSMPD		__BIT(12)
     49  1.1  jmcneill #define	 PLL_LOCK		__BIT(10)
     50  1.1  jmcneill #define	 PLL_POSTDIV2		__BITS(8,6)
     51  1.1  jmcneill #define	 PLL_REFDIV		__BITS(5,0)
     52  1.1  jmcneill 
     53  1.1  jmcneill #define	PLL_CON2		0x08
     54  1.1  jmcneill #define	 PLL_FOUT4PHASEPD	__BIT(27)
     55  1.1  jmcneill #define	 PLL_FOUTVCOPD		__BIT(26)
     56  1.1  jmcneill #define	 PLL_FOUTPOSTDIVPD	__BIT(25)
     57  1.1  jmcneill #define	 PLL_DACPD		__BIT(24)
     58  1.1  jmcneill #define	 PLL_FRACDIV		__BITS(23,0)
     59  1.1  jmcneill 
     60  1.5  jmcneill #define	PLL_CON3		0x0c
     61  1.6       ryo #define	PLL_CON6		0x18
     62  1.5  jmcneill 
     63  1.1  jmcneill #define	PLL_WRITE_MASK		0xffff0000	/* for CON0 and CON1 */
     64  1.1  jmcneill 
     65  1.5  jmcneill /* RK3288 CON0 */
     66  1.5  jmcneill #define	RK3288_CLKR		__BITS(13,8)
     67  1.5  jmcneill #define	RK3288_CLKOD		__BITS(3,0)
     68  1.5  jmcneill /* RK3288 CON1 */
     69  1.5  jmcneill #define	RK3288_LOCK		__BIT(31)
     70  1.5  jmcneill #define	RK3288_CLKF		__BITS(12,0)
     71  1.5  jmcneill /* RK3288 CON2 */
     72  1.5  jmcneill #define	RK3288_BWADJ		__BITS(11,0)
     73  1.5  jmcneill /* RK3288 CON3 */
     74  1.5  jmcneill #define	RK3288_BYPASS		__BIT(0)
     75  1.1  jmcneill 
     76  1.6       ryo #define RK3588_PLLCON0_M	__BITS(9,0)
     77  1.6       ryo #define RK3588_PLLCON1_P	__BITS(5,0)
     78  1.6       ryo #define RK3588_PLLCON1_S	__BITS(8,6)
     79  1.6       ryo #define RK3588_PLLCON2_K	__BITS(15,0)
     80  1.6       ryo #define RK3588_PLLCON1_PWRDOWN	__BIT(13)
     81  1.6       ryo #define RK3588_PLLCON6_LOCK	__BIT(15)
     82  1.6       ryo 
     83  1.6       ryo #define PLL_MODE_SLOW		0x0
     84  1.6       ryo #define PLL_MODE_NORM		0x1
     85  1.6       ryo 
     86  1.1  jmcneill u_int
     87  1.1  jmcneill rk_cru_pll_get_rate(struct rk_cru_softc *sc,
     88  1.1  jmcneill     struct rk_cru_clk *clk)
     89  1.1  jmcneill {
     90  1.1  jmcneill 	struct rk_cru_pll *pll = &clk->u.pll;
     91  1.1  jmcneill 	struct clk *clkp, *clkp_parent;
     92  1.1  jmcneill 	u_int foutvco, foutpostdiv;
     93  1.1  jmcneill 
     94  1.1  jmcneill 	KASSERT(clk->type == RK_CRU_PLL);
     95  1.1  jmcneill 
     96  1.1  jmcneill 	clkp = &clk->base;
     97  1.1  jmcneill 	clkp_parent = clk_get_parent(clkp);
     98  1.1  jmcneill 	if (clkp_parent == NULL)
     99  1.1  jmcneill 		return 0;
    100  1.1  jmcneill 
    101  1.1  jmcneill 	const u_int fref = clk_get_rate(clkp_parent);
    102  1.1  jmcneill 	if (fref == 0)
    103  1.1  jmcneill 		return 0;
    104  1.1  jmcneill 
    105  1.1  jmcneill 	const uint32_t con0 = CRU_READ(sc, pll->con_base + PLL_CON0);
    106  1.1  jmcneill 	const uint32_t con1 = CRU_READ(sc, pll->con_base + PLL_CON1);
    107  1.1  jmcneill 	const uint32_t con2 = CRU_READ(sc, pll->con_base + PLL_CON2);
    108  1.5  jmcneill 	const uint32_t con3 = CRU_READ(sc, pll->con_base + PLL_CON3);
    109  1.5  jmcneill 
    110  1.5  jmcneill 	if ((pll->flags & RK_PLL_RK3288) != 0) {
    111  1.5  jmcneill 		if ((con3 & RK3288_BYPASS) != 0) {
    112  1.5  jmcneill 			return fref;
    113  1.5  jmcneill 		}
    114  1.5  jmcneill 
    115  1.5  jmcneill 		const u_int nr = __SHIFTOUT(con0, RK3288_CLKR) + 1;
    116  1.5  jmcneill 		const u_int no = __SHIFTOUT(con0, RK3288_CLKOD) + 1;
    117  1.5  jmcneill 		const u_int nf = __SHIFTOUT(con1, RK3288_CLKF) + 1;
    118  1.5  jmcneill 
    119  1.5  jmcneill 		const uint64_t tmp = (uint64_t)fref * nf / nr / no;
    120  1.1  jmcneill 
    121  1.5  jmcneill 		return (u_int)tmp;
    122  1.6       ryo 	} else if ((pll->flags & RK_PLL_RK3588) != 0) {
    123  1.6       ryo 		const uint64_t m = __SHIFTOUT(con0, RK3588_PLLCON0_M);
    124  1.6       ryo 		const uint64_t p = __SHIFTOUT(con1, RK3588_PLLCON1_P);
    125  1.6       ryo 		const uint64_t s = __SHIFTOUT(con1, RK3588_PLLCON1_S);
    126  1.6       ryo 		const uint64_t k = __SHIFTOUT(con2, RK3588_PLLCON2_K);
    127  1.6       ryo 
    128  1.6       ryo 		uint64_t tmp = (uint64_t)fref * m;
    129  1.6       ryo 		if (p != 0)
    130  1.6       ryo 			tmp /= p;
    131  1.6       ryo 		if (k != 0 && p != 0)
    132  1.6       ryo 			tmp += ((uint64_t)fref * k) / (p * 65535);
    133  1.6       ryo 		tmp >>= s;
    134  1.6       ryo 		return (u_int)tmp;
    135  1.1  jmcneill 	} else {
    136  1.5  jmcneill 		const u_int postdiv1 = __SHIFTOUT(con0, PLL_POSTDIV1);
    137  1.5  jmcneill 		const u_int fbdiv = __SHIFTOUT(con0, PLL_FBDIV);
    138  1.5  jmcneill 		const u_int dsmpd = __SHIFTOUT(con1, PLL_DSMPD);
    139  1.5  jmcneill 		const u_int refdiv = __SHIFTOUT(con1, PLL_REFDIV);
    140  1.5  jmcneill 		const u_int postdiv2 = __SHIFTOUT(con1, PLL_POSTDIV2);
    141  1.5  jmcneill 		const u_int fracdiv = __SHIFTOUT(con2, PLL_FRACDIV);
    142  1.5  jmcneill 
    143  1.5  jmcneill 		if (dsmpd == 1) {
    144  1.5  jmcneill 			/* integer mode */
    145  1.5  jmcneill 			foutvco = fref / refdiv * fbdiv;
    146  1.5  jmcneill 		} else {
    147  1.5  jmcneill 			/* fractional mode */
    148  1.5  jmcneill 			foutvco = fref / refdiv * fbdiv + ((fref * fracdiv) >> 24);
    149  1.5  jmcneill 		}
    150  1.5  jmcneill 		foutpostdiv = foutvco / postdiv1 / postdiv2;
    151  1.5  jmcneill 
    152  1.5  jmcneill 		return foutpostdiv;
    153  1.1  jmcneill 	}
    154  1.1  jmcneill }
    155  1.1  jmcneill 
    156  1.1  jmcneill int
    157  1.1  jmcneill rk_cru_pll_set_rate(struct rk_cru_softc *sc,
    158  1.1  jmcneill     struct rk_cru_clk *clk, u_int rate)
    159  1.1  jmcneill {
    160  1.1  jmcneill 	struct rk_cru_pll *pll = &clk->u.pll;
    161  1.1  jmcneill 	const struct rk_cru_pll_rate *pll_rate = NULL;
    162  1.1  jmcneill 	uint32_t val;
    163  1.1  jmcneill 	int retry;
    164  1.1  jmcneill 
    165  1.1  jmcneill 	KASSERT(clk->type == RK_CRU_PLL);
    166  1.1  jmcneill 
    167  1.1  jmcneill 	if (pll->rates == NULL || rate == 0 || !HAS_GRF(sc))
    168  1.1  jmcneill 		return EIO;
    169  1.1  jmcneill 
    170  1.1  jmcneill 	for (int i = 0; i < pll->nrates; i++)
    171  1.1  jmcneill 		if (pll->rates[i].rate == rate) {
    172  1.1  jmcneill 			pll_rate = &pll->rates[i];
    173  1.1  jmcneill 			break;
    174  1.1  jmcneill 		}
    175  1.1  jmcneill 	if (pll_rate == NULL)
    176  1.1  jmcneill 		return EINVAL;
    177  1.1  jmcneill 
    178  1.6       ryo 	if ((pll->flags & RK_PLL_RK3288) != 0) {
    179  1.6       ryo 		/* XXX TODO */
    180  1.6       ryo 		KASSERT(false);
    181  1.6       ryo 	} else if ((pll->flags & RK_PLL_RK3588) != 0) {
    182  1.6       ryo 		bool muxed = false;
    183  1.6       ryo 
    184  1.6       ryo 		/* into SLOW mode */
    185  1.6       ryo 		if (__SHIFTOUT(CRU_READ(sc, pll->mode_reg), pll->mode_mask) ==
    186  1.6       ryo 		    PLL_MODE_NORM) {
    187  1.6       ryo 			CRU_WRITE(sc, pll->mode_reg,
    188  1.6       ryo 			    pll->mode_mask << 16 |
    189  1.6       ryo 			    __SHIFTIN(PLL_MODE_SLOW, pll->mode_mask));
    190  1.6       ryo 			muxed = true;
    191  1.6       ryo 		}
    192  1.6       ryo 
    193  1.6       ryo 		/* power down */
    194  1.6       ryo 		CRU_WRITE(sc, pll->con_base + PLL_CON1,
    195  1.6       ryo 		    RK3588_PLLCON1_PWRDOWN << 16 |
    196  1.6       ryo 		    __SHIFTIN(1, RK3588_PLLCON1_PWRDOWN));
    197  1.6       ryo 
    198  1.6       ryo 		/* update m,p,s,k */
    199  1.6       ryo 		CRU_WRITE(sc, pll->con_base + PLL_CON0,
    200  1.6       ryo 		    RK3588_PLLCON0_M << 16 |
    201  1.6       ryo 		    __SHIFTIN(pll_rate->m, RK3588_PLLCON0_M));
    202  1.6       ryo 		CRU_WRITE(sc, pll->con_base + PLL_CON1,
    203  1.6       ryo 		    RK3588_PLLCON1_P << 16 |
    204  1.6       ryo 		    RK3588_PLLCON1_S << 16 |
    205  1.6       ryo 		    __SHIFTIN(pll_rate->p, RK3588_PLLCON1_P) |
    206  1.6       ryo 		    __SHIFTIN(pll_rate->s, RK3588_PLLCON1_S));
    207  1.6       ryo 		CRU_WRITE(sc, pll->con_base + PLL_CON2,
    208  1.6       ryo 		    RK3588_PLLCON2_K << 16 |
    209  1.6       ryo 		    __SHIFTIN(pll_rate->k, RK3588_PLLCON2_K));
    210  1.6       ryo 
    211  1.6       ryo 		/* power up */
    212  1.6       ryo 		CRU_WRITE(sc, pll->con_base + PLL_CON1,
    213  1.6       ryo 		    RK3588_PLLCON1_PWRDOWN << 16 |
    214  1.6       ryo 		    __SHIFTIN(0, RK3588_PLLCON1_PWRDOWN));
    215  1.6       ryo 
    216  1.6       ryo 		/* wait */
    217  1.6       ryo 		for (retry = 1000; retry > 0; retry--) {
    218  1.6       ryo 			if (CRU_READ(sc, pll->con_base + PLL_CON6) &
    219  1.6       ryo 			    pll->lock_mask) {
    220  1.6       ryo 				break;
    221  1.6       ryo 			}
    222  1.6       ryo 			delay(1);
    223  1.6       ryo 		}
    224  1.6       ryo 		if (retry == 0)
    225  1.6       ryo 			device_printf(sc->sc_dev,
    226  1.6       ryo 			    "WARNING: %s failed to lock\n", clk->base.name);
    227  1.6       ryo 
    228  1.6       ryo 		/* into NORM mode */
    229  1.6       ryo 		if (muxed) {
    230  1.6       ryo 			CRU_WRITE(sc, pll->mode_reg,
    231  1.6       ryo 			    pll->mode_mask << 16 |
    232  1.6       ryo 			    __SHIFTIN(PLL_MODE_NORM, pll->mode_mask));
    233  1.6       ryo 		}
    234  1.6       ryo 	} else {
    235  1.6       ryo 		CRU_WRITE(sc, pll->con_base + PLL_CON0,
    236  1.6       ryo 		    __SHIFTIN(pll_rate->postdiv1, PLL_POSTDIV1) |
    237  1.6       ryo 		    __SHIFTIN(pll_rate->fbdiv, PLL_FBDIV) |
    238  1.6       ryo 		    PLL_WRITE_MASK);
    239  1.6       ryo 
    240  1.6       ryo 		CRU_WRITE(sc, pll->con_base + PLL_CON1,
    241  1.6       ryo 		    __SHIFTIN(pll_rate->dsmpd, PLL_DSMPD) |
    242  1.6       ryo 		    __SHIFTIN(pll_rate->postdiv2, PLL_POSTDIV2) |
    243  1.6       ryo 		    __SHIFTIN(pll_rate->refdiv, PLL_REFDIV) |
    244  1.6       ryo 		    PLL_WRITE_MASK);
    245  1.6       ryo 
    246  1.6       ryo 		val = CRU_READ(sc, pll->con_base + PLL_CON2);
    247  1.6       ryo 		val &= ~PLL_FRACDIV;
    248  1.6       ryo 		val |= __SHIFTIN(pll_rate->fracdiv, PLL_FRACDIV);
    249  1.6       ryo 		CRU_WRITE(sc, pll->con_base + PLL_CON2, val);
    250  1.6       ryo 
    251  1.6       ryo 		/* Set PLL work mode to normal */
    252  1.6       ryo 		const uint32_t write_mask = pll->mode_mask << 16;
    253  1.6       ryo 		const uint32_t write_val = pll->mode_mask;
    254  1.6       ryo 		CRU_WRITE(sc, pll->mode_reg, write_mask | write_val);
    255  1.6       ryo 
    256  1.6       ryo 		syscon_lock(sc->sc_grf);
    257  1.6       ryo 		for (retry = 1000; retry > 0; retry--) {
    258  1.6       ryo 			if (syscon_read_4(sc->sc_grf,
    259  1.6       ryo 			    sc->sc_grf_soc_status) & pll->lock_mask)
    260  1.6       ryo 				break;
    261  1.6       ryo 			delay(1);
    262  1.6       ryo 		}
    263  1.6       ryo 		syscon_unlock(sc->sc_grf);
    264  1.5  jmcneill 
    265  1.6       ryo 		if (retry == 0)
    266  1.6       ryo 			device_printf(sc->sc_dev,
    267  1.6       ryo 			    "WARNING: %s failed to lock\n", clk->base.name);
    268  1.1  jmcneill 	}
    269  1.1  jmcneill 
    270  1.1  jmcneill 	return 0;
    271  1.1  jmcneill }
    272  1.1  jmcneill 
    273  1.1  jmcneill const char *
    274  1.1  jmcneill rk_cru_pll_get_parent(struct rk_cru_softc *sc,
    275  1.1  jmcneill     struct rk_cru_clk *clk)
    276  1.1  jmcneill {
    277  1.1  jmcneill 	struct rk_cru_pll *pll = &clk->u.pll;
    278  1.1  jmcneill 
    279  1.1  jmcneill 	KASSERT(clk->type == RK_CRU_PLL);
    280  1.1  jmcneill 
    281  1.4  jmcneill 	return pll->parents[0];
    282  1.1  jmcneill }
    283