1 /* $NetBSD: s3c2800_clk.c,v 1.18 2020/05/29 12:30:39 rin Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: s3c2800_clk.c,v 1.18 2020/05/29 12:30:39 rin Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/atomic.h> 43 #include <sys/time.h> 44 #include <sys/timetc.h> 45 46 #include <sys/bus.h> 47 #include <machine/intr.h> 48 #include <arm/cpufunc.h> 49 50 #include <arm/s3c2xx0/s3c2800reg.h> 51 #include <arm/s3c2xx0/s3c2800var.h> 52 53 54 #ifndef STATHZ 55 #define STATHZ 64 56 #endif 57 58 #define TIMER_FREQUENCY(pclk) ((pclk)/32) /* divider=1/32 */ 59 60 static unsigned int timer0_reload_value; 61 static unsigned int timer0_prescaler; 62 static unsigned int timer0_mseccount; 63 64 #define usec_to_counter(t) \ 65 ((timer0_mseccount*(t))/1000) 66 67 #define counter_to_usec(c,pclk) \ 68 (((c)*timer0_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000)) 69 70 static u_int s3c2800_get_timecount(struct timecounter *); 71 72 static struct timecounter s3c2800_timecounter = { 73 .tc_get_timecount = s3c2800_get_timecount, 74 .tc_counter_mask = 0xffffffff, 75 .tc_name = "s3c2800", 76 .tc_quality = 100, 77 }; 78 79 static volatile uint32_t s3c2800_base; 80 81 static u_int 82 s3c2800_get_timecount(struct timecounter *tc) 83 { 84 struct s3c2800_softc *sc = (struct s3c2800_softc *) s3c2xx0_softc; 85 int save, int_pend0, int_pend1, count; 86 87 save = disable_interrupts(I32_bit); 88 89 again: 90 int_pend0 = S3C2800_INT_TIMER0 & 91 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 92 INTCTL_SRCPND); 93 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, 94 TIMER_TMCNT); 95 96 for (;;){ 97 98 int_pend1 = S3C2800_INT_TIMER0 & 99 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 100 INTCTL_SRCPND); 101 if( int_pend0 == int_pend1 ) 102 break; 103 104 /* 105 * Down counter reached to zero while we were reading 106 * timer values. do it again to get consistent values. 107 */ 108 int_pend0 = int_pend1; 109 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, 110 TIMER_TMCNT); 111 } 112 113 if( __predict_false(count > timer0_reload_value) ){ 114 /* 115 * Buggy Hardware Warning --- sometimes timer counter 116 * reads bogus value like 0xffff. I guess it happens when 117 * the timer is reloaded. 118 */ 119 #if 0 120 printf( "Bogus value from timer counter: %d\n", count ); 121 #endif 122 goto again; 123 } 124 125 restore_interrupts(save); 126 127 if (int_pend1) 128 count -= timer0_reload_value; 129 130 return s3c2800_base - count; 131 } 132 133 static inline int 134 read_timer(struct s3c2800_softc *sc) 135 { 136 int count; 137 138 do { 139 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, 140 TIMER_TMCNT); 141 } while ( __predict_false(count > timer0_reload_value) ); 142 143 return count; 144 } 145 146 /* 147 * delay: 148 * 149 * Delay for at least N microseconds. 150 */ 151 void 152 delay(u_int n) 153 { 154 struct s3c2800_softc *sc = (struct s3c2800_softc *) s3c2xx0_softc; 155 int v0, v1, delta; 156 u_int ucnt; 157 158 if ( timer0_reload_value == 0 ){ 159 /* not initialized yet */ 160 while ( n-- > 0 ){ 161 int m; 162 163 for (m=0; m<100; ++m ) 164 ; 165 } 166 return; 167 } 168 169 /* read down counter */ 170 v0 = read_timer(sc); 171 172 ucnt = usec_to_counter(n); 173 174 while( ucnt > 0 ) { 175 v1 = read_timer(sc); 176 delta = v0 - v1; 177 if ( delta < 0 ) 178 delta += timer0_reload_value; 179 #ifdef DEBUG 180 if (delta < 0 || delta > timer0_reload_value) 181 panic("wrong value from timer counter"); 182 #endif 183 184 if((u_int)delta < ucnt){ 185 ucnt -= (u_int)delta; 186 v0 = v1; 187 } 188 else { 189 ucnt = 0; 190 } 191 } 192 /*NOTREACHED*/ 193 } 194 195 void 196 setstatclockrate(int newhz) 197 { 198 } 199 200 static int 201 hardintr(void *arg) 202 { 203 atomic_add_32(&s3c2800_base, timer0_reload_value); 204 205 hardclock((struct clockframe *)arg); 206 207 return 1; 208 } 209 210 static int 211 statintr(void *arg) 212 { 213 statclock((struct clockframe *)arg); 214 215 return 1; 216 } 217 218 void 219 cpu_initclocks(void) 220 { 221 struct s3c2800_softc *sc = (struct s3c2800_softc *)s3c2xx0_softc; 222 long tc; 223 int prescaler; 224 int pclk = s3c2xx0_softc->sc_pclk; 225 226 stathz = STATHZ; 227 profhz = stathz; 228 229 #define calc_time_constant(hz) \ 230 do { \ 231 prescaler = 1; \ 232 do { \ 233 ++prescaler; \ 234 tc = TIMER_FREQUENCY(pclk) /(hz)/ prescaler; \ 235 } while( tc > 65536 ); \ 236 } while(0) 237 238 239 240 /* Use the channels 0 and 1 for hardclock and statclock, respectively */ 241 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMCON, 0); 242 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMCON, 0); 243 244 calc_time_constant(hz); 245 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMDAT, 246 ((prescaler - 1) << 16) | (tc - 1)); 247 timer0_prescaler = prescaler; 248 timer0_reload_value = tc; 249 timer0_mseccount = TIMER_FREQUENCY(pclk)/timer0_prescaler/1000 ; 250 251 printf("clock: hz=%d stathz = %d PCLK=%d prescaler=%d tc=%ld\n", 252 hz, stathz, pclk, prescaler, tc); 253 254 calc_time_constant(stathz); 255 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMDAT, 256 ((prescaler - 1) << 16) | (tc - 1)); 257 258 259 s3c2800_intr_establish(S3C2800_INT_TIMER0, IPL_CLOCK, 260 IST_NONE, hardintr, 0); 261 s3c2800_intr_establish(S3C2800_INT_TIMER1, IPL_HIGH, 262 IST_NONE, statintr, 0); 263 264 /* start timers */ 265 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMCON, 266 TMCON_MUX_DIV32|TMCON_INTENA|TMCON_ENABLE); 267 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMCON, 268 TMCON_MUX_DIV4|TMCON_INTENA|TMCON_ENABLE); 269 270 /* stop timer2 */ 271 { 272 bus_space_handle_t tmp_ioh; 273 274 bus_space_map(sc->sc_sx.sc_iot, S3C2800_TIMER2_BASE, 275 S3C2800_TIMER_SIZE, 0, &tmp_ioh); 276 277 bus_space_write_4(sc->sc_sx.sc_iot, tmp_ioh, 278 TIMER_TMCON, 0); 279 280 bus_space_unmap(sc->sc_sx.sc_iot, tmp_ioh, 281 S3C2800_TIMER_SIZE); 282 283 } 284 285 s3c2800_timecounter.tc_frequency = TIMER_FREQUENCY(pclk) / timer0_prescaler; 286 tc_init(&s3c2800_timecounter); 287 } 288
Indexes created Sat Sep 20 22:09:52 GMT 2025