s3c2800_clk.c revision 1.12
1 /* $NetBSD: s3c2800_clk.c,v 1.12 2008/01/20 16:28:23 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: s3c2800_clk.c,v 1.12 2008/01/20 16:28:23 joerg Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/atomic.h> 43 #include <sys/time.h> 44 #include <sys/timetc.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 #include <arm/cpufunc.h> 49 50 #include <arm/s3c2xx0/s3c2800reg.h> 51 #include <arm/s3c2xx0/s3c2800var.h> 52 53 54 #ifndef STATHZ 55 #define STATHZ 64 56 #endif 57 58 #define TIMER_FREQUENCY(pclk) ((pclk)/32) /* divider=1/32 */ 59 60 static unsigned int timer0_reload_value; 61 static unsigned int timer0_prescaler; 62 static unsigned int timer0_mseccount; 63 64 #define usec_to_counter(t) \ 65 ((timer0_mseccount*(t))/1000) 66 67 #define counter_to_usec(c,pclk) \ 68 (((c)*timer0_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000)) 69 70 static u_int s3c2800_get_timecount(struct timecounter *); 71 72 static struct timecounter s3c2800_timecounter = { 73 s3c2800_get_timecount, /* get_timecount */ 74 0, /* no poll_pps */ 75 0xffffffff, /* counter_mask */ 76 0, /* frequency */ 77 "s3c23800", /* name */ 78 100, /* quality */ 79 NULL, /* prev */ 80 NULL, /* next */ 81 }; 82 83 static volatile uint32_t s3c2800_base; 84 85 static u_int 86 s3c2800_get_timecount(struct timecounter *tc) 87 { 88 struct s3c2800_softc *sc = (struct s3c2800_softc *) s3c2xx0_softc; 89 int save, int_pend0, int_pend1, count; 90 91 save = disable_interrupts(I32_bit); 92 93 again: 94 int_pend0 = S3C2800_INT_TIMER0 & 95 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 96 INTCTL_SRCPND); 97 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, 98 TIMER_TMCNT); 99 100 for (;;){ 101 102 int_pend1 = S3C2800_INT_TIMER0 & 103 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 104 INTCTL_SRCPND); 105 if( int_pend0 == int_pend1 ) 106 break; 107 108 /* 109 * Down counter reached to zero while we were reading 110 * timer values. do it again to get consistent values. 111 */ 112 int_pend0 = int_pend1; 113 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, 114 TIMER_TMCNT); 115 } 116 117 if( __predict_false(count > timer0_reload_value) ){ 118 /* 119 * Buggy Hardware Warning --- sometimes timer counter 120 * reads bogus value like 0xffff. I guess it happens when 121 * the timer is reloaded. 122 */ 123 #if 0 124 printf( "Bogus value from timer counter: %d\n", count ); 125 #endif 126 goto again; 127 } 128 129 restore_interrupts(save); 130 131 if (int_pend1) 132 count -= timer0_reload_value; 133 134 return s3c2800_base - count; 135 } 136 137 static inline int 138 read_timer(struct s3c2800_softc *sc) 139 { 140 int count; 141 142 do { 143 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, 144 TIMER_TMCNT); 145 } while ( __predict_false(count > timer0_reload_value) ); 146 147 return count; 148 } 149 150 /* 151 * delay: 152 * 153 * Delay for at least N microseconds. 154 */ 155 void 156 delay(u_int n) 157 { 158 struct s3c2800_softc *sc = (struct s3c2800_softc *) s3c2xx0_softc; 159 int v0, v1, delta; 160 u_int ucnt; 161 162 if ( timer0_reload_value == 0 ){ 163 /* not initialized yet */ 164 while ( n-- > 0 ){ 165 int m; 166 167 for (m=0; m<100; ++m ) 168 ; 169 } 170 return; 171 } 172 173 /* read down counter */ 174 v0 = read_timer(sc); 175 176 ucnt = usec_to_counter(n); 177 178 while( ucnt > 0 ) { 179 v1 = read_timer(sc); 180 delta = v0 - v1; 181 if ( delta < 0 ) 182 delta += timer0_reload_value; 183 #ifdef DEBUG 184 if (delta < 0 || delta > timer0_reload_value) 185 panic("wrong value from timer counter"); 186 #endif 187 188 if((u_int)delta < ucnt){ 189 ucnt -= (u_int)delta; 190 v0 = v1; 191 } 192 else { 193 ucnt = 0; 194 } 195 } 196 /*NOTREACHED*/ 197 } 198 199 void 200 setstatclockrate(int newhz) 201 { 202 } 203 204 static int 205 hardintr(void *arg) 206 { 207 atomic_add_32(&s3c2800_base, timer4_reload_value); 208 209 hardclock((struct clockframe *)arg); 210 211 return 1; 212 } 213 214 void 215 cpu_initclocks() 216 { 217 struct s3c2800_softc *sc = (struct s3c2800_softc *)s3c2xx0_softc; 218 long tc; 219 int prescaler; 220 int pclk = s3c2xx0_softc->sc_pclk; 221 222 stathz = STATHZ; 223 profhz = stathz; 224 225 #define calc_time_constant(hz) \ 226 do { \ 227 prescaler = 1; \ 228 do { \ 229 ++prescaler; \ 230 tc = TIMER_FREQUENCY(pclk) /(hz)/ prescaler; \ 231 } while( tc > 65536 ); \ 232 } while(0) 233 234 235 236 /* Use the channels 0 and 1 for hardclock and statclock, respectively */ 237 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMCON, 0); 238 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMCON, 0); 239 240 calc_time_constant(hz); 241 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMDAT, 242 ((prescaler - 1) << 16) | (tc - 1)); 243 timer0_prescaler = prescaler; 244 timer0_reload_value = tc; 245 timer0_mseccount = TIMER_FREQUENCY(pclk)/timer0_prescaler/1000 ; 246 247 printf("clock: hz=%d stathz = %d PCLK=%d prescaler=%d tc=%ld\n", 248 hz, stathz, pclk, prescaler, tc); 249 250 calc_time_constant(stathz); 251 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMDAT, 252 ((prescaler - 1) << 16) | (tc - 1)); 253 254 255 s3c2800_intr_establish(S3C2800_INT_TIMER0, IPL_CLOCK, 256 IST_NONE, hardintr, 0); 257 s3c2800_intr_establish(S3C2800_INT_TIMER1, IPL_HIGH, 258 IST_NONE, statintr, 0); 259 260 /* start timers */ 261 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMCON, 262 TMCON_MUX_DIV32|TMCON_INTENA|TMCON_ENABLE); 263 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMCON, 264 TMCON_MUX_DIV4|TMCON_INTENA|TMCON_ENABLE); 265 266 /* stop timer2 */ 267 { 268 bus_space_handle_t tmp_ioh; 269 270 bus_space_map(sc->sc_sx.sc_iot, S3C2800_TIMER2_BASE, 271 S3C2800_TIMER_SIZE, 0, &tmp_ioh); 272 273 bus_space_write_4(sc->sc_sx.sc_iot, tmp_ioh, 274 TIMER_TMCON, 0); 275 276 bus_space_unmap(sc->sc_sx.sc_iot, tmp_ioh, 277 S3C2800_TIMER_SIZE); 278 279 } 280 281 s3c2800_timecounter.tc_frequency = pclk; 282 tc_init(&s3c2800_timecounter); 283 } 284
Indexes created Tue Sep 30 11:09:46 GMT 2025