s3c2800_clk.c revision 1.5
1 /* $NetBSD: s3c2800_clk.c,v 1.5 2003/07/15 00:24:48 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2002 Fujitsu Component Limited 5 * Copyright (c) 2002 Genetec Corporation 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of The Fujitsu Component Limited nor the name of 17 * Genetec corporation may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC 21 * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 22 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC 25 * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 36 /* 37 * Clock & Power Management 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: s3c2800_clk.c,v 1.5 2003/07/15 00:24:48 lukem Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/kernel.h> 46 #include <sys/time.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 #include <arm/cpufunc.h> 51 52 #include <arm/s3c2xx0/s3c2800reg.h> 53 #include <arm/s3c2xx0/s3c2800var.h> 54 55 56 #ifndef STATHZ 57 #define STATHZ 64 58 #endif 59 60 #define TIMER_FREQUENCY(pclk) ((pclk)/32) /* divider=1/32 */ 61 62 #define TIMER_RELOAD_VAL 1000 63 #define COUNTS_PER_USEC 100 64 65 static unsigned int timer0_reload_value; 66 static unsigned int timer0_prescaler; 67 static unsigned int timer0_mseccount; 68 69 #define usec_to_counter(t) \ 70 ((timer0_mseccount*(t))/1000) 71 72 #define counter_to_usec(c,pclk) \ 73 (((c)*timer0_prescaler*1000)/(TIMER_FREQUENCY(pclk)/1000)) 74 75 /* 76 * microtime: 77 * 78 * Fill in the specified timeval struct with the current time 79 * accurate to the microsecond. 80 */ 81 void 82 microtime(struct timeval *tvp) 83 { 84 struct s3c2800_softc *sc = (struct s3c2800_softc *) s3c2xx0_softc; 85 int save, int_pend0, int_pend1, count, delta; 86 static struct timeval last; 87 int pclk = s3c2xx0_softc->sc_pclk; 88 89 if( timer0_reload_value == 0 ){ 90 /* not initialized yet */ 91 tvp->tv_sec = 0; 92 tvp->tv_usec = 0; 93 return; 94 } 95 96 save = disable_interrupts(I32_bit); 97 98 again: 99 int_pend0 = S3C2800_INT_TIMER0 & 100 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 101 INTCTL_SRCPND); 102 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, 103 TIMER_TMCNT); 104 105 for (;;){ 106 107 int_pend1 = S3C2800_INT_TIMER0 & 108 bus_space_read_4(sc->sc_sx.sc_iot, sc->sc_sx.sc_intctl_ioh, 109 INTCTL_SRCPND); 110 if( int_pend0 == int_pend1 ) 111 break; 112 113 /* 114 * Down counter reached to zero while we were reading 115 * timer values. do it again to get consistent values. 116 */ 117 int_pend0 = int_pend1; 118 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, 119 TIMER_TMCNT); 120 } 121 122 if( __predict_false(count > timer0_reload_value) ){ 123 /* 124 * Buggy Hardware Warning --- sometimes timer counter 125 * reads bogus value like 0xffff. I guess it happens when 126 * the timer is reloaded. 127 */ 128 #if 0 129 printf( "Bogus value from timer counter: %d\n", count ); 130 #endif 131 goto again; 132 } 133 134 /* copy system time */ 135 *tvp = time; 136 137 restore_interrupts(save); 138 139 delta = timer0_reload_value - count; 140 141 if( int_pend1 ){ 142 /* 143 * down counter underflow, but 144 * clock interrupt have not serviced yet 145 */ 146 #if 1 147 tvp->tv_usec += tick; 148 #else 149 delta = 0; 150 #endif 151 } 152 153 tvp->tv_usec += counter_to_usec(delta, pclk); 154 155 /* Make sure microseconds doesn't overflow. */ 156 tvp->tv_sec += tvp->tv_usec / 1000000; 157 tvp->tv_usec = tvp->tv_usec % 1000000; 158 159 if (last.tv_sec && 160 (tvp->tv_sec < last.tv_sec || 161 (tvp->tv_sec == last.tv_sec && 162 tvp->tv_usec < last.tv_usec) ) ){ 163 164 /* XXX: This happens very often when the kernel runs 165 under Multi-ICE */ 166 #if 0 167 printf("time reversal: %ld.%06ld(%d,%d) -> %ld.%06ld(%d,%d)\n", 168 last.tv_sec, last.tv_usec, 169 last_count, last_pend, 170 tvp->tv_sec, tvp->tv_usec, 171 count, int_pend1 ); 172 #endif 173 174 /* make sure the time has advanced. */ 175 *tvp = last; 176 tvp->tv_usec++; 177 if( tvp->tv_usec >= 1000000 ){ 178 tvp->tv_usec -= 1000000; 179 tvp->tv_sec++; 180 } 181 } 182 183 last = *tvp; 184 } 185 186 static __inline int 187 read_timer(struct s3c2800_softc *sc) 188 { 189 int count; 190 191 do { 192 count = bus_space_read_2(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, 193 TIMER_TMCNT); 194 } while ( __predict_false(count > timer0_reload_value) ); 195 196 return count; 197 } 198 199 /* 200 * delay: 201 * 202 * Delay for at least N microseconds. 203 */ 204 void 205 delay(u_int n) 206 { 207 struct s3c2800_softc *sc = (struct s3c2800_softc *) s3c2xx0_softc; 208 int v0, v1, delta; 209 u_int ucnt; 210 211 if ( timer0_reload_value == 0 ){ 212 /* not initialized yet */ 213 while ( n-- > 0 ){ 214 int m; 215 216 for (m=0; m<100; ++m ) 217 ; 218 } 219 return; 220 } 221 222 /* read down counter */ 223 v0 = read_timer(sc); 224 225 ucnt = usec_to_counter(n); 226 227 while( ucnt > 0 ) { 228 v1 = read_timer(sc); 229 delta = v0 - v1; 230 if ( delta < 0 ) 231 delta += timer0_reload_value; 232 #ifdef DEBUG 233 if (delta < 0 || delta > timer0_reload_value) 234 panic("wrong value from timer counter"); 235 #endif 236 237 if((u_int)delta < ucnt){ 238 ucnt -= (u_int)delta; 239 v0 = v1; 240 } 241 else { 242 ucnt = 0; 243 } 244 } 245 /*NOTREACHED*/ 246 } 247 248 /* 249 * inittodr: 250 * 251 * Initialize time from the time-of-day register. 252 */ 253 void 254 inittodr(time_t base) 255 { 256 257 time.tv_sec = base; 258 time.tv_usec = 0; 259 } 260 261 /* 262 * resettodr: 263 * 264 * Reset the time-of-day register with the current time. 265 */ 266 void 267 resettodr(void) 268 { 269 } 270 271 void 272 setstatclockrate(hz) 273 int hz; 274 { 275 } 276 277 278 #define hardintr (int (*)(void *))hardclock 279 #define statintr (int (*)(void *))statclock 280 281 void 282 cpu_initclocks() 283 { 284 struct s3c2800_softc *sc = (struct s3c2800_softc *)s3c2xx0_softc; 285 long tc; 286 int prescaler; 287 int pclk = s3c2xx0_softc->sc_pclk; 288 289 stathz = STATHZ; 290 profhz = stathz; 291 292 #define calc_time_constant(hz) \ 293 do { \ 294 prescaler = 1; \ 295 do { \ 296 ++prescaler; \ 297 tc = TIMER_FREQUENCY(pclk) /(hz)/ prescaler; \ 298 } while( tc > 65536 ); \ 299 } while(0) 300 301 302 303 /* Use the channels 0 and 1 for hardclock and statclock, respectively */ 304 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMCON, 0); 305 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMCON, 0); 306 307 calc_time_constant(hz); 308 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMDAT, 309 ((prescaler - 1) << 16) | (tc - 1)); 310 timer0_prescaler = prescaler; 311 timer0_reload_value = tc; 312 timer0_mseccount = TIMER_FREQUENCY(pclk)/timer0_prescaler/1000 ; 313 314 printf("clock: hz=%d stathz = %d PCLK=%d prescaler=%d tc=%ld\n", 315 hz, stathz, pclk, prescaler, tc); 316 317 calc_time_constant(stathz); 318 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMDAT, 319 ((prescaler - 1) << 16) | (tc - 1)); 320 321 322 s3c2800_intr_establish(S3C2800_INT_TIMER0, IPL_CLOCK, 323 IST_NONE, hardintr, 0); 324 s3c2800_intr_establish(S3C2800_INT_TIMER1, IPL_STATCLOCK, 325 IST_NONE, statintr, 0); 326 327 /* start timers */ 328 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr0_ioh, TIMER_TMCON, 329 TMCON_MUX_DIV32|TMCON_INTENA|TMCON_ENABLE); 330 bus_space_write_4(sc->sc_sx.sc_iot, sc->sc_tmr1_ioh, TIMER_TMCON, 331 TMCON_MUX_DIV4|TMCON_INTENA|TMCON_ENABLE); 332 333 /* stop timer2 */ 334 { 335 bus_space_handle_t tmp_ioh; 336 337 bus_space_map(sc->sc_sx.sc_iot, S3C2800_TIMER2_BASE, 338 S3C2800_TIMER_SIZE, 0, &tmp_ioh); 339 340 bus_space_write_4(sc->sc_sx.sc_iot, tmp_ioh, 341 TIMER_TMCON, 0); 342 343 bus_space_unmap(sc->sc_sx.sc_iot, tmp_ioh, 344 S3C2800_TIMER_SIZE); 345 346 } 347 } 348
Indexes created Mon Sep 29 21:09:56 GMT 2025