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s3c2800_intr.c revision 1.4.2.2
      1  1.4.2.1  skrll /* $NetBSD: s3c2800_intr.c,v 1.4.2.2 2004/09/18 14:32:38 skrll Exp $ */
      2      1.1    bsh 
      3      1.1    bsh /*
      4      1.1    bsh  * Copyright (c) 2002 Fujitsu Component Limited
      5      1.1    bsh  * Copyright (c) 2002 Genetec Corporation
      6      1.1    bsh  * All rights reserved.
      7      1.1    bsh  *
      8      1.1    bsh  * Redistribution and use in source and binary forms, with or without
      9      1.1    bsh  * modification, are permitted provided that the following conditions
     10      1.1    bsh  * are met:
     11      1.1    bsh  * 1. Redistributions of source code must retain the above copyright
     12      1.1    bsh  *    notice, this list of conditions and the following disclaimer.
     13      1.1    bsh  * 2. Redistributions in binary form must reproduce the above copyright
     14      1.1    bsh  *    notice, this list of conditions and the following disclaimer in the
     15      1.1    bsh  *    documentation and/or other materials provided with the distribution.
     16      1.1    bsh  * 3. Neither the name of The Fujitsu Component Limited nor the name of
     17      1.1    bsh  *    Genetec corporation may not be used to endorse or promote products
     18      1.1    bsh  *    derived from this software without specific prior written permission.
     19      1.1    bsh  *
     20      1.1    bsh  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
     21      1.1    bsh  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
     22      1.1    bsh  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     23      1.1    bsh  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     24      1.1    bsh  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
     25      1.1    bsh  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     26      1.1    bsh  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     27      1.1    bsh  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
     28      1.1    bsh  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     29      1.1    bsh  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     30      1.1    bsh  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
     31      1.1    bsh  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32      1.1    bsh  * SUCH DAMAGE.
     33      1.1    bsh  */
     34      1.1    bsh 
     35      1.1    bsh /*
     36      1.1    bsh  * IRQ handler for Samsung S3C2800 processor.
     37      1.1    bsh  * It has integrated interrupt controller.
     38      1.1    bsh  */
     39  1.4.2.1  skrll 
     40  1.4.2.1  skrll #include <sys/cdefs.h>
     41  1.4.2.1  skrll __KERNEL_RCSID(0, "$NetBSD: s3c2800_intr.c,v 1.4.2.2 2004/09/18 14:32:38 skrll Exp $");
     42  1.4.2.1  skrll 
     43      1.1    bsh #include <sys/param.h>
     44      1.1    bsh #include <sys/systm.h>
     45      1.1    bsh #include <sys/malloc.h>
     46      1.1    bsh #include <uvm/uvm_extern.h>
     47      1.1    bsh #include <machine/bus.h>
     48      1.1    bsh #include <machine/intr.h>
     49      1.1    bsh #include <arm/cpufunc.h>
     50      1.1    bsh 
     51      1.1    bsh #include <arm/s3c2xx0/s3c2800reg.h>
     52      1.1    bsh #include <arm/s3c2xx0/s3c2800var.h>
     53      1.1    bsh 
     54      1.1    bsh /*
     55      1.1    bsh  * interrupt dispatch table.
     56      1.1    bsh  */
     57      1.1    bsh 
     58      1.1    bsh struct s3c2xx0_intr_dispatch handler[ICU_LEN];
     59      1.1    bsh 
     60      1.1    bsh __volatile int softint_pending;
     61      1.1    bsh 
     62      1.1    bsh __volatile int current_spl_level;
     63  1.4.2.1  skrll __volatile int intr_mask;    /* XXX: does this need to be volatile? */
     64  1.4.2.1  skrll __volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */
     65      1.1    bsh 
     66      1.1    bsh /* interrupt masks for each level */
     67      1.1    bsh int s3c2xx0_imask[NIPL];
     68      1.1    bsh int s3c2xx0_ilevel[ICU_LEN];
     69      1.1    bsh 
     70      1.1    bsh vaddr_t intctl_base;		/* interrupt controller registers */
     71      1.1    bsh #define icreg(offset) \
     72      1.1    bsh 	(*(volatile uint32_t *)(intctl_base+(offset)))
     73      1.1    bsh 
     74      1.1    bsh /*
     75      1.1    bsh  * Map a software interrupt queue to an interrupt priority level.
     76      1.1    bsh  */
     77      1.1    bsh static const int si_to_ipl[SI_NQUEUES] = {
     78      1.1    bsh 	IPL_SOFT,		/* SI_SOFT */
     79      1.1    bsh 	IPL_SOFTCLOCK,		/* SI_SOFTCLOCK */
     80      1.1    bsh 	IPL_SOFTNET,		/* SI_SOFTNET */
     81      1.1    bsh 	IPL_SOFTSERIAL,		/* SI_SOFTSERIAL */
     82      1.1    bsh };
     83      1.4    bsh 
     84      1.4    bsh /*
     85      1.4    bsh  *   Clearing interrupt pending bits affects some built-in
     86      1.4    bsh  * peripherals.  For example, IIC starts transmitting next data when
     87      1.4    bsh  * its interrupt pending bit is cleared.
     88      1.4    bsh  *   We need to leave those bits to peripheral handlers.
     89      1.4    bsh  */
     90      1.4    bsh #define PENDING_CLEAR_MASK	(~((1<<S3C2800_INT_IIC0)|(1<<S3C2800_INT_IIC1)))
     91      1.4    bsh 
     92      1.1    bsh /*
     93      1.1    bsh  * called from irq_entry.
     94      1.1    bsh  */
     95      1.1    bsh void s3c2800_irq_handler(struct clockframe *);
     96      1.1    bsh void
     97      1.1    bsh s3c2800_irq_handler(struct clockframe *frame)
     98      1.1    bsh {
     99      1.1    bsh 	uint32_t irqbits;
    100      1.1    bsh 	int irqno;
    101      1.1    bsh 	int saved_spl_level;
    102      1.1    bsh 
    103      1.1    bsh 	saved_spl_level = current_spl_level;
    104      1.1    bsh 
    105  1.4.2.1  skrll 	while ((irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK) != 0) {
    106  1.4.2.1  skrll 
    107  1.4.2.1  skrll 		for (irqno = ICU_LEN-1; irqno >= 0; --irqno)
    108  1.4.2.1  skrll 			if (irqbits & (1<<irqno))
    109  1.4.2.1  skrll 				break;
    110  1.4.2.1  skrll 
    111  1.4.2.1  skrll 		if (irqno < 0)
    112  1.4.2.1  skrll 			break;
    113      1.1    bsh 
    114      1.1    bsh 		/* raise spl to stop interrupts of lower priorities */
    115      1.1    bsh 		if (saved_spl_level < handler[irqno].level)
    116      1.1    bsh 			s3c2xx0_setipl(handler[irqno].level);
    117      1.1    bsh 
    118      1.1    bsh 		/* clear pending bit */
    119      1.4    bsh 		icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno);
    120  1.4.2.1  skrll 
    121  1.4.2.1  skrll 		enable_interrupts(I32_bit); /* allow nested interrupts */
    122  1.4.2.1  skrll 
    123      1.1    bsh 		(*handler[irqno].func) (
    124      1.1    bsh 		    handler[irqno].cookie == 0
    125      1.1    bsh 		    ? frame : handler[irqno].cookie);
    126      1.1    bsh 
    127  1.4.2.1  skrll 		disable_interrupts(I32_bit);
    128  1.4.2.1  skrll 
    129  1.4.2.1  skrll 		/* restore spl to that was when this interrupt happen */
    130  1.4.2.1  skrll 		s3c2xx0_setipl(saved_spl_level);
    131      1.1    bsh 	}
    132      1.1    bsh 
    133      1.1    bsh 
    134      1.1    bsh 	if (softint_pending & intr_mask)
    135  1.4.2.1  skrll 		s3c2xx0_do_pending(1);
    136  1.4.2.1  skrll 
    137      1.1    bsh }
    138      1.1    bsh 
    139      1.4    bsh static const u_char s3c2800_ist[] = {
    140      1.4    bsh 	EXTINTR_LOW,		/* NONE */
    141      1.4    bsh 	EXTINTR_FALLING,	/* PULSE */
    142      1.4    bsh 	EXTINTR_FALLING,	/* EDGE */
    143      1.4    bsh 	EXTINTR_LOW,		/* LEVEL */
    144      1.4    bsh 	EXTINTR_HIGH,
    145      1.4    bsh 	EXTINTR_RISING,
    146      1.4    bsh 	EXTINTR_BOTH,
    147      1.4    bsh };
    148      1.1    bsh 
    149      1.1    bsh void *
    150      1.4    bsh s3c2800_intr_establish(int irqno, int level, int type,
    151      1.1    bsh     int (* func) (void *), void *cookie)
    152      1.1    bsh {
    153      1.1    bsh 	int save;
    154      1.1    bsh 
    155      1.4    bsh 	if (irqno < 0 || irqno >= ICU_LEN ||
    156      1.4    bsh 	    type < IST_NONE || IST_EDGE_BOTH < type)
    157      1.1    bsh 		panic("intr_establish: bogus irq or type");
    158      1.1    bsh 
    159      1.1    bsh 	save = disable_interrupts(I32_bit);
    160      1.1    bsh 
    161      1.1    bsh 	handler[irqno].cookie = cookie;
    162      1.1    bsh 	handler[irqno].func = func;
    163      1.1    bsh 	handler[irqno].level = level;
    164      1.1    bsh 
    165      1.1    bsh 	s3c2xx0_update_intr_masks(irqno, level);
    166      1.1    bsh 
    167      1.4    bsh 	if (irqno <= S3C2800_INT_EXT(7)) {
    168      1.4    bsh 		/*
    169      1.4    bsh 		 * Update external interrupt control
    170      1.4    bsh 		 */
    171      1.4    bsh 		uint32_t reg;
    172      1.4    bsh 		u_int 	trig;
    173      1.4    bsh 
    174      1.4    bsh 		trig = s3c2800_ist[type];
    175      1.4    bsh 
    176      1.4    bsh 		reg = bus_space_read_4(s3c2xx0_softc->sc_iot,
    177      1.4    bsh 				       s3c2xx0_softc->sc_gpio_ioh,
    178      1.4    bsh 				       GPIO_EXTINTR);
    179      1.4    bsh 
    180      1.4    bsh 		reg = reg & ~(0x0f << (4*irqno));
    181      1.4    bsh 		reg |= trig << (4*irqno);
    182      1.4    bsh 
    183      1.4    bsh 		bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,
    184      1.4    bsh 				  GPIO_EXTINTR, reg);
    185      1.4    bsh 	}
    186      1.4    bsh 
    187  1.4.2.1  skrll 	s3c2xx0_setipl(current_spl_level);
    188      1.1    bsh 
    189      1.1    bsh 	restore_interrupts(save);
    190      1.1    bsh 
    191      1.1    bsh 	return (&handler[irqno]);
    192      1.1    bsh }
    193      1.1    bsh 
    194      1.1    bsh 
    195  1.4.2.1  skrll static void
    196  1.4.2.1  skrll init_interrupt_masks(void)
    197  1.4.2.1  skrll {
    198  1.4.2.1  skrll 	int i;
    199  1.4.2.1  skrll 
    200  1.4.2.1  skrll 	s3c2xx0_imask[IPL_NONE] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
    201  1.4.2.1  skrll 		SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK) |
    202  1.4.2.1  skrll 		SI_TO_IRQBIT(SI_SOFT);
    203  1.4.2.1  skrll 
    204  1.4.2.1  skrll 	s3c2xx0_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
    205  1.4.2.1  skrll 		SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK);
    206  1.4.2.1  skrll 
    207  1.4.2.1  skrll 	/*
    208  1.4.2.1  skrll 	 * splsoftclock() is the only interface that users of the
    209  1.4.2.1  skrll 	 * generic software interrupt facility have to block their
    210  1.4.2.1  skrll 	 * soft intrs, so splsoftclock() must also block IPL_SOFT.
    211  1.4.2.1  skrll 	 */
    212  1.4.2.1  skrll 	s3c2xx0_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
    213  1.4.2.1  skrll 		SI_TO_IRQBIT(SI_SOFTNET);
    214  1.4.2.1  skrll 
    215  1.4.2.1  skrll 	/*
    216  1.4.2.1  skrll 	 * splsoftnet() must also block splsoftclock(), since we don't
    217  1.4.2.1  skrll 	 * want timer-driven network events to occur while we're
    218  1.4.2.1  skrll 	 * processing incoming packets.
    219  1.4.2.1  skrll 	 */
    220  1.4.2.1  skrll 	s3c2xx0_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTSERIAL);
    221  1.4.2.1  skrll 
    222  1.4.2.1  skrll 	for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i)
    223  1.4.2.1  skrll 		s3c2xx0_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL);
    224  1.4.2.1  skrll 	for (; i < NIPL; ++i)
    225  1.4.2.1  skrll 		s3c2xx0_imask[i] = 0;
    226  1.4.2.1  skrll }
    227  1.4.2.1  skrll 
    228      1.1    bsh void
    229      1.1    bsh s3c2800_intr_init(struct s3c2800_softc *sc)
    230      1.1    bsh {
    231      1.1    bsh 	intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot,
    232      1.1    bsh 	    sc->sc_sx.sc_intctl_ioh);
    233      1.1    bsh 
    234      1.1    bsh 	s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK);
    235      1.1    bsh 
    236      1.1    bsh 	/* clear all pending interrupt */
    237      1.1    bsh 	icreg(INTCTL_SRCPND) = 0xffffffff;
    238      1.1    bsh 
    239  1.4.2.1  skrll 	init_interrupt_masks();
    240  1.4.2.1  skrll 
    241      1.1    bsh 	s3c2xx0_intr_init(handler, ICU_LEN);
    242      1.4    bsh 
    243      1.1    bsh }
    244