Home | History | Annotate | Line # | Download | only in s3c2xx0
s3c2800_intr.c revision 1.1 
      1 /* $NetBSD: s3c2800_intr.c,v 1.1 2002/11/20 17:52:50 bsh Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2002 Fujitsu Component Limited
      5  * Copyright (c) 2002 Genetec Corporation
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. Neither the name of The Fujitsu Component Limited nor the name of
     17  *    Genetec corporation may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
     21  * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
     22  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
     23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     24  * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
     25  * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
     26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
     27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
     28  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
     29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
     31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  */
     34 
     35 /*
     36  * IRQ handler for Samsung S3C2800 processor.
     37  * It has integrated interrupt controller.
     38  */
     39 #include <sys/param.h>
     40 #include <sys/systm.h>
     41 #include <sys/malloc.h>
     42 #include <uvm/uvm_extern.h>
     43 #include <machine/bus.h>
     44 #include <machine/intr.h>
     45 #include <arm/cpufunc.h>
     46 
     47 #include <arm/s3c2xx0/s3c2800reg.h>
     48 #include <arm/s3c2xx0/s3c2800var.h>
     49 #include <arm/s3c2xx0/s3c2xx0_intr.h>
     50 
     51 /*
     52  * interrupt dispatch table.
     53  */
     54 
     55 struct s3c2xx0_intr_dispatch handler[ICU_LEN];
     56 
     57 __volatile int softint_pending;
     58 
     59 __volatile int current_spl_level;
     60 __volatile int intr_mask;
     61 
     62 /* interrupt masks for each level */
     63 int s3c2xx0_imask[NIPL];
     64 int s3c2xx0_ilevel[ICU_LEN];
     65 
     66 int current_intr_depth;
     67 
     68 vaddr_t intctl_base;		/* interrupt controller registers */
     69 #define icreg(offset) \
     70 	(*(volatile uint32_t *)(intctl_base+(offset)))
     71 
     72 /*
     73  * Map a software interrupt queue to an interrupt priority level.
     74  */
     75 static const int si_to_ipl[SI_NQUEUES] = {
     76 	IPL_SOFT,		/* SI_SOFT */
     77 	IPL_SOFTCLOCK,		/* SI_SOFTCLOCK */
     78 	IPL_SOFTNET,		/* SI_SOFTNET */
     79 	IPL_SOFTSERIAL,		/* SI_SOFTSERIAL */
     80 };
     81 /*
     82  * called from irq_entry.
     83  */
     84 void s3c2800_irq_handler(struct clockframe *);
     85 void
     86 s3c2800_irq_handler(struct clockframe *frame)
     87 {
     88 	uint32_t irqbits;
     89 	int irqno;
     90 	int saved_spl_level;
     91 
     92 	++current_intr_depth;
     93 	saved_spl_level = current_spl_level;
     94 
     95 	/* get pending IRQs */
     96 	irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK;
     97 
     98 	for (irqno = 0; irqbits; ++irqno) {
     99 		if ((irqbits & (1 << irqno)) == 0)
    100 			continue;
    101 		/* raise spl to stop interrupts of lower priorities */
    102 		if (saved_spl_level < handler[irqno].level)
    103 			s3c2xx0_setipl(handler[irqno].level);
    104 
    105 		/* clear pending bit */
    106 		icreg(INTCTL_SRCPND) = 1 << irqno;
    107 #ifdef notyet
    108 		/* Enable interrupt */
    109 #endif
    110 		(*handler[irqno].func) (
    111 		    handler[irqno].cookie == 0
    112 		    ? frame : handler[irqno].cookie);
    113 #ifdef notyet
    114 		/* Disable interrupt */
    115 #endif
    116 
    117 		irqbits &= ~(1 << irqno);
    118 	}
    119 
    120 	/* restore spl to that was when this interrupt happen */
    121 	s3c2xx0_setipl(saved_spl_level);
    122 
    123 	if (softint_pending & intr_mask)
    124 		s3c2xx0_do_pending();
    125 
    126 	--current_intr_depth;
    127 }
    128 
    129 
    130 void *
    131 s3c2800_intr_establish(int irqno, int level,
    132     int (* func) (void *), void *cookie)
    133 {
    134 	int save;
    135 
    136 	if (irqno < 0 || irqno >= ICU_LEN)
    137 		panic("intr_establish: bogus irq or type");
    138 
    139 	save = disable_interrupts(I32_bit);
    140 
    141 	handler[irqno].cookie = cookie;
    142 	handler[irqno].func = func;
    143 	handler[irqno].level = level;
    144 
    145 	s3c2xx0_update_intr_masks(irqno, level);
    146 
    147 	intr_mask = s3c2xx0_imask[current_spl_level];
    148 	*s3c2xx0_intr_mask_reg = intr_mask;
    149 
    150 	restore_interrupts(save);
    151 
    152 	return (&handler[irqno]);
    153 }
    154 
    155 
    156 void
    157 s3c2800_intr_init(struct s3c2800_softc *sc)
    158 {
    159 	intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot,
    160 	    sc->sc_sx.sc_intctl_ioh);
    161 
    162 	s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK);
    163 
    164 	/* clear all pending interrupt */
    165 	icreg(INTCTL_SRCPND) = 0xffffffff;
    166 
    167 	s3c2xx0_intr_init(handler, ICU_LEN);
    168 }
    169