sa1111.c revision 1.1
1 /* $NetBSD: sa1111.c,v 1.1 2001/07/08 23:37:52 rjs Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by IWAMOTO Toshihiro. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * TODO: 41 * - separate machine specific attach code 42 * - introduce bus abstraction to support SA1101 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/types.h> 48 #include <sys/conf.h> 49 #include <sys/device.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/uio.h> 53 54 #include <machine/bus.h> 55 #ifdef hpcarm 56 #include <machine/platid.h> 57 #include <machine/platid_mask.h> 58 #endif 59 60 #include <arm/sa11x0/sa11x0_reg.h> 61 #include <arm/sa11x0/sa11x0_var.h> 62 #include <arm/sa11x0/sa11x0_gpioreg.h> 63 #include <arm/sa11x0/sa1111_reg.h> 64 #include <arm/sa11x0/sa1111_var.h> 65 66 static int sacc_match(struct device *, struct cfdata *, void *); 67 static void sacc_attach(struct device *, struct device *, void *); 68 static int sa1111_search(struct device *, struct cfdata *, void *); 69 static int sa1111_print(void *, const char *); 70 71 static void sacc_intr_calculatemasks(struct sacc_softc *); 72 static void sacc_intr_setpolarity(sacc_chipset_tag_t *, int , int); 73 int sacc_intr(void *); 74 75 #if hpcarm 76 void *softintr_establish(int, int (*)(void *), void *); 77 void softintr_schedule(void *); 78 #endif 79 80 #ifdef hpcarm 81 struct platid_data sacc_platid_table[] = { 82 { &platid_mask_MACH_HP_JORNADA_720, (void *)1 }, 83 { &platid_mask_MACH_HP_JORNADA_720JP, (void *)1 }, 84 { NULL, NULL } 85 }; 86 #endif 87 88 struct cfattach sacc_ca = { 89 sizeof(struct sacc_softc), sacc_match, sacc_attach 90 }; 91 92 #ifdef INTR_DEBUG 93 #define DPRINTF(arg) printf arg 94 #else 95 #define DPRINTF(arg) 96 #endif 97 98 static int 99 sacc_match(parent, match, aux) 100 struct device *parent; 101 struct cfdata *match; 102 void *aux; 103 { 104 return (1); 105 } 106 107 static void 108 sacc_attach(parent, self, aux) 109 struct device *parent; 110 struct device *self; 111 void *aux; 112 { 113 int i, gpiopin; 114 struct sacc_softc *sc = (struct sacc_softc *)self; 115 struct sa11x0_softc *psc = (struct sa11x0_softc *)parent; 116 struct sa11x0_attach_args *sa = aux; 117 #ifdef hpcarm 118 struct platid_data *p; 119 #endif 120 121 sc->sc_iot = sa->sa_iot; 122 sc->sc_piot = psc->sc_iot; 123 sc->sc_gpioh = psc->sc_gpioh; 124 #ifdef hpcarm 125 if ((p = platid_search(&platid, sacc_platid_table)) == NULL) 126 return; 127 128 gpiopin = (int)p->data; 129 #else 130 gpiopin = sa->sa_gpio; 131 #endif 132 sc->sc_gpiomask = 1 << gpiopin; 133 134 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, 135 &sc->sc_ioh)) { 136 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 137 return; 138 } 139 140 for(i = 0; i < SACCIC_LEN; i++) 141 sc->sc_intrhand[i] = NULL; 142 143 /* initialize SA1111 interrupt controller */ 144 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0); 145 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0); 146 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0); 147 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 148 SACCIC_INTSTATCLR0, 0xffffffff); 149 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 150 SACCIC_INTSTATCLR1, 0xffffffff); 151 152 /* connect to SA1110's GPIO intr */ 153 sa11x0_intr_establish(0, gpiopin, 1, IPL_SERIAL, sacc_intr, sc); 154 155 /* 156 * Attach each devices 157 */ 158 config_search(sa1111_search, self, sa1111_print); 159 } 160 161 static int 162 sa1111_search(parent, cf, aux) 163 struct device *parent; 164 struct cfdata *cf; 165 void *aux; 166 { 167 if ((*cf->cf_attach->ca_match)(parent, cf, NULL) > 0) 168 config_attach(parent, cf, NULL, sa1111_print); 169 170 return 0; 171 } 172 173 static int 174 sa1111_print(aux, name) 175 void *aux; 176 const char *name; 177 { 178 printf("\n"); 179 return (UNCONF); 180 } 181 182 int 183 sacc_intr(arg) 184 void *arg; 185 { 186 int i; 187 u_int32_t mask; 188 struct sacc_intrvec intstat; 189 struct sacc_softc *sc = arg; 190 #ifdef hpcarm 191 struct sacc_intrhand *ih; 192 #endif 193 194 intstat.lo = 195 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0); 196 intstat.hi = 197 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1); 198 DPRINTF(("sacc_intr_dispatch: %x %x\n", intstat.lo, intstat.hi)); 199 200 for(i = 0, mask = 1; i < 32; i++, mask <<= 1) 201 if (intstat.lo & mask) { 202 /* clear SA1110's GPIO intr status */ 203 bus_space_write_4(sc->sc_piot, sc->sc_gpioh, 204 SAGPIO_EDR, sc->sc_gpiomask); 205 /* 206 * Clear intr status before calling intr handlers. 207 * This cause stray interrupts, but clearing 208 * after calling intr handlers cause intr lossage. 209 */ 210 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 211 SACCIC_INTSTATCLR0, 1 << i); 212 213 #ifdef hpcarm 214 for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next) 215 softintr_schedule(ih->ih_soft); 216 #endif 217 } 218 for(i = 0, mask = 1; i < SACCIC_LEN - 32; i++, mask <<= 1) 219 if (intstat.hi & mask) { 220 /* clear SA1110's GPIO intr status */ 221 bus_space_write_4(sc->sc_piot, sc->sc_gpioh, 222 SAGPIO_EDR, sc->sc_gpiomask); 223 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 224 SACCIC_INTSTATCLR1, 1 << i); 225 #ifdef hpcarm 226 for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next) 227 softintr_schedule(ih->ih_soft); 228 #endif 229 } 230 return 1; 231 } 232 233 void * 234 sacc_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 235 sacc_chipset_tag_t *ic; 236 int irq, type, level; 237 int (*ih_fun)(void *); 238 void *ih_arg; 239 { 240 int s; 241 struct sacc_softc *sc = (struct sacc_softc *)ic; 242 struct sacc_intrhand **p, *ih; 243 244 /* no point in sleeping unless someone can free memory. */ 245 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 246 if (ih == NULL) 247 panic("sacc_intr_establish: can't malloc handler info"); 248 249 if (irq < 0 || irq > SACCIC_LEN || 250 ! (type == IST_EDGE_RAISE || type == IST_EDGE_FALL)) 251 panic("sacc_intr_establish: bogus irq or type"); 252 253 if (sc->sc_intrhand[irq] == NULL) { 254 sacc_intr_setpolarity(ic, irq, type); 255 sc->sc_intrtype[irq] = type; 256 } else if (sc->sc_intrtype[irq] != type) 257 /* XXX we should be able to share raising and 258 * falling edge intrs */ 259 panic("sacc_intr_establish: type must be unique\n"); 260 261 /* install intr handler */ 262 #ifdef hpcarm 263 ih->ih_soft = softintr_establish(level, (void (*)(void *)) ih_fun, 264 ih_arg); 265 #endif 266 ih->ih_irq = irq; 267 ih->ih_next = NULL; 268 269 s = splhigh(); 270 for(p = &sc->sc_intrhand[irq]; *p; p = &(*p)->ih_next) 271 ; 272 273 *p = ih; 274 275 sacc_intr_calculatemasks(sc); 276 splx(s); 277 278 return(ih); 279 } 280 281 void 282 sacc_intr_disestablish(ic, arg) 283 sacc_chipset_tag_t *ic; 284 void *arg; 285 { 286 int irq, s; 287 struct sacc_softc *sc = (struct sacc_softc *)ic; 288 struct sacc_intrhand *ih, **p; 289 290 ih = (struct sacc_intrhand *)arg; 291 irq = ih->ih_irq; 292 293 #ifdef DIAGNOSTIC 294 if (irq < 0 || irq > SACCIC_LEN) 295 panic("sacc_intr_disestablish: bogus irq"); 296 #endif 297 298 s = splhigh(); 299 300 for(p = &sc->sc_intrhand[irq];; p = &(*p)->ih_next) { 301 if (*p == NULL) 302 panic("sacc_intr_disestablish: handler not registered"); 303 if (*p == ih) 304 break; 305 } 306 *p = (*p)->ih_next; 307 308 sacc_intr_calculatemasks(sc); 309 splx(s); 310 311 free(ih, M_DEVBUF); 312 } 313 314 void 315 sacc_intr_setpolarity(ic, irq, type) 316 sacc_chipset_tag_t *ic; 317 int irq; 318 int type; 319 { 320 struct sacc_softc *sc = (struct sacc_softc *)ic; 321 int s; 322 u_int32_t pol, mask; 323 int addr; 324 325 if (irq >= 32) { 326 addr = SACCIC_INTPOL1; 327 irq -= 32; 328 } else 329 addr = SACCIC_INTPOL0; 330 331 mask = (1 << irq); 332 333 s = splhigh(); 334 pol = bus_space_read_4(sc->sc_iot, sc->sc_ioh, addr); 335 if (type == IST_EDGE_RAISE) 336 pol &= ~mask; 337 else 338 pol |= mask; 339 bus_space_write_4(sc->sc_iot, sc->sc_ioh, addr, pol); 340 splx(s); 341 } 342 343 void 344 sacc_intr_calculatemasks(sc) 345 struct sacc_softc *sc; 346 { 347 int irq; 348 349 sc->sc_imask.lo = 0; 350 sc->sc_imask.hi = 0; 351 for(irq = 0; irq < 32; irq++) 352 if (sc->sc_intrhand[irq]) 353 sc->sc_imask.lo |= (1 << irq); 354 for(irq = 0; irq < SACCIC_LEN - 32; irq++) 355 if (sc->sc_intrhand[irq + 32]) 356 sc->sc_imask.hi |= (1 << irq); 357 358 359 /* XXX this should not be done here */ 360 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 361 sc->sc_imask.lo); 362 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 363 sc->sc_imask.hi); 364 DPRINTF(("sacc_intr_calculatemasks: %x %x\n", sc->sc_imask.lo, 365 sc->sc_imask.hi)); 366 } 367
Indexes created Mon Sep 29 21:09:56 GMT 2025