sa1111.c revision 1.10
1 /* $NetBSD: sa1111.c,v 1.10 2003/07/15 00:24:50 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by IWAMOTO Toshihiro. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * TODO: 41 * - separate machine specific attach code 42 * - introduce bus abstraction to support SA1101 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: sa1111.c,v 1.10 2003/07/15 00:24:50 lukem Exp $"); 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/types.h> 51 #include <sys/conf.h> 52 #include <sys/device.h> 53 #include <sys/kernel.h> 54 #include <sys/malloc.h> 55 #include <sys/uio.h> 56 57 #include <machine/bus.h> 58 #ifdef hpcarm 59 #include <machine/platid.h> 60 #include <machine/platid_mask.h> 61 #endif 62 63 #include <arm/sa11x0/sa11x0_reg.h> 64 #include <arm/sa11x0/sa11x0_var.h> 65 #include <arm/sa11x0/sa11x0_gpioreg.h> 66 #include <arm/sa11x0/sa1111_reg.h> 67 #include <arm/sa11x0/sa1111_var.h> 68 69 static int sacc_probe(struct device *, struct cfdata *, void *); 70 static void sacc_attach(struct device *, struct device *, void *); 71 static int sa1111_search(struct device *, struct cfdata *, void *); 72 static int sa1111_print(void *, const char *); 73 74 static void sacc_intr_calculatemasks(struct sacc_softc *); 75 static void sacc_intr_setpolarity(sacc_chipset_tag_t *, int , int); 76 int sacc_intr(void *); 77 78 #ifndef hpcarm 79 void *softintr_establish(int, int (*)(void *), void *); 80 void softintr_schedule(void *); 81 #endif 82 83 #ifdef hpcarm 84 struct platid_data sacc_platid_table[] = { 85 { &platid_mask_MACH_HP_JORNADA_720, (void *)1 }, 86 { &platid_mask_MACH_HP_JORNADA_720JP, (void *)1 }, 87 { NULL, NULL } 88 }; 89 #endif 90 91 CFATTACH_DECL(sacc, sizeof(struct sacc_softc), 92 sacc_probe, sacc_attach, NULL, NULL); 93 94 #ifdef INTR_DEBUG 95 #define DPRINTF(arg) printf arg 96 #else 97 #define DPRINTF(arg) 98 #endif 99 100 static int 101 sacc_probe(parent, match, aux) 102 struct device *parent; 103 struct cfdata *match; 104 void *aux; 105 { 106 struct sa11x0_attach_args *sa = aux; 107 bus_space_handle_t ioh; 108 u_int32_t skid; 109 110 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &ioh)) 111 return (0); 112 113 skid = bus_space_read_4(sa->sa_iot, ioh, SACCSBI_SKID); 114 bus_space_unmap(sa->sa_iot, ioh, sa->sa_size); 115 116 if ((skid & 0xffffff00) != 0x690cc200) 117 return (0); 118 119 return (1); 120 } 121 122 static void 123 sacc_attach(parent, self, aux) 124 struct device *parent; 125 struct device *self; 126 void *aux; 127 { 128 int i, gpiopin; 129 u_int32_t skid; 130 struct sacc_softc *sc = (struct sacc_softc *)self; 131 struct sa11x0_softc *psc = (struct sa11x0_softc *)parent; 132 struct sa11x0_attach_args *sa = aux; 133 #ifdef hpcarm 134 struct platid_data *p; 135 #endif 136 137 printf("\n"); 138 139 sc->sc_iot = sa->sa_iot; 140 sc->sc_piot = psc->sc_iot; 141 sc->sc_gpioh = psc->sc_gpioh; 142 #ifdef hpcarm 143 if ((p = platid_search_data(&platid, sacc_platid_table)) == NULL) 144 return; 145 146 gpiopin = (int) p->data; 147 #else 148 gpiopin = sa->sa_gpio; 149 #endif 150 sc->sc_gpiomask = 1 << gpiopin; 151 152 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, 153 &sc->sc_ioh)) { 154 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 155 return; 156 } 157 158 skid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKID); 159 160 printf("%s: SA1111 rev %d.%d\n", sc->sc_dev.dv_xname, 161 (skid & 0xf0) >> 3, skid & 0xf); 162 163 for(i = 0; i < SACCIC_LEN; i++) 164 sc->sc_intrhand[i] = NULL; 165 166 /* initialize SA1111 interrupt controller */ 167 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0); 168 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0); 169 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0); 170 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 171 SACCIC_INTSTATCLR0, 0xffffffff); 172 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 173 SACCIC_INTSTATCLR1, 0xffffffff); 174 175 /* connect to SA1110's GPIO intr */ 176 sa11x0_intr_establish(0, gpiopin, 1, IPL_SERIAL, sacc_intr, sc); 177 178 /* 179 * Attach each devices 180 */ 181 config_search(sa1111_search, self, NULL); 182 } 183 184 static int 185 sa1111_search(parent, cf, aux) 186 struct device *parent; 187 struct cfdata *cf; 188 void *aux; 189 { 190 if (config_match(parent, cf, NULL) > 0) 191 config_attach(parent, cf, NULL, sa1111_print); 192 193 return 0; 194 } 195 196 static int 197 sa1111_print(aux, name) 198 void *aux; 199 const char *name; 200 { 201 return (UNCONF); 202 } 203 204 int 205 sacc_intr(arg) 206 void *arg; 207 { 208 int i; 209 u_int32_t mask; 210 struct sacc_intrvec intstat; 211 struct sacc_softc *sc = arg; 212 #ifdef hpcarm 213 struct sacc_intrhand *ih; 214 #endif 215 216 intstat.lo = 217 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0); 218 intstat.hi = 219 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1); 220 DPRINTF(("sacc_intr_dispatch: %x %x\n", intstat.lo, intstat.hi)); 221 222 /* clear SA1110's GPIO intr status */ 223 bus_space_write_4(sc->sc_piot, sc->sc_gpioh, 224 SAGPIO_EDR, sc->sc_gpiomask); 225 226 for(i = 0, mask = 1; i < 32; i++, mask <<= 1) 227 if (intstat.lo & mask) { 228 /* 229 * Clear intr status before calling intr handlers. 230 * This cause stray interrupts, but clearing 231 * after calling intr handlers cause intr lossage. 232 */ 233 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 234 SACCIC_INTSTATCLR0, 1 << i); 235 236 #ifdef hpcarm 237 for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next) 238 softintr_schedule(ih->ih_soft); 239 #endif 240 } 241 for(i = 0, mask = 1; i < SACCIC_LEN - 32; i++, mask <<= 1) 242 if (intstat.hi & mask) { 243 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 244 SACCIC_INTSTATCLR1, 1 << i); 245 #ifdef hpcarm 246 for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next) 247 softintr_schedule(ih->ih_soft); 248 #endif 249 } 250 return 1; 251 } 252 253 void * 254 sacc_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 255 sacc_chipset_tag_t *ic; 256 int irq, type, level; 257 int (*ih_fun)(void *); 258 void *ih_arg; 259 { 260 int s; 261 struct sacc_softc *sc = (struct sacc_softc *)ic; 262 struct sacc_intrhand **p, *ih; 263 264 /* no point in sleeping unless someone can free memory. */ 265 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 266 if (ih == NULL) 267 panic("sacc_intr_establish: can't malloc handler info"); 268 269 if (irq < 0 || irq > SACCIC_LEN || 270 ! (type == IST_EDGE_RAISE || type == IST_EDGE_FALL)) 271 panic("sacc_intr_establish: bogus irq or type"); 272 273 if (sc->sc_intrhand[irq] == NULL) { 274 sacc_intr_setpolarity(ic, irq, type); 275 sc->sc_intrtype[irq] = type; 276 } else if (sc->sc_intrtype[irq] != type) 277 /* XXX we should be able to share raising and 278 * falling edge intrs */ 279 panic("sacc_intr_establish: type must be unique"); 280 281 /* install intr handler */ 282 #ifdef hpcarm 283 ih->ih_soft = softintr_establish(level, (void (*)(void *)) ih_fun, 284 ih_arg); 285 #endif 286 ih->ih_irq = irq; 287 ih->ih_next = NULL; 288 289 s = splhigh(); 290 for(p = &sc->sc_intrhand[irq]; *p; p = &(*p)->ih_next) 291 ; 292 293 *p = ih; 294 295 sacc_intr_calculatemasks(sc); 296 splx(s); 297 298 return(ih); 299 } 300 301 void 302 sacc_intr_disestablish(ic, arg) 303 sacc_chipset_tag_t *ic; 304 void *arg; 305 { 306 int irq, s; 307 struct sacc_softc *sc = (struct sacc_softc *)ic; 308 struct sacc_intrhand *ih, **p; 309 310 ih = (struct sacc_intrhand *)arg; 311 irq = ih->ih_irq; 312 313 #ifdef DIAGNOSTIC 314 if (irq < 0 || irq > SACCIC_LEN) 315 panic("sacc_intr_disestablish: bogus irq"); 316 #endif 317 318 s = splhigh(); 319 320 for(p = &sc->sc_intrhand[irq];; p = &(*p)->ih_next) { 321 if (*p == NULL) 322 panic("sacc_intr_disestablish: handler not registered"); 323 if (*p == ih) 324 break; 325 } 326 *p = (*p)->ih_next; 327 328 sacc_intr_calculatemasks(sc); 329 splx(s); 330 331 free(ih, M_DEVBUF); 332 } 333 334 void 335 sacc_intr_setpolarity(ic, irq, type) 336 sacc_chipset_tag_t *ic; 337 int irq; 338 int type; 339 { 340 struct sacc_softc *sc = (struct sacc_softc *)ic; 341 int s; 342 u_int32_t pol, mask; 343 int addr; 344 345 if (irq >= 32) { 346 addr = SACCIC_INTPOL1; 347 irq -= 32; 348 } else 349 addr = SACCIC_INTPOL0; 350 351 mask = (1 << irq); 352 353 s = splhigh(); 354 pol = bus_space_read_4(sc->sc_iot, sc->sc_ioh, addr); 355 if (type == IST_EDGE_RAISE) 356 pol &= ~mask; 357 else 358 pol |= mask; 359 bus_space_write_4(sc->sc_iot, sc->sc_ioh, addr, pol); 360 splx(s); 361 } 362 363 void 364 sacc_intr_calculatemasks(sc) 365 struct sacc_softc *sc; 366 { 367 int irq; 368 369 sc->sc_imask.lo = 0; 370 sc->sc_imask.hi = 0; 371 for(irq = 0; irq < 32; irq++) 372 if (sc->sc_intrhand[irq]) 373 sc->sc_imask.lo |= (1 << irq); 374 for(irq = 0; irq < SACCIC_LEN - 32; irq++) 375 if (sc->sc_intrhand[irq + 32]) 376 sc->sc_imask.hi |= (1 << irq); 377 378 379 /* XXX this should not be done here */ 380 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 381 sc->sc_imask.lo); 382 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 383 sc->sc_imask.hi); 384 DPRINTF(("sacc_intr_calculatemasks: %x %x\n", sc->sc_imask.lo, 385 sc->sc_imask.hi)); 386 } 387
Indexes created Tue Sep 30 06:09:59 GMT 2025