sa1111.c revision 1.5
1 /* $NetBSD: sa1111.c,v 1.5 2002/08/12 22:26:41 rjs Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by IWAMOTO Toshihiro. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * TODO: 41 * - separate machine specific attach code 42 * - introduce bus abstraction to support SA1101 43 */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/types.h> 48 #include <sys/conf.h> 49 #include <sys/device.h> 50 #include <sys/kernel.h> 51 #include <sys/malloc.h> 52 #include <sys/uio.h> 53 54 #include <machine/bus.h> 55 #ifdef hpcarm 56 #include <machine/platid.h> 57 #include <machine/platid_mask.h> 58 #endif 59 60 #include <arm/sa11x0/sa11x0_reg.h> 61 #include <arm/sa11x0/sa11x0_var.h> 62 #include <arm/sa11x0/sa11x0_gpioreg.h> 63 #include <arm/sa11x0/sa1111_reg.h> 64 #include <arm/sa11x0/sa1111_var.h> 65 66 static int sacc_probe(struct device *, struct cfdata *, void *); 67 static void sacc_attach(struct device *, struct device *, void *); 68 static int sa1111_search(struct device *, struct cfdata *, void *); 69 static int sa1111_print(void *, const char *); 70 71 static void sacc_intr_calculatemasks(struct sacc_softc *); 72 static void sacc_intr_setpolarity(sacc_chipset_tag_t *, int , int); 73 int sacc_intr(void *); 74 75 #ifndef hpcarm 76 void *softintr_establish(int, int (*)(void *), void *); 77 void softintr_schedule(void *); 78 #endif 79 80 #ifdef hpcarm 81 struct platid_data sacc_platid_table[] = { 82 { &platid_mask_MACH_HP_JORNADA_720, (void *)1 }, 83 { &platid_mask_MACH_HP_JORNADA_720JP, (void *)1 }, 84 { NULL, NULL } 85 }; 86 #endif 87 88 struct cfattach sacc_ca = { 89 sizeof(struct sacc_softc), sacc_probe, sacc_attach 90 }; 91 92 #ifdef INTR_DEBUG 93 #define DPRINTF(arg) printf arg 94 #else 95 #define DPRINTF(arg) 96 #endif 97 98 static int 99 sacc_probe(parent, match, aux) 100 struct device *parent; 101 struct cfdata *match; 102 void *aux; 103 { 104 struct sa11x0_attach_args *sa = aux; 105 bus_space_handle_t ioh; 106 u_int32_t skid; 107 108 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, &ioh)) 109 return (0); 110 111 skid = bus_space_read_4(sa->sa_iot, ioh, SACCSBI_SKID); 112 bus_space_unmap(sa->sa_iot, ioh, sa->sa_size); 113 114 if ((skid & 0xffffff00) != 0x690cc200) 115 return (0); 116 117 return (1); 118 } 119 120 static void 121 sacc_attach(parent, self, aux) 122 struct device *parent; 123 struct device *self; 124 void *aux; 125 { 126 int i, gpiopin; 127 u_int32_t skid; 128 struct sacc_softc *sc = (struct sacc_softc *)self; 129 struct sa11x0_softc *psc = (struct sa11x0_softc *)parent; 130 struct sa11x0_attach_args *sa = aux; 131 #ifdef hpcarm 132 struct platid_data *p; 133 #endif 134 135 printf("\n"); 136 137 sc->sc_iot = sa->sa_iot; 138 sc->sc_piot = psc->sc_iot; 139 sc->sc_gpioh = psc->sc_gpioh; 140 #ifdef hpcarm 141 if ((p = platid_search_data(&platid, sacc_platid_table)) == NULL) 142 return; 143 144 gpiopin = (int) p->data; 145 #else 146 gpiopin = sa->sa_gpio; 147 #endif 148 sc->sc_gpiomask = 1 << gpiopin; 149 150 if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size, 0, 151 &sc->sc_ioh)) { 152 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 153 return; 154 } 155 156 skid = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCSBI_SKID); 157 158 printf("%s: SA1111 rev %d.%d\n", sc->sc_dev.dv_xname, 159 (skid & 0xf0) >> 3, skid & 0xf); 160 161 for(i = 0; i < SACCIC_LEN; i++) 162 sc->sc_intrhand[i] = NULL; 163 164 /* initialize SA1111 interrupt controller */ 165 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 0); 166 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 0); 167 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTTSTSEL, 0); 168 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 169 SACCIC_INTSTATCLR0, 0xffffffff); 170 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 171 SACCIC_INTSTATCLR1, 0xffffffff); 172 173 /* connect to SA1110's GPIO intr */ 174 sa11x0_intr_establish(0, gpiopin, 1, IPL_SERIAL, sacc_intr, sc); 175 176 /* 177 * Attach each devices 178 */ 179 config_search(sa1111_search, self, NULL); 180 } 181 182 static int 183 sa1111_search(parent, cf, aux) 184 struct device *parent; 185 struct cfdata *cf; 186 void *aux; 187 { 188 if ((*cf->cf_attach->ca_match)(parent, cf, NULL) > 0) 189 config_attach(parent, cf, NULL, sa1111_print); 190 191 return 0; 192 } 193 194 static int 195 sa1111_print(aux, name) 196 void *aux; 197 const char *name; 198 { 199 return (UNCONF); 200 } 201 202 int 203 sacc_intr(arg) 204 void *arg; 205 { 206 int i; 207 u_int32_t mask; 208 struct sacc_intrvec intstat; 209 struct sacc_softc *sc = arg; 210 #ifdef hpcarm 211 struct sacc_intrhand *ih; 212 #endif 213 214 intstat.lo = 215 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR0); 216 intstat.hi = 217 bus_space_read_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTSTATCLR1); 218 DPRINTF(("sacc_intr_dispatch: %x %x\n", intstat.lo, intstat.hi)); 219 220 /* clear SA1110's GPIO intr status */ 221 bus_space_write_4(sc->sc_piot, sc->sc_gpioh, 222 SAGPIO_EDR, sc->sc_gpiomask); 223 224 for(i = 0, mask = 1; i < 32; i++, mask <<= 1) 225 if (intstat.lo & mask) { 226 /* 227 * Clear intr status before calling intr handlers. 228 * This cause stray interrupts, but clearing 229 * after calling intr handlers cause intr lossage. 230 */ 231 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 232 SACCIC_INTSTATCLR0, 1 << i); 233 234 #ifdef hpcarm 235 for(ih = sc->sc_intrhand[i]; ih; ih = ih->ih_next) 236 softintr_schedule(ih->ih_soft); 237 #endif 238 } 239 for(i = 0, mask = 1; i < SACCIC_LEN - 32; i++, mask <<= 1) 240 if (intstat.hi & mask) { 241 bus_space_write_4(sc->sc_iot, sc->sc_ioh, 242 SACCIC_INTSTATCLR1, 1 << i); 243 #ifdef hpcarm 244 for(ih = sc->sc_intrhand[i + 32]; ih; ih = ih->ih_next) 245 softintr_schedule(ih->ih_soft); 246 #endif 247 } 248 return 1; 249 } 250 251 void * 252 sacc_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 253 sacc_chipset_tag_t *ic; 254 int irq, type, level; 255 int (*ih_fun)(void *); 256 void *ih_arg; 257 { 258 int s; 259 struct sacc_softc *sc = (struct sacc_softc *)ic; 260 struct sacc_intrhand **p, *ih; 261 262 /* no point in sleeping unless someone can free memory. */ 263 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 264 if (ih == NULL) 265 panic("sacc_intr_establish: can't malloc handler info"); 266 267 if (irq < 0 || irq > SACCIC_LEN || 268 ! (type == IST_EDGE_RAISE || type == IST_EDGE_FALL)) 269 panic("sacc_intr_establish: bogus irq or type"); 270 271 if (sc->sc_intrhand[irq] == NULL) { 272 sacc_intr_setpolarity(ic, irq, type); 273 sc->sc_intrtype[irq] = type; 274 } else if (sc->sc_intrtype[irq] != type) 275 /* XXX we should be able to share raising and 276 * falling edge intrs */ 277 panic("sacc_intr_establish: type must be unique\n"); 278 279 /* install intr handler */ 280 #ifdef hpcarm 281 ih->ih_soft = softintr_establish(level, (void (*)(void *)) ih_fun, 282 ih_arg); 283 #endif 284 ih->ih_irq = irq; 285 ih->ih_next = NULL; 286 287 s = splhigh(); 288 for(p = &sc->sc_intrhand[irq]; *p; p = &(*p)->ih_next) 289 ; 290 291 *p = ih; 292 293 sacc_intr_calculatemasks(sc); 294 splx(s); 295 296 return(ih); 297 } 298 299 void 300 sacc_intr_disestablish(ic, arg) 301 sacc_chipset_tag_t *ic; 302 void *arg; 303 { 304 int irq, s; 305 struct sacc_softc *sc = (struct sacc_softc *)ic; 306 struct sacc_intrhand *ih, **p; 307 308 ih = (struct sacc_intrhand *)arg; 309 irq = ih->ih_irq; 310 311 #ifdef DIAGNOSTIC 312 if (irq < 0 || irq > SACCIC_LEN) 313 panic("sacc_intr_disestablish: bogus irq"); 314 #endif 315 316 s = splhigh(); 317 318 for(p = &sc->sc_intrhand[irq];; p = &(*p)->ih_next) { 319 if (*p == NULL) 320 panic("sacc_intr_disestablish: handler not registered"); 321 if (*p == ih) 322 break; 323 } 324 *p = (*p)->ih_next; 325 326 sacc_intr_calculatemasks(sc); 327 splx(s); 328 329 free(ih, M_DEVBUF); 330 } 331 332 void 333 sacc_intr_setpolarity(ic, irq, type) 334 sacc_chipset_tag_t *ic; 335 int irq; 336 int type; 337 { 338 struct sacc_softc *sc = (struct sacc_softc *)ic; 339 int s; 340 u_int32_t pol, mask; 341 int addr; 342 343 if (irq >= 32) { 344 addr = SACCIC_INTPOL1; 345 irq -= 32; 346 } else 347 addr = SACCIC_INTPOL0; 348 349 mask = (1 << irq); 350 351 s = splhigh(); 352 pol = bus_space_read_4(sc->sc_iot, sc->sc_ioh, addr); 353 if (type == IST_EDGE_RAISE) 354 pol &= ~mask; 355 else 356 pol |= mask; 357 bus_space_write_4(sc->sc_iot, sc->sc_ioh, addr, pol); 358 splx(s); 359 } 360 361 void 362 sacc_intr_calculatemasks(sc) 363 struct sacc_softc *sc; 364 { 365 int irq; 366 367 sc->sc_imask.lo = 0; 368 sc->sc_imask.hi = 0; 369 for(irq = 0; irq < 32; irq++) 370 if (sc->sc_intrhand[irq]) 371 sc->sc_imask.lo |= (1 << irq); 372 for(irq = 0; irq < SACCIC_LEN - 32; irq++) 373 if (sc->sc_intrhand[irq + 32]) 374 sc->sc_imask.hi |= (1 << irq); 375 376 377 /* XXX this should not be done here */ 378 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN0, 379 sc->sc_imask.lo); 380 bus_space_write_4(sc->sc_iot, sc->sc_ioh, SACCIC_INTEN1, 381 sc->sc_imask.hi); 382 DPRINTF(("sacc_intr_calculatemasks: %x %x\n", sc->sc_imask.lo, 383 sc->sc_imask.hi)); 384 } 385
Indexes created Tue Sep 30 07:10:03 GMT 2025