sa11x0_irq.S revision 1.7
1 /* $NetBSD: sa11x0_irq.S,v 1.7 2005/10/23 15:04:43 peter Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Mark Brinicombe. 5 * Copyright (c) 1998 Causality Limited 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to the NetBSD Foundation 9 * by IWAMOTO Toshihiro. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Mark Brinicombe 22 * for the NetBSD Project. 23 * 4. The name of the company nor the name of the author may be used to 24 * endorse or promote products derived from this software without specific 25 * prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 */ 39 40 #include "opt_irqstats.h" 41 42 #include "assym.h" 43 #include <machine/asm.h> 44 #include <machine/cpu.h> 45 #include <machine/frame.h> 46 #include <arm/sa11x0/sa11x0_reg.h> 47 48 49 .text 50 .align 0 51 52 Lcurrent_spl_level: 53 .word _C_LABEL(current_spl_level) 54 55 Lcurrent_intr_depth: 56 .word _C_LABEL(current_intr_depth) 57 58 Lspl_masks: 59 .word _C_LABEL(spl_masks) 60 61 .globl _C_LABEL(saipic_base) 62 _C_LABEL(saipic_base): 63 .word 0x00000000 64 65 #ifdef INTR_DEBUG 66 Ldbg_str: 67 .asciz "irq_entry %x %x\n" 68 #endif 69 70 AST_ALIGNMENT_FAULT_LOCALS 71 72 /* 73 * Register usage 74 * 75 * r6 - Address of current handler 76 * r7 - Pointer to handler pointer list 77 * r8 - Current IRQ requests. 78 * r9 - Used to count through possible IRQ bits. 79 * r10 - Base address of SAIP 80 */ 81 82 ASENTRY_NP(irq_entry) 83 sub lr, lr, #0x00000004 /* Adjust the lr */ 84 85 PUSHFRAMEINSVC /* Push an interrupt frame */ 86 ENABLE_ALIGNMENT_FAULTS 87 88 /* Load r8 with the SAIPIC interrupt requests */ 89 90 ldr r10, _C_LABEL(saipic_base) 91 ldr r8, [r10, #(SAIPIC_IP)] /* Load IRQ pending register */ 92 93 #ifdef INTR_DEBUG 94 ldr r2, [r10, #(SAIPIC_MR)] 95 adr r0, Ldbg_str 96 mov r1, r8 97 bl _C_LABEL(printf) 98 #endif 99 /* 100 * Note that we have entered the IRQ handler. 101 * We are in SVC mode so we cannot use the processor mode 102 * to determine if we are in an IRQ. Instead we will count the 103 * each time the interrupt handler is nested. 104 */ 105 106 ldr r0, Lcurrent_intr_depth 107 ldr r1, [r0] 108 add r1, r1, #1 109 str r1, [r0] 110 111 /* 112 * Need to block all interrupts at the IPL or lower for 113 * all asserted interrupts. 114 * This basically emulates hardware interrupt priority levels. 115 * Means we need to go through the interrupt mask and for 116 * every asserted interrupt we need to mask out all other 117 * interrupts at the same or lower IPL. 118 * If only we could wait until the main loop but we need to sort 119 * this out first so interrupts can be re-enabled. 120 * 121 * This would benefit from a special ffs type routine 122 */ 123 124 mov r9, #(_SPL_LEVELS - 1) 125 ldr r7, Lspl_masks 126 127 Lfind_highest_ipl: 128 ldr r2, [r7, r9, lsl #2] 129 tst r8, r2 130 subeq r9, r9, #1 131 beq Lfind_highest_ipl 132 133 /* r9 = SPL level of highest priority interrupt */ 134 add r9, r9, #1 135 ldr r2, [r7, r9, lsl #2] 136 mvn r2, r2 137 138 ldr r0, Lcurrent_spl_level 139 ldr r1, [r0] 140 str r9, [r0] 141 stmfd sp!, {r1} 142 143 /* Update the SAIP irq masks */ 144 bl _C_LABEL(irq_setmasks) 145 146 #ifdef INTR_DEBUG 147 stmfd sp!, {r0,r1,r2} 148 adr r0, Ldbg_str 149 mov r1, #1 150 mov r2, r9 151 bl _C_LABEL(printf) 152 ldmia sp!, {r0,r1,r2} 153 #endif 154 mrs r0, cpsr_all /* Enable IRQs */ 155 bic r0, r0, #I32_bit 156 msr cpsr_all, r0 157 158 ldr r7, Lirqhandlers 159 mov r9, #0x00000001 160 161 irqloop: 162 /* This would benefit from a special ffs type routine */ 163 tst r8, r9 /* Is a bit set ? */ 164 beq nextirq /* No ? try next bit */ 165 166 ldr r6, [r7] /* Get address of first handler structure */ 167 168 teq r6, #0x00000000 /* Do we have a handler */ 169 moveq r0, r8 /* IRQ requests as arg 0 */ 170 beq _C_LABEL(stray_irqhandler) /* call special handler */ 171 172 ldr r0, Lcnt /* Stat info */ 173 ldr r1, [r0, #(V_INTR)] 174 add r1, r1, #0x00000001 175 str r1, [r0, #(V_INTR)] 176 177 /* 178 * XXX: Should stats be accumulated for every interrupt routine 179 * called or for every physical interrupt that is serviced. 180 */ 181 182 #ifdef IRQSTATS 183 ldr r0, Lintrcnt 184 ldr r1, [r6, #(IH_COUNT)] 185 186 add r0, r0, r1, lsl #2 187 ldr r1, [r0] 188 add r1, r1, #0x00000001 189 str r1, [r0] 190 #endif /* IRQSTATS */ 191 192 irqchainloop: 193 #ifdef INTR_DEBUG 194 stmfd sp!, {r0,r1,r2} 195 adr r0, Ldbg_str 196 mov r1, #2 197 bl _C_LABEL(printf) 198 ldmia sp!, {r0,r1,r2} 199 #endif 200 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 201 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 202 addeq r0, sp, #4 /* ... stack frame [XXX needs care] */ 203 mov lr, pc /* return address */ 204 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 205 206 teq r0, #0x00000001 /* Was the irq serviced ? */ 207 beq irqdone 208 209 ldr r6, [r6, #(IH_NEXT)] 210 teq r6, #0x00000000 211 bne irqchainloop 212 213 irqdone: 214 nextirq: 215 add r7, r7, #0x00000004 /* update pointer to handlers */ 216 mov r9, r9, lsl #1 /* move on to next bit */ 217 teq r9, #(1 << 31) /* done the last bit ? */ 218 bne irqloop /* no - loop back. */ 219 220 ldmfd sp!, {r2} 221 ldr r1, Lcurrent_spl_level 222 str r2, [r1] 223 224 /* Restore previous disabled mask */ 225 bl _C_LABEL(irq_setmasks) 226 227 bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 228 229 /* Kill IRQ's in preparation for exit */ 230 mrs r0, cpsr_all 231 orr r0, r0, #(I32_bit) 232 msr cpsr_all, r0 233 234 #ifdef INTR_DEBUG 235 adr r0, dbg_str 236 mov r1, #3 237 ldr r2, [r10, #(SAIPIC_MR)] 238 bl _C_LABEL(printf) 239 #endif 240 241 /* Decrement the nest count */ 242 ldr r0, Lcurrent_intr_depth 243 ldr r1, [r0] 244 sub r1, r1, #1 245 str r1, [r0] 246 247 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 248 PULLFRAMEFROMSVCANDEXIT 249 250 /* NOT REACHED */ 251 b . - 8 252 253 ENTRY(irq_setmasks) 254 /* Disable interrupts */ 255 mrs r3, cpsr_all 256 orr r1, r3, #(I32_bit) 257 msr cpsr_all, r1 258 259 /* Calculate interrupt mask */ 260 ldr r0, Lspl_masks 261 ldr r2, Lcurrent_spl_level 262 ldr r2, [r2] 263 ldr r2, [r0, r2, lsl #2] 264 265 ldr r0, _C_LABEL(saipic_base) 266 str r2, [r0, #(SAIPIC_MR)] /* Set mask register */ 267 268 /* Restore old cpsr and exit */ 269 msr cpsr_all, r3 270 mov pc, lr 271 272 Lcnt: 273 .word _C_LABEL(uvmexp) 274 275 #ifdef IRQSTATS 276 Lintrcnt: 277 .word _C_LABEL(intrcnt) 278 #endif 279 280 Lirqhandlers: 281 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 282 283 284 #ifdef IRQSTATS 285 .global _C_LABEL(intrnames), _C_LABEL(eintrnames) 286 .global _C_LABEL(eintrcnt) 287 _C_LABEL(intrnames): 288 _C_LABEL(eintrnames): 289 _C_LABEL(eintrcnt): 290 291 .globl _C_LABEL(intrcnt), _C_LABEL(sintrcnt) 292 293 _C_LABEL(intrcnt): 294 .space ICU_LEN*4 /* XXX Should be linked to number of interrupts */ 295 296 _C_LABEL(sintrcnt): 297 .space 32*4 298 #endif 299
Indexes created Fri Oct 03 02:09:57 GMT 2025