1 /* $NetBSD: exynos_dwcmmc.c,v 1.15 2021/03/14 08:16:57 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: exynos_dwcmmc.c,v 1.15 2021/03/14 08:16:57 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <arm/samsung/exynos_var.h> 42 43 #include <dev/ic/dwc_mmc_reg.h> 44 #include <dev/ic/dwc_mmc_var.h> 45 #include <dev/fdt/fdtvar.h> 46 47 #define MPS_BEGIN 0x200 48 #define MPS_END 0x204 49 #define MPS_CTRL 0x20c 50 #define MPS_CTRL_SECURE_WRITE __BIT(6) 51 #define MPS_CTRL_NON_SECURE_READ __BIT(5) 52 #define MPS_CTRL_NON_SECURE_WRITE __BIT(4) 53 #define MPS_CTRL_VALID __BIT(0) 54 55 static int exynos_dwcmmc_match(device_t, cfdata_t, void *); 56 static void exynos_dwcmmc_attach(device_t, device_t, void *); 57 58 static int exynos_dwcmmc_card_detect(struct dwc_mmc_softc *); 59 static int exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *, int); 60 61 struct exynos_dwcmmc_softc { 62 struct dwc_mmc_softc sc; 63 struct clk *sc_clk_biu; 64 struct clk *sc_clk_ciu; 65 struct fdtbus_gpio_pin *sc_pin_cd; 66 u_int sc_ciu_div; 67 }; 68 69 CFATTACH_DECL_NEW(exynos_dwcmmc, sizeof(struct exynos_dwcmmc_softc), 70 exynos_dwcmmc_match, exynos_dwcmmc_attach, NULL, NULL); 71 72 static const struct device_compatible_entry compat_data[] = { 73 /* disable encryption mode? */ 74 { .compat = "samsung,exynos5250-dw-mshc", .value = 0 }, 75 { .compat = "samsung,exynos5420-dw-mshc-smu", .value = 1 }, 76 { .compat = "samsung,exynos5420-dw-mshc", .value = 0 }, 77 DEVICE_COMPAT_EOL 78 }; 79 80 static int 81 exynos_dwcmmc_match(device_t parent, cfdata_t cf, void *aux) 82 { 83 struct fdt_attach_args * const faa = aux; 84 85 return of_compatible_match(faa->faa_phandle, compat_data); 86 } 87 88 static void 89 exynos_dwcmmc_attach(device_t parent, device_t self, void *aux) 90 { 91 struct exynos_dwcmmc_softc *esc = device_private(self); 92 struct dwc_mmc_softc *sc = &esc->sc; 93 struct fdt_attach_args * const faa = aux; 94 const struct device_compatible_entry *dce; 95 const int phandle = faa->faa_phandle; 96 char intrstr[128]; 97 bus_addr_t addr; 98 bus_size_t size; 99 int error; 100 101 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 102 aprint_error(": couldn't get registers\n"); 103 return; 104 } 105 106 if (of_getprop_uint32(phandle, "samsung,dw-mshc-ciu-div", &esc->sc_ciu_div)) { 107 aprint_error(": missing samsung,dw-mshc-ciu-div property\n"); 108 return; 109 } 110 111 esc->sc_clk_biu = fdtbus_clock_get(phandle, "biu"); 112 if (esc->sc_clk_biu == NULL) { 113 aprint_error(": couldn't get clock biu\n"); 114 return; 115 } 116 esc->sc_clk_ciu = fdtbus_clock_get(phandle, "ciu"); 117 if (esc->sc_clk_ciu == NULL) { 118 aprint_error(": couldn't get clock ciu\n"); 119 return; 120 } 121 122 error = clk_enable(esc->sc_clk_biu); 123 if (error) { 124 aprint_error(": couldn't enable clock biu: %d\n", error); 125 return; 126 } 127 error = clk_enable(esc->sc_clk_ciu); 128 if (error) { 129 aprint_error(": couldn't enable clock ciu: %d\n", error); 130 return; 131 } 132 133 dce = of_compatible_lookup(faa->faa_phandle, compat_data); 134 KASSERT(dce != NULL); 135 136 sc->sc_dev = self; 137 sc->sc_bst = faa->faa_bst; 138 sc->sc_dmat = faa->faa_dmat; 139 sc->sc_intr_cardmask = DWC_MMC_INT_SDIO_INT(8); 140 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 141 if (error) { 142 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d\n", 143 addr, error); 144 return; 145 } 146 147 sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / (esc->sc_ciu_div + 1); 148 of_getprop_uint32(phandle, "fifo-depth", &sc->sc_fifo_depth); 149 sc->sc_flags = DWC_MMC_F_DMA; 150 sc->sc_bus_clock = exynos_dwcmmc_bus_clock; 151 152 esc->sc_pin_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 153 GPIO_PIN_INPUT); 154 if (esc->sc_pin_cd) 155 sc->sc_card_detect = exynos_dwcmmc_card_detect; 156 157 aprint_naive("\n"); 158 aprint_normal(": MHS (%u Hz)\n", sc->sc_clock_freq); 159 160 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 161 aprint_error_dev(self, "failed to decode interrupt\n"); 162 return; 163 } 164 165 if (dwc_mmc_init(sc) != 0) 166 return; 167 168 sc->sc_ih = fdtbus_intr_establish_xname(phandle, 0, IPL_BIO, 0, 169 dwc_mmc_intr, sc, device_xname(self)); 170 if (sc->sc_ih == NULL) { 171 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 172 intrstr); 173 return; 174 } 175 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 176 177 /* Disable encryption mode */ 178 if (dce->value != 0) { 179 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_BEGIN, 0); 180 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_END, ~0U); 181 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_CTRL, 182 MPS_CTRL_NON_SECURE_READ | MPS_CTRL_NON_SECURE_WRITE | 183 MPS_CTRL_SECURE_WRITE | MPS_CTRL_VALID); 184 } 185 } 186 187 static int 188 exynos_dwcmmc_card_detect(struct dwc_mmc_softc *sc) 189 { 190 struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 191 192 KASSERT(esc->sc_pin_cd != NULL); 193 194 return fdtbus_gpio_read(esc->sc_pin_cd); 195 } 196 197 static int 198 exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *sc, int rate) 199 { 200 struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 201 const int ciu_div = esc->sc_ciu_div + 1; 202 int error; 203 204 error = clk_set_rate(esc->sc_clk_ciu, 1000 * rate * ciu_div); 205 if (error != 0) { 206 aprint_error_dev(sc->sc_dev, "failed to set rate to %u Hz: %d\n", 207 rate * ciu_div * 1000, error); 208 return error; 209 } 210 211 sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / ciu_div; 212 213 aprint_debug_dev(sc->sc_dev, "set clock rate to %u Hz (target %u Hz)\n", 214 sc->sc_clock_freq, rate * 1000); 215 216 return 0; 217 } 218
Indexes created Mon Sep 29 21:09:56 GMT 2025