exynos_dwcmmc.c revision 1.10
1 /* $NetBSD: exynos_dwcmmc.c,v 1.10 2020/03/20 06:23:51 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: exynos_dwcmmc.c,v 1.10 2020/03/20 06:23:51 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <arm/samsung/exynos_var.h> 42 43 #include <dev/ic/dwc_mmc_reg.h> 44 #include <dev/ic/dwc_mmc_var.h> 45 #include <dev/fdt/fdtvar.h> 46 47 #define MPS_BEGIN 0x200 48 #define MPS_END 0x204 49 #define MPS_CTRL 0x20c 50 #define MPS_CTRL_SECURE_WRITE __BIT(6) 51 #define MPS_CTRL_NON_SECURE_READ __BIT(5) 52 #define MPS_CTRL_NON_SECURE_WRITE __BIT(4) 53 #define MPS_CTRL_VALID __BIT(0) 54 55 static int exynos_dwcmmc_match(device_t, cfdata_t, void *); 56 static void exynos_dwcmmc_attach(device_t, device_t, void *); 57 58 static int exynos_dwcmmc_card_detect(struct dwc_mmc_softc *); 59 static int exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *, int); 60 61 struct exynos_dwcmmc_softc { 62 struct dwc_mmc_softc sc; 63 struct clk *sc_clk_biu; 64 struct clk *sc_clk_ciu; 65 struct fdtbus_gpio_pin *sc_pin_cd; 66 u_int sc_ciu_div; 67 }; 68 69 CFATTACH_DECL_NEW(exynos_dwcmmc, sizeof(struct exynos_dwcmmc_softc), 70 exynos_dwcmmc_match, exynos_dwcmmc_attach, NULL, NULL); 71 72 static const char * const exynos_dwcmmc_compat[] = { 73 "samsung,exynos5250-dw-mshc", 74 "samsung,exynos5420-dw-mshc-smu", 75 "samsung,exynos5420-dw-mshc", 76 NULL 77 }; 78 79 static int 80 exynos_dwcmmc_match(device_t parent, cfdata_t cf, void *aux) 81 { 82 struct fdt_attach_args * const faa = aux; 83 84 return of_match_compatible(faa->faa_phandle, exynos_dwcmmc_compat); 85 } 86 87 static void 88 exynos_dwcmmc_attach(device_t parent, device_t self, void *aux) 89 { 90 struct exynos_dwcmmc_softc *esc = device_private(self); 91 struct dwc_mmc_softc *sc = &esc->sc; 92 struct fdt_attach_args * const faa = aux; 93 const int phandle = faa->faa_phandle; 94 char intrstr[128]; 95 bus_addr_t addr; 96 bus_size_t size; 97 int error; 98 99 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 100 aprint_error(": couldn't get registers\n"); 101 return; 102 } 103 104 if (of_getprop_uint32(phandle, "samsung,dw-mshc-ciu-div", &esc->sc_ciu_div)) { 105 aprint_error(": missing samsung,dw-mshc-ciu-div property\n"); 106 return; 107 } 108 109 esc->sc_clk_biu = fdtbus_clock_get(phandle, "biu"); 110 if (esc->sc_clk_biu == NULL) { 111 aprint_error(": couldn't get clock biu\n"); 112 return; 113 } 114 esc->sc_clk_ciu = fdtbus_clock_get(phandle, "ciu"); 115 if (esc->sc_clk_ciu == NULL) { 116 aprint_error(": couldn't get clock ciu\n"); 117 return; 118 } 119 120 error = clk_enable(esc->sc_clk_biu); 121 if (error) { 122 aprint_error(": couldn't enable clock biu: %d\n", error); 123 return; 124 } 125 error = clk_enable(esc->sc_clk_ciu); 126 if (error) { 127 aprint_error(": couldn't enable clock ciu: %d\n", error); 128 return; 129 } 130 131 sc->sc_dev = self; 132 sc->sc_bst = faa->faa_bst; 133 sc->sc_dmat = faa->faa_dmat; 134 sc->sc_intr_cardmask = DWC_MMC_INT_SDIO_INT(8); 135 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 136 if (error) { 137 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d\n", 138 addr, error); 139 return; 140 } 141 142 sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / (esc->sc_ciu_div + 1); 143 of_getprop_uint32(phandle, "fifo-depth", &sc->sc_fifo_depth); 144 sc->sc_flags = DWC_MMC_F_DMA; 145 sc->sc_bus_clock = exynos_dwcmmc_bus_clock; 146 147 esc->sc_pin_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 148 GPIO_PIN_INPUT); 149 if (esc->sc_pin_cd) 150 sc->sc_card_detect = exynos_dwcmmc_card_detect; 151 152 aprint_naive("\n"); 153 aprint_normal(": MHS (%u Hz)\n", sc->sc_clock_freq); 154 155 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 156 aprint_error_dev(self, "failed to decode interrupt\n"); 157 return; 158 } 159 160 if (dwc_mmc_init(sc) != 0) 161 return; 162 163 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, 164 dwc_mmc_intr, sc); 165 if (sc->sc_ih == NULL) { 166 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 167 intrstr); 168 return; 169 } 170 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 171 172 /* Disable encryption mode */ 173 const char * compat_enc[] = { "samsung,exynos5420-dw-mshc-smu", NULL }; 174 if (of_match_compatible(phandle, compat_enc)) { 175 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_BEGIN, 0); 176 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_END, ~0U); 177 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_CTRL, 178 MPS_CTRL_NON_SECURE_READ | MPS_CTRL_NON_SECURE_WRITE | 179 MPS_CTRL_SECURE_WRITE | MPS_CTRL_VALID); 180 } 181 } 182 183 static int 184 exynos_dwcmmc_card_detect(struct dwc_mmc_softc *sc) 185 { 186 struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 187 188 KASSERT(esc->sc_pin_cd != NULL); 189 190 return fdtbus_gpio_read(esc->sc_pin_cd); 191 } 192 193 static int 194 exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *sc, int rate) 195 { 196 struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 197 const int ciu_div = esc->sc_ciu_div + 1; 198 int error; 199 200 error = clk_set_rate(esc->sc_clk_ciu, 1000 * rate * ciu_div); 201 if (error != 0) { 202 aprint_error_dev(sc->sc_dev, "failed to set rate to %u Hz: %d\n", 203 rate * ciu_div * 1000, error); 204 return error; 205 } 206 207 sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / ciu_div; 208 209 aprint_debug_dev(sc->sc_dev, "set clock rate to %u Hz (target %u Hz)\n", 210 sc->sc_clock_freq, rate * 1000); 211 212 return 0; 213 } 214
Indexes created Wed Oct 01 15:09:59 GMT 2025