exynos_dwcmmc.c revision 1.6
1 /* $NetBSD: exynos_dwcmmc.c,v 1.6 2018/07/02 20:28:24 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: exynos_dwcmmc.c,v 1.6 2018/07/02 20:28:24 jmcneill Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <arm/samsung/exynos_var.h> 42 43 #include <dev/ic/dwc_mmc_var.h> 44 #include <dev/fdt/fdtvar.h> 45 46 #define FIFO_REG 0x200 47 #define MPS_BEGIN 0x200 48 #define MPS_END 0x204 49 #define MPS_CTRL 0x20c 50 #define MPS_CTRL_SECURE_WRITE __BIT(6) 51 #define MPS_CTRL_NON_SECURE_READ __BIT(5) 52 #define MPS_CTRL_NON_SECURE_WRITE __BIT(4) 53 #define MPS_CTRL_VALID __BIT(0) 54 55 static int exynos_dwcmmc_match(device_t, cfdata_t, void *); 56 static void exynos_dwcmmc_attach(device_t, device_t, void *); 57 58 static int exynos_dwcmmc_card_detect(struct dwc_mmc_softc *); 59 static int exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *, int); 60 61 struct exynos_dwcmmc_softc { 62 struct dwc_mmc_softc sc; 63 struct clk *sc_clk_biu; 64 struct clk *sc_clk_ciu; 65 struct fdtbus_gpio_pin *sc_pin_cd; 66 u_int sc_ciu_div; 67 }; 68 69 CFATTACH_DECL_NEW(exynos_dwcmmc, sizeof(struct dwc_mmc_softc), 70 exynos_dwcmmc_match, exynos_dwcmmc_attach, NULL, NULL); 71 72 static const char * const exynos_dwcmmc_compat[] = { 73 "samsung,exynos5250-dw-mshc", 74 "samsung,exynos5420-dw-mshc-smu", 75 "samsung,exynos5420-dw-mshc", 76 NULL 77 }; 78 79 static int 80 exynos_dwcmmc_match(device_t parent, cfdata_t cf, void *aux) 81 { 82 struct fdt_attach_args * const faa = aux; 83 84 return of_match_compatible(faa->faa_phandle, exynos_dwcmmc_compat); 85 } 86 87 static void 88 exynos_dwcmmc_attach(device_t parent, device_t self, void *aux) 89 { 90 struct exynos_dwcmmc_softc *esc = device_private(self); 91 struct dwc_mmc_softc *sc = &esc->sc; 92 struct fdt_attach_args * const faa = aux; 93 const int phandle = faa->faa_phandle; 94 char intrstr[128]; 95 bus_addr_t addr; 96 bus_size_t size; 97 u_int fifo_depth; 98 int error; 99 100 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 101 aprint_error(": couldn't get registers\n"); 102 return; 103 } 104 105 if (of_getprop_uint32(phandle, "fifo-depth", &fifo_depth)) { 106 fifo_depth = 64; 107 } 108 if (of_getprop_uint32(phandle, "samsung,dw-mshc-ciu-div", &esc->sc_ciu_div)) { 109 aprint_error(": missing samsung,dw-mshc-ciu-div property\n"); 110 return; 111 } 112 113 esc->sc_clk_biu = fdtbus_clock_get(phandle, "biu"); 114 if (esc->sc_clk_biu == NULL) { 115 aprint_error(": couldn't get clock biu\n"); 116 return; 117 } 118 esc->sc_clk_ciu = fdtbus_clock_get(phandle, "ciu"); 119 if (esc->sc_clk_ciu == NULL) { 120 aprint_error(": couldn't get clock ciu\n"); 121 return; 122 } 123 124 error = clk_enable(esc->sc_clk_biu); 125 if (error) { 126 aprint_error(": couldn't enable clock biu: %d\n", error); 127 return; 128 } 129 error = clk_enable(esc->sc_clk_ciu); 130 if (error) { 131 aprint_error(": couldn't enable clock ciu: %d\n", error); 132 return; 133 } 134 135 sc->sc_dev = self; 136 sc->sc_bst = faa->faa_bst; 137 sc->sc_dmat = faa->faa_dmat; 138 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 139 if (error) { 140 aprint_error(": couldn't map %#llx: %d\n", 141 (uint64_t)addr, error); 142 return; 143 } 144 145 sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / (esc->sc_ciu_div + 1); 146 sc->sc_fifo_depth = fifo_depth; 147 sc->sc_fifo_reg = FIFO_REG; 148 sc->sc_flags = DWC_MMC_F_USE_HOLD_REG | DWC_MMC_F_DMA; 149 sc->sc_bus_clock = exynos_dwcmmc_bus_clock; 150 151 esc->sc_pin_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 152 GPIO_PIN_INPUT); 153 if (esc->sc_pin_cd) 154 sc->sc_card_detect = exynos_dwcmmc_card_detect; 155 156 aprint_naive("\n"); 157 aprint_normal(": MHS (%u Hz)\n", sc->sc_clock_freq); 158 159 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 160 aprint_error_dev(self, "failed to decode interrupt\n"); 161 return; 162 } 163 164 if (dwc_mmc_init(sc) != 0) 165 return; 166 167 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, 168 dwc_mmc_intr, sc); 169 if (sc->sc_ih == NULL) { 170 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 171 intrstr); 172 return; 173 } 174 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 175 176 /* Disable encryption mode */ 177 const char * compat_enc[] = { "samsung,exynos5420-dw-mshc-smu", NULL }; 178 if (of_match_compatible(phandle, compat_enc)) { 179 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_BEGIN, 0); 180 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_END, ~0U); 181 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_CTRL, 182 MPS_CTRL_NON_SECURE_READ | MPS_CTRL_NON_SECURE_WRITE | 183 MPS_CTRL_SECURE_WRITE | MPS_CTRL_VALID); 184 } 185 } 186 187 static int 188 exynos_dwcmmc_card_detect(struct dwc_mmc_softc *sc) 189 { 190 struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 191 192 KASSERT(esc->sc_pin_cd != NULL); 193 194 return fdtbus_gpio_read(esc->sc_pin_cd); 195 } 196 197 static int 198 exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *sc, int rate) 199 { 200 struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 201 const int ciu_div = esc->sc_ciu_div + 1; 202 int error; 203 204 error = clk_set_rate(esc->sc_clk_ciu, 1000 * rate * ciu_div); 205 if (error != 0) { 206 aprint_error_dev(sc->sc_dev, "failed to set rate to %u Hz: %d\n", 207 rate * ciu_div * 1000, error); 208 return error; 209 } 210 211 sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / ciu_div; 212 213 aprint_debug_dev(sc->sc_dev, "set clock rate to %u Hz (target %u Hz)\n", 214 sc->sc_clock_freq, rate * 1000); 215 216 return 0; 217 } 218
Indexes created Wed Oct 01 13:09:50 GMT 2025