exynos_dwcmmc.c revision 1.9
1 /* $NetBSD: exynos_dwcmmc.c,v 1.9 2019/10/18 06:13:38 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: exynos_dwcmmc.c,v 1.9 2019/10/18 06:13:38 skrll Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/device.h> 35 #include <sys/intr.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 41 #include <arm/samsung/exynos_var.h> 42 43 #include <dev/ic/dwc_mmc_var.h> 44 #include <dev/fdt/fdtvar.h> 45 46 #define MPS_BEGIN 0x200 47 #define MPS_END 0x204 48 #define MPS_CTRL 0x20c 49 #define MPS_CTRL_SECURE_WRITE __BIT(6) 50 #define MPS_CTRL_NON_SECURE_READ __BIT(5) 51 #define MPS_CTRL_NON_SECURE_WRITE __BIT(4) 52 #define MPS_CTRL_VALID __BIT(0) 53 54 static int exynos_dwcmmc_match(device_t, cfdata_t, void *); 55 static void exynos_dwcmmc_attach(device_t, device_t, void *); 56 57 static int exynos_dwcmmc_card_detect(struct dwc_mmc_softc *); 58 static int exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *, int); 59 60 struct exynos_dwcmmc_softc { 61 struct dwc_mmc_softc sc; 62 struct clk *sc_clk_biu; 63 struct clk *sc_clk_ciu; 64 struct fdtbus_gpio_pin *sc_pin_cd; 65 u_int sc_ciu_div; 66 }; 67 68 CFATTACH_DECL_NEW(exynos_dwcmmc, sizeof(struct exynos_dwcmmc_softc), 69 exynos_dwcmmc_match, exynos_dwcmmc_attach, NULL, NULL); 70 71 static const char * const exynos_dwcmmc_compat[] = { 72 "samsung,exynos5250-dw-mshc", 73 "samsung,exynos5420-dw-mshc-smu", 74 "samsung,exynos5420-dw-mshc", 75 NULL 76 }; 77 78 static int 79 exynos_dwcmmc_match(device_t parent, cfdata_t cf, void *aux) 80 { 81 struct fdt_attach_args * const faa = aux; 82 83 return of_match_compatible(faa->faa_phandle, exynos_dwcmmc_compat); 84 } 85 86 static void 87 exynos_dwcmmc_attach(device_t parent, device_t self, void *aux) 88 { 89 struct exynos_dwcmmc_softc *esc = device_private(self); 90 struct dwc_mmc_softc *sc = &esc->sc; 91 struct fdt_attach_args * const faa = aux; 92 const int phandle = faa->faa_phandle; 93 char intrstr[128]; 94 bus_addr_t addr; 95 bus_size_t size; 96 int error; 97 98 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 99 aprint_error(": couldn't get registers\n"); 100 return; 101 } 102 103 if (of_getprop_uint32(phandle, "samsung,dw-mshc-ciu-div", &esc->sc_ciu_div)) { 104 aprint_error(": missing samsung,dw-mshc-ciu-div property\n"); 105 return; 106 } 107 108 esc->sc_clk_biu = fdtbus_clock_get(phandle, "biu"); 109 if (esc->sc_clk_biu == NULL) { 110 aprint_error(": couldn't get clock biu\n"); 111 return; 112 } 113 esc->sc_clk_ciu = fdtbus_clock_get(phandle, "ciu"); 114 if (esc->sc_clk_ciu == NULL) { 115 aprint_error(": couldn't get clock ciu\n"); 116 return; 117 } 118 119 error = clk_enable(esc->sc_clk_biu); 120 if (error) { 121 aprint_error(": couldn't enable clock biu: %d\n", error); 122 return; 123 } 124 error = clk_enable(esc->sc_clk_ciu); 125 if (error) { 126 aprint_error(": couldn't enable clock ciu: %d\n", error); 127 return; 128 } 129 130 sc->sc_dev = self; 131 sc->sc_bst = faa->faa_bst; 132 sc->sc_dmat = faa->faa_dmat; 133 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh); 134 if (error) { 135 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d\n", 136 addr, error); 137 return; 138 } 139 140 sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / (esc->sc_ciu_div + 1); 141 of_getprop_uint32(phandle, "fifo-depth", &sc->sc_fifo_depth); 142 sc->sc_flags = DWC_MMC_F_DMA; 143 sc->sc_bus_clock = exynos_dwcmmc_bus_clock; 144 145 esc->sc_pin_cd = fdtbus_gpio_acquire(phandle, "cd-gpios", 146 GPIO_PIN_INPUT); 147 if (esc->sc_pin_cd) 148 sc->sc_card_detect = exynos_dwcmmc_card_detect; 149 150 aprint_naive("\n"); 151 aprint_normal(": MHS (%u Hz)\n", sc->sc_clock_freq); 152 153 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 154 aprint_error_dev(self, "failed to decode interrupt\n"); 155 return; 156 } 157 158 if (dwc_mmc_init(sc) != 0) 159 return; 160 161 sc->sc_ih = fdtbus_intr_establish(phandle, 0, IPL_BIO, 0, 162 dwc_mmc_intr, sc); 163 if (sc->sc_ih == NULL) { 164 aprint_error_dev(self, "couldn't establish interrupt on %s\n", 165 intrstr); 166 return; 167 } 168 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 169 170 /* Disable encryption mode */ 171 const char * compat_enc[] = { "samsung,exynos5420-dw-mshc-smu", NULL }; 172 if (of_match_compatible(phandle, compat_enc)) { 173 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_BEGIN, 0); 174 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_END, ~0U); 175 bus_space_write_4(sc->sc_bst, sc->sc_bsh, MPS_CTRL, 176 MPS_CTRL_NON_SECURE_READ | MPS_CTRL_NON_SECURE_WRITE | 177 MPS_CTRL_SECURE_WRITE | MPS_CTRL_VALID); 178 } 179 } 180 181 static int 182 exynos_dwcmmc_card_detect(struct dwc_mmc_softc *sc) 183 { 184 struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 185 186 KASSERT(esc->sc_pin_cd != NULL); 187 188 return fdtbus_gpio_read(esc->sc_pin_cd); 189 } 190 191 static int 192 exynos_dwcmmc_bus_clock(struct dwc_mmc_softc *sc, int rate) 193 { 194 struct exynos_dwcmmc_softc *esc = device_private(sc->sc_dev); 195 const int ciu_div = esc->sc_ciu_div + 1; 196 int error; 197 198 error = clk_set_rate(esc->sc_clk_ciu, 1000 * rate * ciu_div); 199 if (error != 0) { 200 aprint_error_dev(sc->sc_dev, "failed to set rate to %u Hz: %d\n", 201 rate * ciu_div * 1000, error); 202 return error; 203 } 204 205 sc->sc_clock_freq = clk_get_rate(esc->sc_clk_ciu) / ciu_div; 206 207 aprint_debug_dev(sc->sc_dev, "set clock rate to %u Hz (target %u Hz)\n", 208 sc->sc_clock_freq, rate * 1000); 209 210 return 0; 211 } 212
Indexes created Wed Oct 01 13:09:50 GMT 2025