exynos_pinctrl.c revision 1.20 1 /* $NetBSD: exynos_pinctrl.c,v 1.20 2021/01/27 02:01:53 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2015, 2020 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Marty Fouts, and by Nick Hudson
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include "opt_exynos.h"
33 #include "opt_arm_debug.h"
34 #include "gpio.h"
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(1, "$NetBSD: exynos_pinctrl.c,v 1.20 2021/01/27 02:01:53 thorpej Exp $");
38
39 #include <sys/param.h>
40 #include <sys/bus.h>
41 #include <sys/device.h>
42 #include <sys/intr.h>
43 #include <sys/systm.h>
44 #include <sys/kmem.h>
45 #include <sys/gpio.h>
46
47 #include <dev/gpio/gpiovar.h>
48
49 #include <arm/samsung/exynos_reg.h>
50 #include <arm/samsung/exynos_var.h>
51 #include <arm/samsung/exynos_intr.h>
52 #include <arm/samsung/exynos_pinctrl.h>
53
54 #include <dev/fdt/fdtvar.h>
55
56 struct exynos_pinctrl_config {
57 int pc_phandle;
58 struct exynos_gpio_pin_cfg pc_pincfg;
59 struct exynos_pinctrl_softc *pc_sc;
60 };
61
62 static int exynos_pinctrl_match(device_t, cfdata_t, void *);
63 static void exynos_pinctrl_attach(device_t, device_t, void *);
64
65 static int exynos_pinctrl_set_cfg(device_t, const void *, size_t);
66 static void exynos_parse_config(int, struct exynos_gpio_pin_cfg *);
67
68 static struct fdtbus_pinctrl_controller_func exynos_pinctrl_controller_func = {
69 .set_config = exynos_pinctrl_set_cfg
70 };
71
72 CFATTACH_DECL_NEW(exynos_pinctrl, sizeof(struct exynos_pinctrl_softc),
73 exynos_pinctrl_match, exynos_pinctrl_attach, NULL, NULL);
74
75
76 static const struct device_compatible_entry compat_data[] = {
77 { .compat = "samsung,exynos5410-pinctrl",
78 .data = &exynos5410_pinctrl_banks },
79 { .compat = "samsung,exynos5420-pinctrl",
80 .data = &exynos5420_pinctrl_banks },
81
82 DEVICE_COMPAT_EOL
83 };
84
85 static int
86 exynos_pinctrl_match(device_t parent, cfdata_t cf, void *aux)
87 {
88 struct fdt_attach_args * const faa = aux;
89
90 return of_match_compat_data(faa->faa_phandle, compat_data);
91 }
92
93 static void
94 exynos_pinctrl_attach(device_t parent, device_t self, void *aux)
95 {
96 struct exynos_pinctrl_softc * const sc
97 = kmem_zalloc(sizeof(*sc), KM_SLEEP);
98 struct fdt_attach_args * const faa = aux;
99 bus_addr_t addr;
100 bus_size_t size;
101 int error;
102 int child;
103
104 if (fdtbus_get_reg(faa->faa_phandle, 0, &addr, &size) != 0) {
105 aprint_error(": couldn't get registers\n");
106 return;
107 }
108
109 aprint_normal(" pinctrl @ 0x%08x ", (uint)addr);
110 self->dv_private = sc;
111 sc->sc_dev = self;
112 sc->sc_bst = faa->faa_bst;
113 sc->sc_epb = of_search_compatible(faa->faa_phandle, compat_data)->data;
114
115 error = bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh);
116 if (error) {
117 aprint_error(": couldn't map %#" PRIxBUSADDR ": %d",
118 addr, error);
119 return;
120 }
121
122 aprint_naive("\n");
123 aprint_normal("\n");
124
125 for (child = OF_child(faa->faa_phandle); child;
126 child = OF_peer(child)) {
127
128 if (of_hasprop(child, "gpio-controller")) {
129 exynos_gpio_bank_config(sc, faa, child);
130 }
131
132 if (of_hasprop(child, "samsung,pins")) {
133 fdtbus_register_pinctrl_config(self, child,
134 &exynos_pinctrl_controller_func);
135 }
136 }
137 }
138
139 static void
140 exynos_parse_config(int phandle, struct exynos_gpio_pin_cfg *gc)
141 {
142 gc->cfg_valid = of_getprop_uint32(phandle, "samsung,pin-function", &gc->cfg) == 0;
143 gc->pud_valid = of_getprop_uint32(phandle, "samsung,pin-pud", &gc->pud) == 0;
144 gc->drv_valid = of_getprop_uint32(phandle, "samsung,pin-drv", &gc->drv) == 0;
145 gc->conpwd_valid = of_getprop_uint32(phandle, "samsung,pin-conpwd", &gc->conpwd) == 0;
146 gc->pudpwd_valid = of_getprop_uint32(phandle, "samsung,pin-pudpwd", &gc->pudpwd) == 0;
147 }
148
149 static int
150 exynos_parse_pin(const char *pinname)
151 {
152
153 const int len = strlen(pinname);
154
155 if (len == 0)
156 return -1;
157
158 if (pinname[len - 1] < '0' || pinname[len - 1] > '9')
159 return -1;
160
161 return pinname[len - 1] - '0';
162 }
163
164 static int
165 exynos_do_config(struct exynos_pinctrl_config *pc)
166 {
167 struct exynos_gpio_pin_cfg *gc = &pc->pc_pincfg;
168 const struct exynos_pinctrl_banks *epb = pc->pc_sc->sc_epb;
169 struct exynos_gpio_bank *bank;
170 const char *pins;
171 int pin;
172
173 int pins_len = OF_getproplen(pc->pc_phandle, "samsung,pins");
174 if (pins_len <= 0)
175 return -1;
176
177 for (pins = fdtbus_get_string(pc->pc_phandle, "samsung,pins");
178 pins_len > 0;
179 pins_len -= strlen(pins) + 1, pins += strlen(pins) + 1) {
180 bank = exynos_gpio_bank_lookup(epb, pins);
181 pin = exynos_parse_pin(pins);
182 if (bank == NULL) {
183 aprint_error_dev(pc->pc_sc->sc_dev,
184 "unknown pin name '%s'\n", pins);
185 continue;
186 }
187 exynos_gpio_pin_ctl_write(bank, gc, pin);
188 }
189
190 return 0;
191 }
192
193 static int
194 exynos_pinctrl_set_cfg(device_t dev, const void *data, size_t len)
195 {
196 struct exynos_pinctrl_config pc;
197
198 if (len != 4)
199 return -1;
200
201 pc.pc_phandle = fdtbus_get_phandle_from_native(be32dec(data));
202 pc.pc_sc = device_private(dev);
203 exynos_parse_config(pc.pc_phandle, &pc.pc_pincfg);
204
205 return exynos_do_config(&pc);
206 }
207