1 /* $NetBSD: sni_gpio.c,v 1.13 2022/01/25 10:38:56 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Socionext SC2A11 SynQuacer GPIO driver 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: sni_gpio.c,v 1.13 2022/01/25 10:38:56 nisimura Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/systm.h> 42 #include <sys/gpio.h> 43 #include <sys/kernel.h> 44 #include <sys/systm.h> 45 46 #include <machine/endian.h> 47 #include <sys/bus.h> 48 #include <sys/intr.h> 49 50 #include <dev/gpio/gpiovar.h> 51 #include <dev/fdt/fdtvar.h> 52 #include <dev/acpi/acpireg.h> 53 #include <dev/acpi/acpivar.h> 54 #include <dev/acpi/acpi_intr.h> 55 56 static int snigpio_fdt_match(device_t, struct cfdata *, void *); 57 static void snigpio_fdt_attach(device_t, device_t, void *); 58 static int snigpio_acpi_match(device_t, struct cfdata *, void *); 59 static void snigpio_acpi_attach(device_t, device_t, void *); 60 61 struct snigpio_softc { 62 device_t sc_dev; 63 bus_space_tag_t sc_iot; 64 bus_space_handle_t sc_ioh; 65 bus_addr_t sc_iob; 66 bus_size_t sc_ios; 67 void *sc_ih; 68 kmutex_t sc_lock; 69 struct gpio_chipset_tag sc_gpio_gc; 70 gpio_pin_t sc_gpio_pins[32]; 71 int sc_maxpins; 72 int sc_phandle; 73 }; 74 75 CFATTACH_DECL_NEW(snigpio_fdt, sizeof(struct snigpio_softc), 76 snigpio_fdt_match, snigpio_fdt_attach, NULL, NULL); 77 78 CFATTACH_DECL_NEW(snigpio_acpi, sizeof(struct snigpio_softc), 79 snigpio_acpi_match, snigpio_acpi_attach, NULL, NULL); 80 81 /* 82 * "DevelopmentBox" implementation 83 * DSW3-PIN1, DSW3-PIN2, DSW3-PIN3, DSW3-PIN4, 84 * DSW3-PIN5, DSW3-PIN6, DSW3-PIN7, DSW3-PIN8, 85 * PSIN#, PWROFF#, GPIO-A, GPIO-B, 86 * GPIO-C, GPIO-D, PCIE1EXTINT, PCIE0EXTINT, 87 * PHY2-INT#, PHY1-INT#, GPIO-E, GPIO-F, 88 * GPIO-G, GPIO-H, GPIO-I, GPIO-J, 89 * GPIO-K, GPIO-L, PEC-PD26, PEC-PD27, 90 * PEC-PD28, PEC-PD29, PEC-PD30, PEC-PD31 91 * 92 * DSW3-PIN1 -- erase NOR "UEFI variable store" region 93 * DSW3-PIN3 -- tweek PCIe bus implementation error toggle 94 * PowerButton (PWROFF#) can be detectable. 95 * 96 * DevelopmentBox has 96board mezzanine 2x 20 receptacle 97 * gpio "/gpio@51000000" pinA-L (23-34) down edge sensitive 98 * i2c "/i2c1@51221000" 99 * spi "/spi1@54810000" 100 * uart0 "/uart@2a400000" pin3,5,7,9 for real S2CA11 console 101 * uart1 SCP secure co-prorcessor uart console in pin11,13 102 */ 103 static void snigpio_attach_i(struct snigpio_softc *); 104 105 static const struct device_compatible_entry compat_data[] = { 106 { .compat = "socionext,synquacer-gpio" }, 107 { .compat = "fujitsu,mb86s70-gpio" }, 108 DEVICE_COMPAT_EOL 109 }; 110 static const struct device_compatible_entry compatible[] = { 111 { .compat = "SCX0007" }, 112 DEVICE_COMPAT_EOL 113 }; 114 115 static int 116 snigpio_fdt_match(device_t parent, struct cfdata *match, void *aux) 117 { 118 struct fdt_attach_args * const faa = aux; 119 120 return of_compatible_match(faa->faa_phandle, compat_data); 121 } 122 123 static void 124 snigpio_fdt_attach(device_t parent, device_t self, void *aux) 125 { 126 struct snigpio_softc * const sc = device_private(self); 127 struct fdt_attach_args * const faa = aux; 128 const int phandle = faa->faa_phandle; 129 bus_space_handle_t ioh; 130 bus_addr_t addr; 131 bus_size_t size; 132 133 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 134 || bus_space_map(faa->faa_bst, addr, size, 0, &ioh) != 0) { 135 aprint_error_dev(self, "unable to map device\n"); 136 return; 137 } 138 139 sc->sc_dev = self; 140 sc->sc_iot = faa->faa_bst; 141 sc->sc_ioh = ioh; 142 sc->sc_iob = addr; 143 sc->sc_ios = size; 144 sc->sc_phandle = phandle; 145 /* could use FDI "gpio-line-names" array via device_set_handle() */ 146 147 snigpio_attach_i(sc); 148 149 return; 150 } 151 152 static int 153 snigpio_acpi_match(device_t parent, struct cfdata *match, void *aux) 154 { 155 struct acpi_attach_args *aa = aux; 156 157 return acpi_compatible_match(aa, compatible); 158 } 159 160 static void 161 snigpio_acpi_attach(device_t parent, device_t self, void *aux) 162 { 163 struct snigpio_softc * const sc = device_private(self); 164 struct acpi_attach_args *aa = aux; 165 ACPI_HANDLE handle = aa->aa_node->ad_handle; 166 bus_space_handle_t ioh; 167 struct acpi_resources res; 168 struct acpi_mem *mem; 169 ACPI_STATUS rv; 170 char *list; 171 172 rv = acpi_resource_parse(self, aa->aa_node->ad_handle, "_CRS", 173 &res, &acpi_resource_parse_ops_default); 174 if (ACPI_FAILURE(rv)) 175 return; 176 177 mem = acpi_res_mem(&res, 0); 178 if (mem == NULL || mem->ar_length == 0) { 179 aprint_error_dev(self, "incomplete resources\n"); 180 return; 181 } 182 if (bus_space_map(aa->aa_memt, mem->ar_base, mem->ar_length, 0, 183 &ioh)) { 184 aprint_error_dev(self, "couldn't map registers\n"); 185 return; 186 } 187 188 sc->sc_dev = self; 189 sc->sc_iot = aa->aa_memt; 190 sc->sc_ioh = ioh; 191 sc->sc_ios = mem->ar_length; 192 sc->sc_phandle = 0; 193 /* UEFI provides "gpio-line-names" for us */ 194 195 aprint_normal("%s", device_xname(self)); 196 snigpio_attach_i(sc); 197 198 acpi_resource_cleanup(&res); 199 return; 200 } 201 202 static void 203 snigpio_attach_i(struct snigpio_softc *sc) 204 { 205 struct gpio_chipset_tag *gc; 206 struct gpiobus_attach_args gba; 207 208 aprint_naive("\n"); 209 aprint_normal(": Socionext GPIO controller\n"); 210 211 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 212 sc->sc_maxpins = 32; 213 214 /* create controller tag */ 215 gc = &sc->sc_gpio_gc; 216 gc->gp_cookie = sc; 217 gc->gp_pin_read = NULL; /* AAA */ 218 gc->gp_pin_write = NULL; /* AAA */ 219 gc->gp_pin_ctl = NULL; /* AAA */ 220 gc->gp_intr_establish = NULL; /* AAA */ 221 gc->gp_intr_disestablish = NULL; /* AAA */ 222 gc->gp_intr_str = NULL; /* AAA */ 223 224 gba.gba_gc = gc; 225 gba.gba_pins = &sc->sc_gpio_pins[0]; 226 gba.gba_npins = sc->sc_maxpins; 227 228 config_found(sc->sc_dev, &gba, gpiobus_print, CFARGS_NONE); 229 } 230
Indexes created Wed Sep 24 15:09:51 GMT 2025