sni_gpio.c revision 1.12
1 /* $NetBSD: sni_gpio.c,v 1.12 2021/12/21 06:00:45 nisimura Exp $ */ 2 3 /*- 4 * Copyright (c) 2020 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Tohru Nishimura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Socionext SC2A11 SynQuacer GPIO driver 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: sni_gpio.c,v 1.12 2021/12/21 06:00:45 nisimura Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/systm.h> 42 #include <sys/gpio.h> 43 #include <sys/kernel.h> 44 #include <sys/systm.h> 45 46 #include <machine/endian.h> 47 #include <sys/bus.h> 48 #include <sys/intr.h> 49 50 #include <dev/gpio/gpiovar.h> 51 #include <dev/fdt/fdtvar.h> 52 #include <dev/acpi/acpireg.h> 53 #include <dev/acpi/acpivar.h> 54 #include <dev/acpi/acpi_intr.h> 55 56 static int snigpio_fdt_match(device_t, struct cfdata *, void *); 57 static void snigpio_fdt_attach(device_t, device_t, void *); 58 static int snigpio_acpi_match(device_t, struct cfdata *, void *); 59 static void snigpio_acpi_attach(device_t, device_t, void *); 60 61 struct snigpio_softc { 62 device_t sc_dev; 63 bus_space_tag_t sc_iot; 64 bus_space_handle_t sc_ioh; 65 bus_addr_t sc_iob; 66 bus_size_t sc_ios; 67 void *sc_ih; 68 kmutex_t sc_lock; 69 struct gpio_chipset_tag sc_gpio_gc; 70 gpio_pin_t sc_gpio_pins[32]; 71 int sc_maxpins; 72 int sc_phandle; 73 }; 74 75 CFATTACH_DECL_NEW(snigpio_fdt, sizeof(struct snigpio_softc), 76 snigpio_fdt_match, snigpio_fdt_attach, NULL, NULL); 77 78 CFATTACH_DECL_NEW(snigpio_acpi, sizeof(struct snigpio_softc), 79 snigpio_acpi_match, snigpio_acpi_attach, NULL, NULL); 80 81 /* 82 * "DevelopmentBox" implementation 83 * DSW3-PIN1, DSW3-PIN2, DSW3-PIN3, DSW3-PIN4, 84 * DSW3-PIN5, DSW3-PIN6, DSW3-PIN7, DSW3-PIN8, 85 * PSIN#, PWROFF#, GPIO-A, GPIO-B, 86 * GPIO-C, GPIO-D, PCIE1EXTINT, PCIE0EXTINT, 87 * PHY2-INT#, PHY1-INT#, GPIO-E, GPIO-F, 88 * GPIO-G, GPIO-H, GPIO-I, GPIO-J, 89 * GPIO-K, GPIO-L, PEC-PD26, PEC-PD27, 90 * PEC-PD28, PEC-PD29, PEC-PD30, PEC-PD31 91 * 92 * DSW3-PIN1 -- erase NOR "UEFI variable store" region 93 * DSW3-PIN3 -- tweek PCIe bus implementation error toggle 94 * PowerButton (PWROFF#) can be detectable. 95 * 96 * DevelopmentBox has 96board mezzanine 2x 20 receptacle 97 * gpio "/gpio@51000000" pinA-L (10-25) down edge sensitive 98 * i2c "/i2c1@51221000" 99 * spi "/spi1@54810000" 100 * uart0 "/uart@2a400000" pin1-4 for real S2C11 console 101 * uart1 SCP secure co-prorcessor uart console in pin5-6 102 */ 103 static void snigpio_attach_i(struct snigpio_softc *); 104 static int snigpio_intr(void *); 105 106 static const struct device_compatible_entry compat_data[] = { 107 { .compat = "socionext,synquacer-gpio" }, 108 { .compat = "fujitsu,mb86s70-gpio" }, 109 DEVICE_COMPAT_EOL 110 }; 111 static const struct device_compatible_entry compatible[] = { 112 { .compat = "SCX0007" }, 113 DEVICE_COMPAT_EOL 114 }; 115 116 static int 117 snigpio_fdt_match(device_t parent, struct cfdata *match, void *aux) 118 { 119 struct fdt_attach_args * const faa = aux; 120 121 return of_compatible_match(faa->faa_phandle, compat_data); 122 } 123 124 static void 125 snigpio_fdt_attach(device_t parent, device_t self, void *aux) 126 { 127 struct snigpio_softc * const sc = device_private(self); 128 struct fdt_attach_args * const faa = aux; 129 const int phandle = faa->faa_phandle; 130 bus_space_handle_t ioh; 131 bus_addr_t addr; 132 bus_size_t size; 133 char intrstr[128]; 134 const char *list; 135 136 aprint_naive("\n"); 137 aprint_normal(": Socionext GPIO controller\n"); 138 139 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0 140 || bus_space_map(faa->faa_bst, addr, size, 0, &ioh) != 0) { 141 aprint_error_dev(self, "unable to map device\n"); 142 return; 143 } 144 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 145 aprint_error_dev(self, "failed to decode interrupt\n"); 146 goto fail; 147 } 148 sc->sc_ih = fdtbus_intr_establish(phandle, 149 0, IPL_VM, 0, snigpio_intr, sc); 150 if (sc->sc_ih == NULL) { 151 aprint_error_dev(self, "couldn't establish interrupt\n"); 152 goto fail; 153 } 154 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 155 156 list = fdtbus_get_string(phandle, "gpio-line-names"); 157 if (list) 158 aprint_normal_dev(self, "%s\n", list); 159 160 sc->sc_dev = self; 161 sc->sc_iot = faa->faa_bst; 162 sc->sc_ioh = ioh; 163 sc->sc_iob = addr; 164 sc->sc_ios = size; 165 sc->sc_phandle = phandle; 166 167 snigpio_attach_i(sc); 168 169 return; 170 fail: 171 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 172 return; 173 } 174 175 static int 176 snigpio_acpi_match(device_t parent, struct cfdata *match, void *aux) 177 { 178 struct acpi_attach_args *aa = aux; 179 180 return acpi_compatible_match(aa, compatible); 181 } 182 183 static void 184 snigpio_acpi_attach(device_t parent, device_t self, void *aux) 185 { 186 struct snigpio_softc * const sc = device_private(self); 187 struct acpi_attach_args *aa = aux; 188 ACPI_HANDLE handle = aa->aa_node->ad_handle; 189 bus_space_handle_t ioh; 190 struct acpi_resources res; 191 struct acpi_mem *mem; 192 struct acpi_irq *irq; 193 ACPI_STATUS rv; 194 char *list; 195 196 aprint_naive("\n"); 197 aprint_normal(": Socionext GPIO controller\n"); 198 199 rv = acpi_resource_parse(self, aa->aa_node->ad_handle, "_CRS", 200 &res, &acpi_resource_parse_ops_default); 201 if (ACPI_FAILURE(rv)) { 202 aprint_error_dev(self, "missing crs resources\n"); 203 return; 204 } 205 mem = acpi_res_mem(&res, 0); 206 irq = acpi_res_irq(&res, 0); 207 if (mem == NULL || irq == NULL || mem->ar_length == 0) { 208 aprint_error_dev(self, "incomplete resources\n"); 209 return; 210 } 211 if (bus_space_map(aa->aa_memt, mem->ar_base, mem->ar_length, 0, 212 &ioh)) { 213 aprint_error_dev(self, "couldn't map registers\n"); 214 return; 215 } 216 sc->sc_ih = acpi_intr_establish(self, (uint64_t)handle, 217 IPL_VM, false, snigpio_intr, sc, device_xname(self)); 218 if (sc->sc_ih == NULL) { 219 aprint_error_dev(self, "couldn't establish interrupt\n"); 220 goto fail; 221 } 222 rv = acpi_dsd_string(handle, "gpio-line-names", &list); 223 if (ACPI_SUCCESS(rv)) 224 aprint_normal_dev(self, "%s\n", list); 225 226 sc->sc_dev = self; 227 sc->sc_iot = aa->aa_memt; 228 sc->sc_ioh = ioh; 229 sc->sc_ios = mem->ar_length; 230 sc->sc_phandle = 0; 231 232 snigpio_attach_i(sc); 233 234 acpi_resource_cleanup(&res); 235 return; 236 fail: 237 acpi_resource_cleanup(&res); 238 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_ios); 239 return; 240 } 241 242 static void 243 snigpio_attach_i(struct snigpio_softc *sc) 244 { 245 struct gpio_chipset_tag *gc; 246 struct gpiobus_attach_args gba; 247 248 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM); 249 sc->sc_maxpins = 32; 250 251 /* create controller tag */ 252 gc = &sc->sc_gpio_gc; 253 gc->gp_cookie = sc; 254 gc->gp_pin_read = NULL; /* AAA */ 255 gc->gp_pin_write = NULL; /* AAA */ 256 gc->gp_pin_ctl = NULL; /* AAA */ 257 gc->gp_intr_establish = NULL; /* AAA */ 258 gc->gp_intr_disestablish = NULL; /* AAA */ 259 gc->gp_intr_str = NULL; /* AAA */ 260 261 gba.gba_gc = gc; 262 gba.gba_pins = &sc->sc_gpio_pins[0]; 263 gba.gba_npins = sc->sc_maxpins; 264 265 config_found(sc->sc_dev, &gba, gpiobus_print, CFARGS_NONE); 266 } 267 268 static int 269 snigpio_intr(void *arg) 270 { 271 return 1; 272 } 273
Indexes created Tue Sep 30 20:09:53 GMT 2025