sun4i_a10_ccu.c revision 1.10
1 /* $NetBSD: sun4i_a10_ccu.c,v 1.10 2019/01/22 23:06:49 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(1, "$NetBSD: sun4i_a10_ccu.c,v 1.10 2019/01/22 23:06:49 jmcneill Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/systm.h> 37 38 #include <dev/fdt/fdtvar.h> 39 40 #include <arm/sunxi/sunxi_ccu.h> 41 #include <arm/sunxi/sun4i_a10_ccu.h> 42 #include <arm/sunxi/sun7i_a20_ccu.h> 43 44 #define PLL1_CFG_REG 0x000 45 #define PLL2_CFG_REG 0x008 46 #define PLL3_CFG_REG 0x010 47 #define PLL5_CFG_REG 0x020 48 #define PLL6_CFG_REG 0x028 49 #define PLL7_CFG_REG 0x030 50 #define OSC24M_CFG_REG 0x050 51 #define CPU_AHB_APB0_CFG_REG 0x054 52 #define APB1_CLK_DIV_REG 0x058 53 #define AHB_GATING_REG0 0x060 54 #define AHB_GATING_REG1 0x064 55 #define APB0_GATING_REG 0x068 56 #define APB1_GATING_REG 0x06c 57 #define NAND_SCLK_CFG_REG 0x080 58 #define SD0_SCLK_CFG_REG 0x088 59 #define SD1_SCLK_CFG_REG 0x08c 60 #define SD2_SCLK_CFG_REG 0x090 61 #define SD3_SCLK_CFG_REG 0x094 62 #define SATA_CFG_REG 0x0c8 63 #define USBPHY_CFG_REG 0x0cc 64 #define DRAM_GATING_REG 0x100 65 #define BE0_CFG_REG 0x104 66 #define BE1_CFG_REG 0x108 67 #define FE0_CFG_REG 0x10c 68 #define FE1_CFG_REG 0x110 69 #define MP_CFG_REG 0x114 70 #define LCD0CH0_CFG_REG 0x118 71 #define LCD1CH0_CFG_REG 0x11c 72 #define LCD0CH1_CFG_REG 0x12c 73 #define LCD1CH1_CFG_REG 0x130 74 #define CSI_CFG_REG 0x134 75 #define VE_CFG_REG 0x13c 76 #define AUDIO_CODEC_SCLK_CFG_REG 0x140 77 #define LVDS_CFG_REG 0x14c 78 #define HDMI_CLOCK_CFG_REG 0x150 79 #define MALI_CLOCK_CFG_REG 0x154 80 #define IEP_SCLK_CFG_REG 0x160 81 82 static int sun4i_a10_ccu_match(device_t, cfdata_t, void *); 83 static void sun4i_a10_ccu_attach(device_t, device_t, void *); 84 85 enum sun4i_a10_ccu_type { 86 CCU_A10 = 1, 87 CCU_A20, 88 }; 89 90 static const struct of_compat_data compat_data[] = { 91 { "allwinner,sun4i-a10-ccu", CCU_A10 }, 92 { "allwinner,sun7i-a20-ccu", CCU_A20 }, 93 { NULL } 94 }; 95 96 CFATTACH_DECL_NEW(sunxi_a10_ccu, sizeof(struct sunxi_ccu_softc), 97 sun4i_a10_ccu_match, sun4i_a10_ccu_attach, NULL, NULL); 98 99 static struct sunxi_ccu_reset sun4i_a10_ccu_resets[] = { 100 SUNXI_CCU_RESET(A10_RST_USB_PHY0, USBPHY_CFG_REG, 0), 101 SUNXI_CCU_RESET(A10_RST_USB_PHY1, USBPHY_CFG_REG, 1), 102 SUNXI_CCU_RESET(A10_RST_USB_PHY2, USBPHY_CFG_REG, 2), 103 SUNXI_CCU_RESET(A10_RST_DE_BE0, BE0_CFG_REG, 30), 104 SUNXI_CCU_RESET(A10_RST_DE_BE1, BE1_CFG_REG, 30), 105 SUNXI_CCU_RESET(A10_RST_DE_FE0, FE0_CFG_REG, 30), 106 SUNXI_CCU_RESET(A10_RST_DE_FE1, FE1_CFG_REG, 30), 107 SUNXI_CCU_RESET(A10_RST_DE_MP, MP_CFG_REG, 30), 108 SUNXI_CCU_RESET(A10_RST_TCON0, LCD0CH0_CFG_REG, 30), 109 SUNXI_CCU_RESET(A10_RST_TCON1, LCD1CH0_CFG_REG, 30), 110 SUNXI_CCU_RESET(A10_RST_LVDS, LVDS_CFG_REG, 0), 111 }; 112 113 static const char *cpu_parents[] = { "losc", "osc24m", "pll_core", "pll_periph" }; 114 static const char *axi_parents[] = { "cpu" }; 115 static const char *ahb_parents[] = { "axi", "pll_periph", "pll_periph_base" }; 116 static const char *apb0_parents[] = { "ahb" }; 117 static const char *apb1_parents[] = { "osc24m", "pll_periph", "losc" }; 118 static const char *mod_parents[] = { "osc24m", "pll_periph", "pll_ddr_other" }; 119 static const char *sata_parents[] = { "pll6_periph_sata", "external" }; 120 static const char *de_parents[] = { "pll_video0", "pll_video1", "pll_ddr_other" }; 121 static const char *lcd_parents[] = { "pll_video0", "pll_video1", "pll_video0x2", "pll_video1x2" }; 122 123 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_pll1_table[] = { 124 { 1008000000, 21, 1, 0, 0 }, 125 { 960000000, 20, 1, 0, 0 }, 126 { 912000000, 19, 1, 0, 0 }, 127 { 864000000, 18, 1, 0, 0 }, 128 { 720000000, 30, 0, 0, 0 }, 129 { 624000000, 26, 0, 0, 0 }, 130 { 528000000, 22, 0, 0, 0 }, 131 { 312000000, 13, 0, 0, 0 }, 132 { 144000000, 12, 0, 0, 1 }, 133 { 0 } 134 }; 135 136 static const struct sunxi_ccu_nkmp_tbl sun4i_a10_ac_dig_table[] = { 137 { 24576000, 86, 0, 21, 4 }, 138 { 0 } 139 }; 140 141 /* 142 * some special cases 143 * hardcode lcd0 (tcon0) to pll3 and lcd1 (tcon1) to pll7. 144 * compute pll rate based on desired pixel clock 145 */ 146 147 static int sun4i_a10_ccu_lcd0ch0_set_rate(struct sunxi_ccu_softc *, 148 struct sunxi_ccu_clk *, u_int); 149 static int sun4i_a10_ccu_lcd1ch0_set_rate(struct sunxi_ccu_softc *, 150 struct sunxi_ccu_clk *, u_int); 151 static u_int sun4i_a10_ccu_lcd0ch0_round_rate(struct sunxi_ccu_softc *, 152 struct sunxi_ccu_clk *, u_int); 153 static u_int sun4i_a10_ccu_lcd1ch0_round_rate(struct sunxi_ccu_softc *, 154 struct sunxi_ccu_clk *, u_int); 155 static int sun4i_a10_ccu_lcd0ch1_set_rate(struct sunxi_ccu_softc *, 156 struct sunxi_ccu_clk *, u_int); 157 static int sun4i_a10_ccu_lcd1ch1_set_rate(struct sunxi_ccu_softc *, 158 struct sunxi_ccu_clk *, u_int); 159 160 static struct sunxi_ccu_clk sun4i_a10_ccu_clks[] = { 161 SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc", 162 OSC24M_CFG_REG, 0), 163 164 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_CORE, "pll_core", "osc24m", 165 PLL1_CFG_REG, /* reg */ 166 __BITS(12,8), /* n */ 167 __BITS(5,4), /* k */ 168 __BITS(1,0), /* m */ 169 __BITS(17,16), /* p */ 170 __BIT(31), /* enable */ 171 0, /* lock */ 172 sun4i_a10_pll1_table, /* table */ 173 SUNXI_CCU_NKMP_FACTOR_P_POW2 | SUNXI_CCU_NKMP_FACTOR_N_EXACT | 174 SUNXI_CCU_NKMP_FACTOR_N_ZERO_IS_ONE | SUNXI_CCU_NKMP_SCALE_CLOCK), 175 176 SUNXI_CCU_NKMP_TABLE(A10_CLK_PLL_AUDIO_BASE, "pll_audio", "osc24m", 177 PLL2_CFG_REG, /* reg */ 178 __BITS(14,8), /* n */ 179 0, /* k */ 180 __BITS(4,0), /* m */ 181 __BITS(29,26), /* p */ 182 __BIT(31), /* enable */ 183 0, /* lock */ 184 sun4i_a10_ac_dig_table, /* table */ 185 0), 186 187 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_BASE, "pll_periph_base", "osc24m", 188 PLL6_CFG_REG, /* reg */ 189 __BITS(12,8), /* n */ 190 __BITS(5,4), /* k */ 191 0, /* m */ 192 0, /* p */ 193 __BIT(31), /* enable */ 194 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 195 196 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_PERIPH, "pll_periph", "pll_periph_base", 197 2, 1), 198 199 SUNXI_CCU_NKMP(A10_CLK_PLL_PERIPH_SATA, "pll_periph_sata", "pll_periph_base", 200 PLL6_CFG_REG, /* reg */ 201 0, /* n */ 202 0, /* k */ 203 __BITS(1,0), /* m */ 204 0, /* p */ 205 __BIT(14), /* enable */ 206 0), 207 208 SUNXI_CCU_DIV_GATE(A10_CLK_SATA, "sata", sata_parents, 209 SATA_CFG_REG, /* reg */ 210 0, /* div */ 211 __BIT(24), /* sel */ 212 __BIT(31), /* enable */ 213 0), 214 215 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR_BASE, "pll_ddr_other", "osc24m", 216 PLL5_CFG_REG, /* reg */ 217 __BITS(12, 8), /* n */ 218 __BITS(5,4), /* k */ 219 0, /* m */ 220 __BITS(17,16), /* p */ 221 __BIT(31), /* enable */ 222 SUNXI_CCU_NKMP_FACTOR_N_EXACT | SUNXI_CCU_NKMP_FACTOR_P_POW2), 223 224 SUNXI_CCU_NKMP(A10_CLK_PLL_DDR, "pll_ddr", "osc24m", 225 PLL5_CFG_REG, /* reg */ 226 __BITS(12, 8), /* n */ 227 __BITS(5,4), /* k */ 228 __BITS(1,0), /* m */ 229 0, /* p */ 230 __BIT(31), /* enable */ 231 SUNXI_CCU_NKMP_FACTOR_N_EXACT), 232 233 SUNXI_CCU_DIV(A10_CLK_CPU, "cpu", cpu_parents, 234 CPU_AHB_APB0_CFG_REG, /* reg */ 235 0, /* div */ 236 __BITS(17,16), /* sel */ 237 SUNXI_CCU_DIV_SET_RATE_PARENT), 238 239 SUNXI_CCU_DIV(A10_CLK_AXI, "axi", axi_parents, 240 CPU_AHB_APB0_CFG_REG, /* reg */ 241 __BITS(1,0), /* div */ 242 0, /* sel */ 243 0), 244 245 SUNXI_CCU_DIV(A10_CLK_AHB, "ahb", ahb_parents, 246 CPU_AHB_APB0_CFG_REG, /* reg */ 247 __BITS(5,4), /* div */ 248 __BITS(7,6), /* sel */ 249 SUNXI_CCU_DIV_POWER_OF_TWO), 250 251 SUNXI_CCU_DIV(A10_CLK_APB0, "apb0", apb0_parents, 252 CPU_AHB_APB0_CFG_REG, /* reg */ 253 __BITS(9,8), /* div */ 254 0, /* sel */ 255 SUNXI_CCU_DIV_ZERO_IS_ONE | SUNXI_CCU_DIV_POWER_OF_TWO), 256 257 SUNXI_CCU_NM(A10_CLK_APB1, "apb1", apb1_parents, 258 APB1_CLK_DIV_REG, /* reg */ 259 __BITS(17,16), /* n */ 260 __BITS(4,0), /* m */ 261 __BITS(25,24), /* sel */ 262 0, /* enable */ 263 SUNXI_CCU_NM_POWER_OF_TWO), 264 265 SUNXI_CCU_NM(A10_CLK_NAND, "nand", mod_parents, 266 NAND_SCLK_CFG_REG, /* reg */ 267 __BITS(17,16), /* n */ 268 __BITS(3,0), /* m */ 269 __BITS(25,24), /* sel */ 270 __BIT(31), /* enable */ 271 SUNXI_CCU_NM_POWER_OF_TWO), 272 273 SUNXI_CCU_NM(A10_CLK_MMC0, "mmc0", mod_parents, 274 SD0_SCLK_CFG_REG, /* reg */ 275 __BITS(17,16), /* n */ 276 __BITS(3,0), /* m */ 277 __BITS(25,24), /* sel */ 278 __BIT(31), /* enable */ 279 SUNXI_CCU_NM_POWER_OF_TWO), 280 SUNXI_CCU_PHASE(A10_CLK_MMC0_SAMPLE, "mmc0_sample", "mmc0", 281 SD0_SCLK_CFG_REG, __BITS(22,20)), 282 SUNXI_CCU_PHASE(A10_CLK_MMC0_OUTPUT, "mmc0_output", "mmc0", 283 SD0_SCLK_CFG_REG, __BITS(10,8)), 284 SUNXI_CCU_NM(A10_CLK_MMC1, "mmc1", mod_parents, 285 SD1_SCLK_CFG_REG, /* reg */ 286 __BITS(17,16), /* n */ 287 __BITS(3,0), /* m */ 288 __BITS(25,24), /* sel */ 289 __BIT(31), /* enable */ 290 SUNXI_CCU_NM_POWER_OF_TWO), 291 SUNXI_CCU_PHASE(A10_CLK_MMC1_SAMPLE, "mmc1_sample", "mmc1", 292 SD1_SCLK_CFG_REG, __BITS(22,20)), 293 SUNXI_CCU_PHASE(A10_CLK_MMC1_OUTPUT, "mmc1_output", "mmc1", 294 SD1_SCLK_CFG_REG, __BITS(10,8)), 295 SUNXI_CCU_NM(A10_CLK_MMC2, "mmc2", mod_parents, 296 SD2_SCLK_CFG_REG, /* reg */ 297 __BITS(17,16), /* n */ 298 __BITS(3,0), /* m */ 299 __BITS(25,24), /* sel */ 300 __BIT(31), /* enable */ 301 SUNXI_CCU_NM_POWER_OF_TWO), 302 SUNXI_CCU_PHASE(A10_CLK_MMC2_SAMPLE, "mmc2_sample", "mmc2", 303 SD2_SCLK_CFG_REG, __BITS(22,20)), 304 SUNXI_CCU_PHASE(A10_CLK_MMC2_OUTPUT, "mmc2_output", "mmc2", 305 SD2_SCLK_CFG_REG, __BITS(10,8)), 306 SUNXI_CCU_NM(A10_CLK_MMC3, "mmc3", mod_parents, 307 SD3_SCLK_CFG_REG, /* reg */ 308 __BITS(17,16), /* n */ 309 __BITS(3,0), /* m */ 310 __BITS(25,24), /* sel */ 311 __BIT(31), /* enable */ 312 SUNXI_CCU_NM_POWER_OF_TWO), 313 SUNXI_CCU_PHASE(A10_CLK_MMC3_SAMPLE, "mmc3_sample", "mmc3", 314 SD3_SCLK_CFG_REG, __BITS(22,20)), 315 SUNXI_CCU_PHASE(A10_CLK_MMC3_OUTPUT, "mmc3_output", "mmc3", 316 SD3_SCLK_CFG_REG, __BITS(10,8)), 317 318 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO0, "pll_video0", "osc24m", 319 PLL3_CFG_REG, /* reg */ 320 __BITS(7,0), /* m */ 321 9, /* m_min */ 322 127, /* m_max */ 323 __BIT(15), /* div_en */ 324 __BIT(14), /* frac_sel */ 325 270000000, 297000000, /* frac values */ 326 0, /* prediv */ 327 8, /* prediv_val */ 328 __BIT(31), /* enable */ 329 0), 330 SUNXI_CCU_FRACTIONAL(A10_CLK_PLL_VIDEO1, "pll_video1", "osc24m", 331 PLL7_CFG_REG, /* reg */ 332 __BITS(7,0), /* m */ 333 9, /* m_min */ 334 127, /* m_max */ 335 __BIT(15), /* div_en */ 336 __BIT(14), /* frac_sel */ 337 270000000, 297000000, /* frac values */ 338 0, /* prediv */ 339 8, /* prediv_val */ 340 __BIT(31), /* enable */ 341 0), 342 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO0_2X, 343 "pll_video0x2", "pll_video0", 344 1, 2), 345 SUNXI_CCU_FIXED_FACTOR(A10_CLK_PLL_VIDEO1_2X, 346 "pll_video1x2", "pll_video1", 347 1, 2), 348 349 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE0, "debe0-mod", de_parents, 350 BE0_CFG_REG, /* reg */ 351 __BITS(3,0), /* div */ 352 __BITS(25,24), /* sel */ 353 __BIT(31), /* enable */ 354 0 /* flags */ 355 ), 356 SUNXI_CCU_DIV_GATE(A10_CLK_DE_BE1, "debe1-mod", de_parents, 357 BE1_CFG_REG, /* reg */ 358 __BITS(3,0), /* div */ 359 __BITS(25,24), /* sel */ 360 __BIT(31), /* enable */ 361 0 /* flags */ 362 ), 363 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE0, "defe0-mod", de_parents, 364 FE0_CFG_REG, /* reg */ 365 __BITS(3,0), /* div */ 366 __BITS(25,24), /* sel */ 367 __BIT(31), /* enable */ 368 0 /* flags */ 369 ), 370 SUNXI_CCU_DIV_GATE(A10_CLK_DE_FE1, "defe1-mod", de_parents, 371 FE1_CFG_REG, /* reg */ 372 __BITS(3,0), /* div */ 373 __BITS(25,24), /* sel */ 374 __BIT(31), /* enable */ 375 0 /* flags */ 376 ), 377 [A10_CLK_TCON0_CH0] = { 378 .type = SUNXI_CCU_DIV, 379 .base.name = "tcon0-ch0", 380 .u.div.reg = LCD0CH0_CFG_REG, 381 .u.div.parents = lcd_parents, 382 .u.div.nparents = __arraycount(lcd_parents), 383 .u.div.div = 0, 384 .u.div.sel = __BITS(25,24), 385 .u.div.enable = __BIT(31), 386 .u.div.flags = 0, 387 .enable = sunxi_ccu_div_enable, 388 .get_rate = sunxi_ccu_div_get_rate, 389 .set_rate = sun4i_a10_ccu_lcd0ch0_set_rate, 390 .round_rate = sun4i_a10_ccu_lcd0ch0_round_rate, 391 .set_parent = sunxi_ccu_div_set_parent, 392 .get_parent = sunxi_ccu_div_get_parent, 393 }, 394 [A10_CLK_TCON1_CH0] = { 395 .type = SUNXI_CCU_DIV, 396 .base.name = "tcon1-ch0", 397 .u.div.reg = LCD1CH0_CFG_REG, 398 .u.div.parents = lcd_parents, 399 .u.div.nparents = __arraycount(lcd_parents), 400 .u.div.div = 0, 401 .u.div.sel = __BITS(25,24), 402 .u.div.enable = __BIT(31), 403 .u.div.flags = 0, 404 .enable = sunxi_ccu_div_enable, 405 .get_rate = sunxi_ccu_div_get_rate, 406 .set_rate = sun4i_a10_ccu_lcd1ch0_set_rate, 407 .round_rate = sun4i_a10_ccu_lcd1ch0_round_rate, 408 .set_parent = sunxi_ccu_div_set_parent, 409 .get_parent = sunxi_ccu_div_get_parent, 410 }, 411 [A10_CLK_TCON0_CH1] = { 412 .type = SUNXI_CCU_DIV, 413 .base.name = "tcon0-ch1", 414 .u.div.reg = LCD0CH1_CFG_REG, 415 .u.div.parents = lcd_parents, 416 .u.div.nparents = __arraycount(lcd_parents), 417 .u.div.div = __BITS(3,0), 418 .u.div.sel = __BITS(25,24), 419 .u.div.enable = __BIT(15) | __BIT(31), 420 .u.div.flags = 0, 421 .enable = sunxi_ccu_div_enable, 422 .get_rate = sunxi_ccu_div_get_rate, 423 .set_rate = sun4i_a10_ccu_lcd0ch1_set_rate, 424 .set_parent = sunxi_ccu_div_set_parent, 425 .get_parent = sunxi_ccu_div_get_parent, 426 }, 427 [A10_CLK_TCON1_CH1] = { 428 .type = SUNXI_CCU_DIV, 429 .base.name = "tcon1-ch1", 430 .u.div.reg = LCD1CH1_CFG_REG, 431 .u.div.parents = lcd_parents, 432 .u.div.nparents = __arraycount(lcd_parents), 433 .u.div.div = __BITS(3,0), 434 .u.div.sel = __BITS(25,24), 435 .u.div.enable = __BIT(15) | __BIT(31), 436 .u.div.flags = 0, 437 .enable = sunxi_ccu_div_enable, 438 .get_rate = sunxi_ccu_div_get_rate, 439 .set_rate = sun4i_a10_ccu_lcd1ch1_set_rate, 440 .set_parent = sunxi_ccu_div_set_parent, 441 .get_parent = sunxi_ccu_div_get_parent, 442 }, 443 SUNXI_CCU_DIV_GATE(A10_CLK_HDMI, "hdmi-mod", lcd_parents, 444 HDMI_CLOCK_CFG_REG, /* reg */ 445 __BITS(3,0), /* div */ 446 __BITS(25,24), /* sel */ 447 __BIT(31), /* enable */ 448 0 /* flags */ 449 ), 450 451 /* AHB_GATING_REG0 */ 452 SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb", 453 AHB_GATING_REG0, 0), 454 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 455 AHB_GATING_REG0, 1), 456 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 457 AHB_GATING_REG0, 2), 458 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 459 AHB_GATING_REG0, 3), 460 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 461 AHB_GATING_REG0, 4), 462 SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb", 463 AHB_GATING_REG0, 5), 464 SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb", 465 AHB_GATING_REG0, 6), 466 SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb", 467 AHB_GATING_REG0, 7), 468 SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb", 469 AHB_GATING_REG0, 8), 470 SUNXI_CCU_GATE(A10_CLK_AHB_MMC1, "ahb-mmc1", "ahb", 471 AHB_GATING_REG0, 9), 472 SUNXI_CCU_GATE(A10_CLK_AHB_MMC2, "ahb-mmc2", "ahb", 473 AHB_GATING_REG0, 10), 474 SUNXI_CCU_GATE(A10_CLK_AHB_MMC3, "ahb-mmc3", "ahb", 475 AHB_GATING_REG0, 11), 476 SUNXI_CCU_GATE(A10_CLK_AHB_MS, "ahb-ms", "ahb", 477 AHB_GATING_REG0, 12), 478 SUNXI_CCU_GATE(A10_CLK_AHB_NAND, "ahb-nand", "ahb", 479 AHB_GATING_REG0, 13), 480 SUNXI_CCU_GATE(A10_CLK_AHB_SDRAM, "ahb-sdram", "ahb", 481 AHB_GATING_REG0, 14), 482 SUNXI_CCU_GATE(A10_CLK_AHB_ACE, "ahb-ace", "ahb", 483 AHB_GATING_REG0, 16), 484 SUNXI_CCU_GATE(A10_CLK_AHB_EMAC, "ahb-emac", "ahb", 485 AHB_GATING_REG0, 17), 486 SUNXI_CCU_GATE(A10_CLK_AHB_TS, "ahb-ts", "ahb", 487 AHB_GATING_REG0, 18), 488 SUNXI_CCU_GATE(A10_CLK_AHB_SPI0, "ahb-spi0", "ahb", 489 AHB_GATING_REG0, 20), 490 SUNXI_CCU_GATE(A10_CLK_AHB_SPI1, "ahb-spi1", "ahb", 491 AHB_GATING_REG0, 21), 492 SUNXI_CCU_GATE(A10_CLK_AHB_SPI2, "ahb-spi2", "ahb", 493 AHB_GATING_REG0, 22), 494 SUNXI_CCU_GATE(A10_CLK_AHB_SPI3, "ahb-spi3", "ahb", 495 AHB_GATING_REG0, 23), 496 SUNXI_CCU_GATE(A10_CLK_AHB_SATA, "ahb-sata", "ahb", 497 AHB_GATING_REG0, 25), 498 SUNXI_CCU_GATE(A10_CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 499 AHB_GATING_REG0, 28), 500 501 /* AHB_GATING_REG1. Missing: TVE, HDMI */ 502 SUNXI_CCU_GATE(A10_CLK_AHB_VE, "ahb-ve", "ahb", 503 AHB_GATING_REG1, 0), 504 SUNXI_CCU_GATE(A10_CLK_AHB_TVD, "ahb-tvd", "ahb", 505 AHB_GATING_REG1, 1), 506 SUNXI_CCU_GATE(A10_CLK_AHB_TVE0, "ahb-tve0", "ahb", 507 AHB_GATING_REG1, 2), 508 SUNXI_CCU_GATE(A10_CLK_AHB_TVE1, "ahb-tve1", "ahb", 509 AHB_GATING_REG1, 3), 510 SUNXI_CCU_GATE(A10_CLK_AHB_LCD0, "ahb-lcd0", "ahb", 511 AHB_GATING_REG1, 4), 512 SUNXI_CCU_GATE(A10_CLK_AHB_LCD1, "ahb-lcd1", "ahb", 513 AHB_GATING_REG1, 5), 514 SUNXI_CCU_GATE(A10_CLK_AHB_CSI0, "ahb-csi0", "ahb", 515 AHB_GATING_REG1, 8), 516 SUNXI_CCU_GATE(A10_CLK_AHB_CSI1, "ahb-csi1", "ahb", 517 AHB_GATING_REG1, 9), 518 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 519 AHB_GATING_REG1, 10), 520 SUNXI_CCU_GATE(A10_CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 521 AHB_GATING_REG1, 11), 522 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 523 AHB_GATING_REG1, 12), 524 SUNXI_CCU_GATE(A10_CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 525 AHB_GATING_REG1, 13), 526 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 527 AHB_GATING_REG1, 14), 528 SUNXI_CCU_GATE(A10_CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 529 AHB_GATING_REG1, 15), 530 SUNXI_CCU_GATE(A10_CLK_AHB_GMAC, "ahb-gmac", "ahb", 531 AHB_GATING_REG1, 17), 532 SUNXI_CCU_GATE(A10_CLK_AHB_MP, "ahb-mp", "ahb", 533 AHB_GATING_REG1, 18), 534 SUNXI_CCU_GATE(A10_CLK_AHB_GPU, "ahb-gpu", "ahb", 535 AHB_GATING_REG1, 20), 536 537 /* APB0_GATING_REG */ 538 SUNXI_CCU_GATE(A10_CLK_APB0_CODEC, "apb0-codec", "apb0", 539 APB0_GATING_REG, 0), 540 SUNXI_CCU_GATE(A10_CLK_APB0_SPDIF, "apb0-spdif", "apb0", 541 APB0_GATING_REG, 1), 542 SUNXI_CCU_GATE(A10_CLK_APB0_AC97, "apb0-ac97", "apb0", 543 APB0_GATING_REG, 2), 544 SUNXI_CCU_GATE(A10_CLK_APB0_I2S0, "apb0-i2s0", "apb0", 545 APB0_GATING_REG, 3), 546 SUNXI_CCU_GATE(A10_CLK_APB0_I2S1, "apb0-i2s1", "apb0", 547 APB0_GATING_REG, 4), 548 SUNXI_CCU_GATE(A10_CLK_APB0_PIO, "apb0-pio", "apb0", 549 APB0_GATING_REG, 5), 550 SUNXI_CCU_GATE(A10_CLK_APB0_IR0, "apb0-ir0", "apb0", 551 APB0_GATING_REG, 6), 552 SUNXI_CCU_GATE(A10_CLK_APB0_IR1, "apb0-ir1", "apb0", 553 APB0_GATING_REG, 7), 554 SUNXI_CCU_GATE(A10_CLK_APB0_I2S2, "apb0-i2s2", "apb0", 555 APB0_GATING_REG, 8), 556 SUNXI_CCU_GATE(A10_CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 557 APB0_GATING_REG, 10), 558 559 /* APB1_GATING_REG */ 560 SUNXI_CCU_GATE(A10_CLK_APB1_I2C0, "apb1-i2c0", "apb1", 561 APB1_GATING_REG, 0), 562 SUNXI_CCU_GATE(A10_CLK_APB1_I2C1, "apb1-i2c1", "apb1", 563 APB1_GATING_REG, 1), 564 SUNXI_CCU_GATE(A10_CLK_APB1_I2C2, "apb1-i2c2", "apb1", 565 APB1_GATING_REG, 2), 566 SUNXI_CCU_GATE(A10_CLK_APB1_I2C3, "apb1-i2c3", "apb1", 567 APB1_GATING_REG, 3), 568 SUNXI_CCU_GATE(A10_CLK_APB1_CAN, "apb1-can", "apb1", 569 APB1_GATING_REG, 4), 570 SUNXI_CCU_GATE(A10_CLK_APB1_SCR, "apb1-scr", "apb1", 571 APB1_GATING_REG, 5), 572 SUNXI_CCU_GATE(A10_CLK_APB1_PS20, "apb1-ps20", "apb1", 573 APB1_GATING_REG, 6), 574 SUNXI_CCU_GATE(A10_CLK_APB1_PS21, "apb1-ps21", "apb1", 575 APB1_GATING_REG, 7), 576 SUNXI_CCU_GATE(A10_CLK_APB1_I2C4, "apb1-i2c4", "apb1", 577 APB1_GATING_REG, 15), 578 SUNXI_CCU_GATE(A10_CLK_APB1_UART0, "apb1-uart0", "apb1", 579 APB1_GATING_REG, 16), 580 SUNXI_CCU_GATE(A10_CLK_APB1_UART1, "apb1-uart1", "apb1", 581 APB1_GATING_REG, 17), 582 SUNXI_CCU_GATE(A10_CLK_APB1_UART2, "apb1-uart2", "apb1", 583 APB1_GATING_REG, 18), 584 SUNXI_CCU_GATE(A10_CLK_APB1_UART3, "apb1-uart3", "apb1", 585 APB1_GATING_REG, 19), 586 SUNXI_CCU_GATE(A10_CLK_APB1_UART4, "apb1-uart4", "apb1", 587 APB1_GATING_REG, 20), 588 SUNXI_CCU_GATE(A10_CLK_APB1_UART5, "apb1-uart5", "apb1", 589 APB1_GATING_REG, 21), 590 SUNXI_CCU_GATE(A10_CLK_APB1_UART6, "apb1-uart6", "apb1", 591 APB1_GATING_REG, 22), 592 SUNXI_CCU_GATE(A10_CLK_APB1_UART7, "apb1-uart7", "apb1", 593 APB1_GATING_REG, 23), 594 595 /* DRAM GATING */ 596 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE0, "dram-de-be0", "pll_ddr_other", 597 DRAM_GATING_REG, 26), 598 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_BE1, "dram-de-be1", "pll_ddr_other", 599 DRAM_GATING_REG, 27), 600 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE0, "dram-de-fe0", "pll_ddr_other", 601 DRAM_GATING_REG, 25), 602 SUNXI_CCU_GATE(A10_CLK_DRAM_DE_FE1, "dram-de-fe1", "pll_ddr_other", 603 DRAM_GATING_REG, 24), 604 605 /* AUDIO_CODEC_SCLK_CFG_REG */ 606 SUNXI_CCU_GATE(A10_CLK_CODEC, "codec", "pll_audio", 607 AUDIO_CODEC_SCLK_CFG_REG, 31), 608 609 /* USBPHY_CFG_REG */ 610 SUNXI_CCU_GATE(A10_CLK_USB_OHCI0, "usb-ohci0", "osc24m", 611 USBPHY_CFG_REG, 6), 612 SUNXI_CCU_GATE(A10_CLK_USB_OHCI1, "usb-ohci1", "osc24m", 613 USBPHY_CFG_REG, 7), 614 SUNXI_CCU_GATE(A10_CLK_USB_PHY, "usb-phy", "osc24m", 615 USBPHY_CFG_REG, 8), 616 }; 617 618 /* 619 * some special cases 620 * hardcode lcd0 (tcon0) to pll3 and lcd1 (tcon1) to pll7. 621 * compute pll rate based on desired pixel clock 622 */ 623 624 static int 625 sun4i_a10_ccu_lcd0ch0_set_rate(struct sunxi_ccu_softc *sc, 626 struct sunxi_ccu_clk * clk, u_int rate) 627 { 628 int error; 629 error = sunxi_ccu_lcdxch0_set_rate(sc, clk, 630 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 631 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 632 rate); 633 return error; 634 } 635 636 static int 637 sun4i_a10_ccu_lcd1ch0_set_rate(struct sunxi_ccu_softc *sc, 638 struct sunxi_ccu_clk * clk, u_int rate) 639 { 640 return sunxi_ccu_lcdxch0_set_rate(sc, clk, 641 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 642 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 643 rate); 644 } 645 646 static u_int 647 sun4i_a10_ccu_lcd0ch0_round_rate(struct sunxi_ccu_softc *sc, 648 struct sunxi_ccu_clk * clk, u_int rate) 649 { 650 return sunxi_ccu_lcdxch0_round_rate(sc, clk, 651 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 652 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 653 rate); 654 } 655 656 static u_int 657 sun4i_a10_ccu_lcd1ch0_round_rate(struct sunxi_ccu_softc *sc, 658 struct sunxi_ccu_clk * clk, u_int rate) 659 { 660 return sunxi_ccu_lcdxch0_round_rate(sc, clk, 661 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 662 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 663 rate); 664 } 665 666 static int 667 sun4i_a10_ccu_lcd0ch1_set_rate(struct sunxi_ccu_softc *sc, 668 struct sunxi_ccu_clk * clk, u_int rate) 669 { 670 return sunxi_ccu_lcdxch1_set_rate(sc, clk, 671 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0], 672 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO0_2X], 673 rate); 674 } 675 676 static int 677 sun4i_a10_ccu_lcd1ch1_set_rate(struct sunxi_ccu_softc *sc, 678 struct sunxi_ccu_clk * clk, u_int rate) 679 { 680 return sunxi_ccu_lcdxch1_set_rate(sc, clk, 681 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1], 682 &sun4i_a10_ccu_clks[A10_CLK_PLL_VIDEO1_2X], 683 rate); 684 } 685 686 #if 0 687 static int 688 sun4i_a10_ccu_lcdxch0_set_rate(struct sunxi_ccu_softc *sc, 689 struct sunxi_ccu_clk * clk, u_int rate, int unit) 690 { 691 int parent_index; 692 struct clk *clkp; 693 int error; 694 695 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 696 clkp = &sun4i_a10_ccu_clks[parent_index].base; 697 error = clk_set_rate(clkp, rate); 698 if (error) { 699 error = clk_set_rate(clkp, rate / 2); 700 if (error != 0) 701 return error; 702 parent_index = 703 (unit == 0) ? A10_CLK_PLL_VIDEO0_2X : A10_CLK_PLL_VIDEO1_2X; 704 clkp = &sun4i_a10_ccu_clks[parent_index].base; 705 } 706 error = clk_set_parent(&clk->base, clkp); 707 KASSERT(error == 0); 708 return error; 709 } 710 711 static u_int 712 sun4i_a10_ccu_lcdxch0_round_rate(struct sunxi_ccu_softc *sc, 713 struct sunxi_ccu_clk * clk, u_int try_rate, int unit) 714 { 715 int parent_index; 716 struct clk *clkp; 717 int diff, diff_x2; 718 int rate, rate_x2; 719 720 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 721 clkp = &sun4i_a10_ccu_clks[parent_index].base; 722 rate = clk_round_rate(clkp, try_rate); 723 diff = abs(try_rate - rate); 724 725 rate_x2 = (clk_round_rate(clkp, try_rate / 2) * 2); 726 diff_x2 = abs(try_rate - rate_x2); 727 728 if (diff_x2 < diff) 729 return rate_x2; 730 return rate; 731 } 732 733 static void 734 sun4i_a10_tcon_calc_pll(int f_ref, int f_out, int *pm, int *pn, int *pd) 735 { 736 int best = INT_MAX; 737 for (int d = 1; d <= 2 && best != 0; d++) { 738 for (int m = 1; m <= 16 && best != 0; m++) { 739 for (int n = 9; n <= 127 && best != 0; n++) { 740 int f_cur = (n * f_ref * d) / m; 741 int diff = abs(f_out - f_cur); 742 if (diff < best) { 743 best = diff; 744 *pm = m; 745 *pn = n; 746 *pd = d; 747 if (diff == 0) 748 return; 749 } 750 } 751 } 752 } 753 } 754 755 static int 756 sun4i_a10_ccu_lcdxch1_set_rate(struct sunxi_ccu_softc *sc, 757 struct sunxi_ccu_clk *clk, u_int rate, int unit) 758 { 759 int parent_index; 760 struct clk *clkp, *pllclk; 761 int error; 762 int n = 0, m = 0, d = 0; 763 764 parent_index = (unit == 0) ? A10_CLK_PLL_VIDEO0 : A10_CLK_PLL_VIDEO1; 765 clkp = &sun4i_a10_ccu_clks[parent_index].base; 766 pllclk = clkp; 767 768 sun4i_a10_tcon_calc_pll(3000000, rate, &m, &n, &d); 769 770 if (n == 0 || m == 0 || d == 0) 771 return ERANGE; 772 773 if (d == 2) { 774 parent_index = 775 (unit == 0) ? A10_CLK_PLL_VIDEO0_2X : A10_CLK_PLL_VIDEO1_2X; 776 clkp = &sun4i_a10_ccu_clks[parent_index].base; 777 } 778 779 error = clk_set_rate(pllclk, 3000000 * n); 780 KASSERT(error == 0); 781 error = clk_set_parent(&clk->base, clkp); 782 KASSERT(error == 0); 783 error = sunxi_ccu_div_set_rate(sc, clk, rate); 784 KASSERT(error == 0); 785 return error; 786 } 787 #endif 788 789 static int 790 sun4i_a10_ccu_match(device_t parent, cfdata_t cf, void *aux) 791 { 792 struct fdt_attach_args * const faa = aux; 793 794 return of_match_compat_data(faa->faa_phandle, compat_data); 795 } 796 797 static struct sunxi_ccu_softc *sc0; 798 static void 799 sun4i_a10_ccu_attach(device_t parent, device_t self, void *aux) 800 { 801 struct sunxi_ccu_softc * const sc = device_private(self); 802 struct fdt_attach_args * const faa = aux; 803 enum sun4i_a10_ccu_type type; 804 struct clk *clk, *clkp; 805 int error; 806 807 sc->sc_dev = self; 808 sc->sc_phandle = faa->faa_phandle; 809 sc->sc_bst = faa->faa_bst; 810 811 sc->sc_resets = sun4i_a10_ccu_resets; 812 sc->sc_nresets = __arraycount(sun4i_a10_ccu_resets); 813 814 sc->sc_clks = sun4i_a10_ccu_clks; 815 sc->sc_nclks = __arraycount(sun4i_a10_ccu_clks); 816 817 if (sunxi_ccu_attach(sc) != 0) 818 return; 819 820 aprint_naive("\n"); 821 822 type = of_search_compatible(faa->faa_phandle, compat_data)->data; 823 824 switch (type) { 825 case CCU_A10: 826 aprint_normal(": A10 CCU\n"); 827 break; 828 case CCU_A20: 829 aprint_normal(": A20 CCU\n"); 830 break; 831 } 832 /* hardcode debe clocks parent to PLL5 */ 833 clkp = &sun4i_a10_ccu_clks[A10_CLK_PLL_DDR_BASE].base; 834 clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE0].base; 835 error = clk_set_parent(clk, clkp); 836 KASSERT(error == 0); 837 clk = &sun4i_a10_ccu_clks[A10_CLK_DE_BE1].base; 838 error = clk_set_parent(clk, clkp); 839 KASSERT(error == 0); 840 841 (void)error; 842 sunxi_ccu_print(sc); 843 sc0 = sc; 844 } 845 846 void sun4i_ccu_print(void); 847 void 848 sun4i_ccu_print(void) 849 { 850 sunxi_ccu_print(sc0); 851 } 852
Indexes created Thu Oct 02 01:09:59 GMT 2025