| History log of /src/sys/arch/arm/sunxi/sun4i_a10_ccu.c |
| Revision | | Date | Author | Comments |
| 1.16 |
| 27-Jan-2021 |
thorpej | branches: 1.16.16;
Rename of_match_compat_data() to of_compatible_match(). Similarly,
rename of_search_compatible() to of_compatible_lookup().
Standardize on of_compatible_match() for driver matching, and adapt
all call sites.
|
| 1.15 |
| 27-Jan-2021 |
thorpej | Use DEVICE_COMPAT_EOL.
|
| 1.14 |
| 25-Jan-2021 |
thorpej | Since we're using designated initialisers for compat data, we should
use a completely empty initializer for the sentinel.
|
| 1.13 |
| 18-Jan-2021 |
thorpej | Remove "struct of_compat_data" and replace its usage with
"struct device_compatible_entry"; they are ABI-compatible.
Fix several "loses const qualifier" bugs encountered during
this conversion.
|
| 1.12 |
| 07-May-2020 |
jmcneill | branches: 1.12.2;
Add A20 CLK_OUT_A and CLK_OUT_B clocks
|
| 1.11 |
| 01-Aug-2019 |
tnn | sun4i: enable clocks for SPI[0-3], needed by sun4i_spi
|
| 1.10 |
| 22-Jan-2019 |
jmcneill | branches: 1.10.4;
Add sun50i DE clocks.
|
| 1.9 |
| 02-Apr-2018 |
bouyer | branches: 1.9.2;
Add missing A10_RST_LVDS entry
fix sun4i_a10_ac_dig_table[] with values from arm/allwinner/,
audio plays at the right rate again on my lime2
|
| 1.8 |
| 01-Apr-2018 |
bouyer | Add a round_rate() callback for the sunxi clock domain.
Add a sunxi_ccu_display.c file with helpers for setting up display engine
clocks.
for fractional clocks, rename frac_en to div_en, I got the logic inverted.
Adjust tcon0-ch0, tcon0-ch1, tcon1-ch0 and tcon1-ch1 definitions to
automatically select a parent. tcon0 hardcoded to pll3 and tcon1 to pll7.
Define a round_rate() callback for these clocks, as well as fractional clocks.
Hardcode debe clocks parent to pll5.
|
| 1.7 |
| 19-Mar-2018 |
bouyer | Add some more A10/A20 clocks definitions; related to display engines.
The video PLLs requires a new clock type, SUNXI_CCU_FRACTIONAL
|
| 1.6 |
| 16-Dec-2017 |
jmcneill | branches: 1.6.2;
Add PLL1 table entry for 624 MHz
|
| 1.5 |
| 13-Nov-2017 |
jmcneill | branches: 1.5.2;
add NAND module clock
|
| 1.4 |
| 09-Oct-2017 |
jmcneill | Add A10/A20 cpufreq scaling support
|
| 1.3 |
| 07-Oct-2017 |
jmcneill | Add A10/A20 SATA support
|
| 1.2 |
| 07-Oct-2017 |
jmcneill | Add mmc sample and output phase clocks
|
| 1.1 |
| 06-Oct-2017 |
jmcneill | Add driver for sun4i (A10) and sun7i (A20) clock controller.
|
| 1.5.2.2 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.5.2.1 |
| 13-Nov-2017 |
jdolecek | file sun4i_a10_ccu.c was added on branch tls-maxphys on 2017-12-03 11:35:56 +0000
|
| 1.6.2.3 |
| 26-Jan-2019 |
pgoyette | Sync with HEAD
|
| 1.6.2.2 |
| 07-Apr-2018 |
pgoyette | Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
|
| 1.6.2.1 |
| 22-Mar-2018 |
pgoyette | Synch with HEAD, resolve conflicts
|
| 1.9.2.2 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.9.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.10.4.1 |
| 07-May-2020 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #891):
sys/arch/arm/sunxi/sun4i_a10_ccu.c: revision 1.12
Add A20 CLK_OUT_A and CLK_OUT_B clocks
|
| 1.12.2.1 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
| 1.16.16.1 |
| 02-Oct-2022 |
bouyer | Patch from Robert Swindells: start converting the A20 console driver to
drm2.
It builds but panics at boot because of missing helper functions for
debe.
|
